CN104681403A - Semiconductor and forming method thereof - Google Patents

Abstract

A semiconductor device and its forming method, wherein the forming method of the semiconductor device includes: providing a semiconductor substrate, a first interlayer dielectric layer is formed on the surface of the semiconductor substrate; forming a second interlayer dielectric layer on the surface of the first interlayer dielectric layer Two interlayer dielectric layers; simultaneously etching the second interlayer dielectric layer in the first region and the second region, forming a first groove in the second interlayer dielectric layer in the first region, and forming a first groove in the second interlayer dielectric layer in the first region, A second groove is formed in the second interlayer dielectric layer of the second region, and the first groove includes a first groove and a plurality of first through holes located at the bottom of the first groove, and adjacent first through holes There is a protrusion between them; a metal barrier layer, an insulating layer and a third metal layer are sequentially formed in the first region, the metal barrier layer covers the bottom and side walls of the first groove, and the metal barrier layer also covers the protrusion side walls and top. The invention forms the MIM capacitor while forming the interconnection structure, increases the capacitance per unit area, and saves the chip area.

Description

Semiconductor device and method of forming the same

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device and a forming method thereof.

Background technique

In VLSI, capacitors are one of the commonly used passive components, which are usually integrated into active components such as bipolar (Bipolar) transistors or complementary metal oxide semiconductor (CMOS: Complementary Metal Oxide Semiconductor) transistors.

At present, the technology of manufacturing capacitors can be divided into two types: using polysilicon as the electrode and using metal as the electrode. Using polysilicon as the electrode will cause a lack of carriers, so that when the surface voltage across the capacitor changes, the capacitance will also change. Therefore, capacitors with polysilicon electrodes cannot maintain the linearity requirements of today's logic circuits; capacitors with metal electrodes do not have the above problems. Such capacitors are generally called Metal-Insulator-Metal (MIM: Metal-Insulator-Metal) capacitors.

MIM capacitors have the advantages of high capacitance and low resistivity. In addition, in the semiconductor manufacturing process, MIM capacitors can be formed in interlayer metal and copper interconnection processes, which also reduces the difficulty and complexity of integration with CMOS front-end processes. Therefore, MIM capacitors are widely used in radio frequency circuits or high-speed analog circuits for charge storage and circuit matching.

However, with the rapid development of semiconductor manufacturing technology, in order to achieve faster computing speed, larger data storage capacity and more functions, semiconductor chips are developing towards high integration, and the size of semiconductor devices is also getting smaller and smaller. Therefore, it is more and more important to increase the capacitance per unit chip area and increase the capacitance density to save the chip area.

Contents of the invention

The problem solved by the present invention is to provide a semiconductor device and its forming method, increase the capacitance per unit chip area, save the chip area, and meet the development trend of device miniaturization.

In order to solve the above problems, the present invention provides a method for forming a semiconductor device, comprising: providing a semiconductor substrate, a first interlayer dielectric layer is formed on the surface of the semiconductor substrate, and the first interlayer dielectric layer includes a first region and the second region, the first metal layer is formed in the first interlayer dielectric layer in the first region, the second metal layer is formed in the first interlayer dielectric layer in the second region, and the first The metal layer and the second metal layer are flush with the top of the first interlayer dielectric layer; forming a second interlayer dielectric layer on the surface of the first interlayer dielectric layer; simultaneously etching the first interlayer dielectric layer in the first region and the second region Two interlayer dielectric layers, a first groove is formed in the second interlayer dielectric layer in the first region, a second groove is formed in the second interlayer dielectric layer in the second region, and the first groove is formed in the second interlayer dielectric layer in the second region. A groove includes a first groove and a plurality of first through holes located at the bottom of the first groove, with protrusions between adjacent first through holes, and the second groove includes a second groove and a plurality of first through holes located at the second The second through hole at the bottom of the groove, the bottom of the first groove and the bottom of the second groove respectively expose the surfaces of the first metal layer and the second metal layer; a metal barrier layer, an insulating layer and a second metal layer are sequentially formed in the first region Three metal layers, the metal barrier layer covers the bottom and sidewall of the first groove, the metal barrier layer also covers the sidewall and top of the protrusion; forming a fourth metal that fills the first groove layer, and the fifth metal layer filling the second groove, and the fourth metal layer covers the surface of the third metal layer.

Optionally, while forming the barrier metal layer, the insulating layer and the third metal layer in the first region, the barrier metal layer, the insulating layer and the third metal layer are formed in the second region, and the second region The metal barrier layer covers the bottom and sidewalls of the second groove.

Optionally, before forming the fourth metal layer, further steps are included: forming a photoresist layer covering the first region; using the photoresist layer as a mask, etching and removing the third metal layer and the second region Insulation.

Optionally, the material of the barrier metal layer and the third metal layer is Ta, Ti, W, TaN, TiN, WN, Co or alloys thereof.

Optionally, the barrier metal layer and the third metal layer are a single-layer structure or a multi-layer structure.

Optionally, the material of the insulating layer is SiO ₂ , SiN, SiON or high-k dielectric material.

Optionally, the material of the first metal layer, the second metal layer, the fourth metal layer and the fifth metal layer is Cu, Al, W, CuAl alloy or CuMn alloy.

Optionally, the step of forming the first groove and the second groove includes: first forming the first groove and the second groove, and then forming the first through hole and the second through hole; or first forming the first through hole holes and second through holes, and then form first trenches and second trenches.

Optionally, the process step of forming the first trench and the second trench first, and then forming the first via hole and the second via hole includes: forming a first mask layer on the surface of the second interlayer dielectric layer, so that The first mask layer in the first region has a first opening, and the first mask layer in the second region has a second opening; using the first mask layer as a mask, the first region is etched away at the same time and a second interlayer dielectric layer with a partial thickness of the second region, a first trench is formed in the first region, and a second trench is formed in the second region; at the bottom and sidewalls of the first trench , the bottom and sidewalls of the second trench, and the remaining surface of the second interlayer dielectric layer form a second mask layer, the second mask layer at the bottom of the first trench has a plurality of third openings, the first The second mask layer at the bottom of the second trench has a fourth opening; using the second mask layer as a mask, etch and remove the second interlayer dielectric layer until the surface of the first metal layer and the second metal layer are exposed , forming a plurality of first through holes in the first region, and forming second through holes in the second region.

Optionally, the process step of forming the first through hole and the second through hole first, and then forming the first trench and the second trench includes: forming a first mask layer on the surface of the second interlayer dielectric layer, so that The first mask layer in the first region has a plurality of first openings, and the first mask layer in the second region has a second opening; using the first mask layer as a mask, the first mask layer is etched and removed at the same time. The second interlayer dielectric layer in the first region and the second region, until the surfaces of the first metal layer and the second metal layer are exposed, forming a plurality of first through holes in the first region, and forming second through holes in the second region; A second mask layer is formed on the surface of the remaining second interlayer dielectric layer, the second mask layer in the first region has a third opening, the second mask layer in the second region has a fourth opening, and the third The opening exposes the first through hole, and the fourth opening exposes the second through hole; using the second mask layer as a mask, a part of the thickness of the second interlayer dielectric layer is etched away to form a first through hole in the first region. A trench, forming a second trench in the second region.

Optionally, the second interlayer dielectric layer is etched using a dry etching process.

Optionally, the dry etching process is plasma etching, and the process parameters of the plasma etching _{process are :} the etching gas includes Ar, _O2 , _CaFb and _CxHyFz gases, wherein , the flow rate of Ar is 0 sccm to 500 sccm, the flow rate of _O2 is 0 sccm to 500 sccm, the flow rate of C _a F _b is 0 sccm to 500 sccm, the flow rate of C _x H _y F _z is 0 sccm to 500 sccm, the etch chamber pressure is 10 mTorr to 100 mTorr Torr, the temperature is -20 degrees to 200 degrees, the source power is 100 watts to 1000 watts, and the bias power is 0 watts to 500 watts.

Optionally, the protrusion is formed after etching the second interlayer dielectric layer.

Optionally, the fourth metal layer and the fifth metal layer are etched, so that the tops of the fourth metal layer and the fifth metal layer are lower than the tops of the second interlayer dielectric layer.

Optionally, after forming the fourth metal layer, further include the steps of: forming a third interlayer dielectric layer on the surface of the second interlayer dielectric layer, the fourth metal layer and the fifth metal layer; etching the third layer The intermediary layer forms a third groove and a fourth groove, the bottom of the third groove exposes the fourth metal layer, and the bottom of the fourth groove exposes the fifth metal layer; the sixth metal layer of the groove, and at the same time form the seventh metal layer filling the fourth groove.

The present invention also provides a semiconductor device, comprising: a first interlayer dielectric layer located on the surface of a semiconductor substrate, the first interlayer dielectric layer includes a first region and a second region, and the first region of the first region There is a first metal layer in the interlayer dielectric layer, there is a second metal layer in the first interlayer dielectric layer in the second region, and the tops of the first metal layer and the second metal layer are flush with the top of the first interlayer dielectric layer flat; the second interlayer dielectric layer on the surface of the first interlayer dielectric layer; the first groove in the second interlayer dielectric layer in the first region, the first groove includes a first groove grooves and a plurality of first through holes at the bottom of the first trenches, with protrusions between adjacent first through holes, second grooves in the second interlayer dielectric layer in the second region, and the second The groove includes a second groove and a second through hole at the bottom of the second groove, the first through hole and the second through hole respectively expose the surface of the first metal layer and the second metal layer; The metal barrier layer on the bottom and sidewall of the groove, the insulating layer on the surface of the metal barrier layer, the third metal layer on the surface of the insulating layer, and the metal barrier layer is also located on the side wall and top of the protrusion; filled with The fourth metal layer of the first groove is filled with the fifth metal layer of the second groove.

Optionally, the bottom and sidewalls of the second groove have a metal barrier layer.

Optionally, the material of the barrier metal layer and the third metal layer is Ta, Ti, W, TaN, TiN, WN, Co or alloys thereof.

Optionally, the tops of the fourth metal layer and the fifth metal layer are lower than the tops of the second interlayer dielectric layer.

Compared with the prior art, the technical solution of the present invention has the following advantages:

The present invention provides a method for forming a semiconductor device. A first groove is formed in a second interlayer dielectric layer in a first region, and the first groove includes a first groove and multiple grooves at the bottom of the first groove. a first through hole, with protrusions between adjacent through holes; a metal barrier layer, an insulating layer and a third metal layer are sequentially formed in the first region, and the metal barrier layer covers the bottom and side walls of the first groove , the metal barrier layer also covers the top and sidewall of the protrusion; in the technical solution of the present invention, a MIM capacitor in a semiconductor device is formed in the second interlayer dielectric layer in the first region, and the metal barrier layer is a MIM capacitor The first electrode plate of the MIM capacitor, the insulating layer is the middle insulating layer of the MIM capacitor, and the third metal layer is the second electrode plate of the MIM capacitor; the overlapping area of the first electrode plate and the second electrode plate of the MIM capacitor includes: the first groove The bottom and sidewall area, raised surface and sidewall area; Compared with the prior art, the overlapping area of the first electrode plate and the second electrode plate of the MIM capacitor formed by the technical scheme of the present invention has obviously increased, therefore increases The capacitance of the MIM capacitor per unit area is increased, the capacitance density of the semiconductor device is improved, the chip area is saved, and the development trend of miniaturization and miniaturization of the semiconductor device is met.

At the same time, in the technical solution of the present invention, while forming the MIM capacitor, an interconnection structure is formed in the second interlayer dielectric layer in the second region, and the formation process of the MIM capacitor is compatible with the formation process of the interconnection structure, which improves the Improve the production efficiency of semiconductor devices and shorten the production cycle.

Further, in the technical solution of the present invention, after forming the fourth metal layer and the fifth metal layer, the fourth metal layer and the fifth metal layer are etched so that the tops of the fourth metal layer and the fifth metal layer are lower than The top of the second interlayer dielectric layer prevents electrical connection between the fourth metal layer and the fifth metal layer, improving the reliability of the semiconductor device.

The present invention also provides a semiconductor device with superior structural performance, wherein there are a plurality of first through holes in the first groove, and there are protrusions between adjacent first through holes; The bottom and side walls have a metal barrier layer, and the metal barrier layer is also located on the raised top and side walls; the metal barrier layer is the first electrode plate of the MIM capacitor in the semiconductor device, and the third metal layer is the first electrode plate of the MIM capacitor. Two electrode plates, the overlapping area of the first electrode plate and the second electrode plate includes: the bottom and side wall area of the first groove, the top and side wall area of the protrusion; compared with the prior art, this embodiment The overlapping area of the first electrode plate and the second electrode plate of the MIM capacitor is increased, thereby increasing the capacitance per unit area of the semiconductor device, increasing the capacitance density, and saving the chip area.

Further, the bottom and sidewalls of the second groove have a metal barrier layer, and the metal barrier layer prevents easily diffused metal ions in the fifth metal layer from diffusing into the second interlayer dielectric layer, thereby improving the reliability of the semiconductor device.

Furthermore, the top of the fourth metal layer and the top of the fifth metal layer are lower than the top of the second interlayer dielectric layer, thereby preventing direct electrical connection between the fourth metal layer and the fifth metal layer, further improving the reliability of semiconductor devices, and optimizing semiconductor The electrical performance of the device.

Description of drawings

1 is a schematic flow chart of a method for forming a semiconductor device according to an embodiment of the present invention;

2 to 14 are schematic cross-sectional structure diagrams of a semiconductor device formation process provided by another embodiment of the present invention.

Detailed ways

It can be seen from the background art that in order to meet the development of semiconductor chips toward high integration, it is more and more important to increase the capacitance per unit chip area.

In order to solve the above problems, the formation method of semiconductor devices is studied. At present, the most common method is to form MIM capacitors at the same time as dual damascene. Specifically, the formation method of semiconductor devices includes the following steps, please refer to Figure 1 : Step S1, providing a substrate, the substrate has a first region and a second region, the first region has a first metal layer in the substrate, the second region has a second metal layer in the substrate, and the first The tops of the metal layer and the second metal layer are flush with the top of the substrate; step S2, forming an interlayer dielectric layer covering the surface of the substrate; step S3, forming a first recess in the interlayer dielectric layer in the first region Groove, the shape of the first groove is square or U-shaped, and a second groove is formed in the interlayer dielectric layer of the second region, and the second groove is a single damascene opening or a double damascene opening; step S4, sequentially forming a metal barrier layer, an insulating layer, and a third metal layer in the first groove; step S5, forming a fourth metal layer that fills the first groove, and simultaneously forming a fourth metal layer that fills the second groove. The fifth metal layer of the recess.

In the semiconductor device formed by the above method, a MIM capacitor is formed in the first region, the metal barrier layer is the first electrode plate of the MIM capacitor, the insulating layer is an intermediate insulating layer of the MIM capacitor, and the third metal layer is the second electrode plate of the MIM capacitor . However, in the MIM capacitor in the semiconductor device formed by the above method, the overlapping area of the first electrode plate and the second electrode plate is small, resulting in a low capacitance of the formed MIM capacitor, which is difficult to meet the capacitance requirement of the semiconductor device.

Since the capacitance of the MIM capacitor is proportional to the overlapping area between the two metal electrode plates, in order to increase the capacitance in the semiconductor device, it is usually necessary to increase the overlapping area between the metal electrode plates of the MIM capacitor; and increase the overlapping area of the metal electrode plates As a result, the volume of semiconductor devices increases, which cannot meet the development trend of smaller and smaller sizes of semiconductor devices.

Therefore, the present invention provides a method for forming a semiconductor device. While forming an interconnection structure, a MIM capacitor with high capacitance is formed to increase the capacitance per unit chip area, save chip area, and meet the development of miniaturization of semiconductor devices. trend.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

2 to 14 are schematic cross-sectional structure diagrams of a semiconductor device formation process provided by another embodiment of the present invention.

Referring to FIG. 2, a semiconductor substrate (not shown) is provided, and a first interlayer dielectric layer 100 is formed on the surface of the semiconductor substrate, and the first interlayer dielectric layer 100 includes a first region I and a second region II , the first region I has a first metal layer 101 in the first interlayer dielectric layer 100, the second region II has a second metal layer 102 in the first interlayer dielectric layer 100, and the first metal layer 101 and the top of the second metal layer 102 are flush with the top of the first interlayer dielectric layer 100 .

The first region I and the second region II are respectively used to form the MIM capacitor and the interconnection structure in the semiconductor device. In this embodiment, the MIM capacitor is formed in the first region I, and the interconnection structure is formed in the second region II as an exemplary illustration. .

The material of the first interlayer dielectric layer 100 is silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity less than 4), and the low-k dielectric material Silicon hydroxide (SiOCH), boron-doped glass (BSG: Boron-Doped Silicate Glass), fluorine-doped glass (FSG: Fluorine-Doped Silicate Glass) or phosphorus-doped glass (PSG: Phosphorus-Doped Silicate Glass) .

The materials of the first metal layer 101 and the second metal layer 102 are Cu, Al, W, CuAl alloy or CuMn alloy.

Referring to FIG. 3 , a second interlayer dielectric layer 103 is formed on the surface of the first interlayer dielectric layer 100 .

The material of the second interlayer dielectric layer 103 is silicon oxide, silicon nitride, silicon oxynitride or a low-k dielectric material, and the low-k dielectric material is silicon hydroxide, boron-doped glass, fluorine-doped glass or Phosphorus-doped glass.

In this embodiment, the material of the second interlayer dielectric layer 103 is silicon oxide.

In other embodiments of the present invention, an etch barrier layer may be formed between the first interlayer dielectric layer and the second interlayer dielectric layer, and the material of the etch barrier layer is silicon oxide, silicon nitride, silicon oxynitride or silicon carbide.

Please refer to FIG. 4, a first mask layer 104 is formed on the surface of the second interlayer dielectric layer 103, the first mask layer 104 in the first region I has a first opening 105, and the second region II The second mask layer 104 has a second opening 106 .

In this embodiment, the first opening 105 defines the position of the first groove to be subsequently formed in the first region I, and the second opening 106 defines the position of the second groove to be subsequently formed in the second region II.

In this embodiment, the material of the first mask layer 104 is silicon nitride, and the thickness is 200 angstroms to 5000 angstroms.

As an embodiment, the process steps of forming the first mask layer 104 include: forming an initial mask layer on the surface of the second interlayer dielectric layer 103; forming a patterned photoresist layer on the surface of the initial mask layer; Using the patterned photoresist layer as a mask, etch the initial mask layer of the first region I to form a first opening 105, and simultaneously etch the initial mask layer of the second region I to form a second opening 106 , forming a first mask layer 104 having a first opening 105 and a second opening 106 .

In other embodiments of the present invention, the first mask layer may be a photoresist layer or a laminated structure of an anti-reflection coating and a photoresist layer.

Please refer to FIG. 5 , using the first mask layer 104 (please refer to FIG. 4 ) as a mask, the second interlayer dielectric layer 103 with a partial thickness in the first region I is etched away, and the first interlayer dielectric layer 103 is formed in the first region I. The trench 115 is etched to remove part of the thickness of the second interlayer dielectric layer 103 in the second region II at the same time, and the second trench 116 is formed in the second region II.

The formation process of the first trench 115 and the second trench 116 is dry etching. As an embodiment, the dry etching process is plasma etching, and the process parameters of the plasma etching process are: the etching gas includes Ar, O ₂ , Ca _{F b} and C _{x Hy} F _z gases, Wherein, the flow rate of _Ar is 0sccm to 500sccm, the flow rate of _O2 is 0sccm to _500sccm , the flow rate of C _a F _b is 0sccm to 500sccm, the flow rate of _CxHyFz is 0sccm to 500sccm, and the pressure of the etching chamber is 10mTorr to 100 Millitorr, temperature from -20 degrees to 200 degrees, source power from 100 watts to 1000 watts, bias power from 0 watts to 500 watts. (C _a F _b can be CF ₄ , C _x H _y F _z can be CHF ₃ or CH ₂ F ₂ )

After the first trench 115 and the second trench 116 are formed, a step is further included: removing the first mask layer 104 . In this embodiment, the first mask layer 104 is removed by a wet etching process. The etching liquid of the wet etching process is a hot phosphoric acid solution, wherein the temperature of the solution is 120 to 200 degrees, and the mass of phosphoric acid is The percentages range from 65% to 85%.

Please refer to FIG. 6 , at the bottom and sidewalls of the first trench 115 (please refer to FIG. 5 ), the bottom and sidewalls of the second trench 116 (please refer to FIG. 5 ), and the remaining second interlayer dielectric layer 103 A second mask layer 107 is formed on the surface, the second mask layer 107 at the bottom of the first trench 115 has a plurality of third openings 108, and the second mask layer 107 at the bottom of the second trench 116 has a fourth Opening 109.

The third opening 108 defines the position and diameter of the third through hole to be formed later, and the fourth opening 109 defines the position and diameter of the fourth through hole to be formed subsequently.

It should be noted that the multiple is any number of values greater than or equal to 2. In this embodiment, the second mask layer 107 at the bottom of the first trench 115 has three third openings 108 for an exemplary illustration. In other embodiments, the second mask layer at the bottom of the first trench may have 2, 4 or more third openings.

The third opening 108 exposes the bottom of the first trench 115 , and the fourth opening 109 exposes the bottom of the second trench 116 .

The formation process and steps of the second mask layer 107 can refer to the formation process and steps of the first mask layer 104 , which will not be repeated here.

Please refer to FIG. 7 , using the second mask layer 107 (please refer to FIG. 6 ) as a mask, etch and remove the second interlayer dielectric layer 103 until the surfaces of the first metal layer 101 and the second metal layer 102 are exposed. , forming a plurality of first through holes 118 in the first region I, with protrusions 120 between adjacent first through holes 118 , and forming second through holes 119 in the second region II.

It should be noted that the multiple is any number of values greater than or equal to 2. In this embodiment, three first through holes 118 are formed in the first region I for exemplary illustration. In other embodiments, 2, 4 or more first through holes are formed in the first region.

For the process of etching the second interlayer dielectric layer 103 to form the first via hole 118 and the second via hole 119 , reference may be made to the process of forming the first trench 115 and the second trench 116 in this embodiment, which will not be repeated here.

It should be noted that, in other embodiments of the present invention, an etching stopper layer is formed between the first interlayer dielectric layer and the second interlayer dielectric layer, then the second interlayer dielectric layer at the bottom of the first trench is etched and etching the barrier layer to form a first through hole, and etch the second interlayer dielectric layer and the etch barrier layer at the bottom of the second trench to form a second through hole.

In this embodiment, a first groove is formed in the second interlayer dielectric layer 103 in the first region I, and the first groove includes a first groove 115 and a plurality of grooves at the bottom of the first groove 115 A first through hole 118; a second groove is formed in the second interlayer dielectric layer 103 in the second region II, the second groove includes the second groove 116 and the second groove at the bottom of the second groove 116 Two through holes 119 ; the bottom of the first groove and the bottom of the second groove respectively expose the surfaces of the first metal layer 101 and the second metal layer 102 .

There are a plurality of first through holes 118 in the first region I, and there are protrusions 120 between adjacent first through holes 118, and the protrusions 120 are formed after etching the second interlayer dielectric layer 103; In the embodiment, a plurality of protrusions 120 are formed in the first groove, and when a MIM capacitor is subsequently formed in the first groove, the top area and the side wall area of the plurality of protrusions 120 are also the first electrode plate of the MIM capacitor. and the overlapping area between the second electrode plate, compared with the prior art, the overlapping area between the first electrode plate and the second electrode plate of the implementation MIM capacitor is significantly increased, thereby improving the capacitance of the MIM capacitor and increasing the MIM The capacitance density of the capacitor meets the development trend of miniaturization of semiconductor devices.

In this embodiment, the formation sequence of the first groove and the second groove is as follows: the first groove 115 and the second groove 116 are formed first, and then the first through hole 118 and the second through hole 119 are formed.

In other embodiments of the present invention, the order of forming the first groove and the second groove may also be: first form the first through hole and the second through hole, and then form the first groove and the second groove. Specifically, the process steps of first forming the first through hole and the second through hole, and then forming the first trench and the second trench include: forming a first mask layer on the surface of the second interlayer dielectric layer, the The first mask layer in the first region has a plurality of first openings, and the first mask layer in the second region has second openings; using the first mask layer as a mask, etch and remove the first region and the second interlayer dielectric layer in the second region until the surfaces of the first metal layer and the second metal layer are exposed, a plurality of first through holes are formed in the first region, and second through holes are formed in the second region; A second mask layer is formed on the surface of the remaining second interlayer dielectric layer, the second mask layer in the first region has a third opening, the second mask layer in the second region has a fourth opening, and the third opening exposing the first via hole, and the fourth opening exposing the second via hole; using the second mask layer as a mask, etching and removing part of the thickness of the second interlayer dielectric layer to form a first trench in the first region groove, forming a second trench in the second region.

Referring to FIG. 8, a barrier metal layer 121, an insulating layer 122 and a third metal layer 123 are sequentially formed in the first region I, and the barrier metal layer 121 covers the bottom and sidewalls of the first groove and the top of the protrusion 120. and side walls.

Since the subsequent formation of the interconnection structure in the second region, in order to prevent the easily diffused ions in the metal from diffusing into the second interlayer dielectric layer, before using the metal to fill the second groove, it is necessary to fill the bottom and side of the second groove. The walls form a metal barrier. Therefore, in order to save process cost and shorten the production cycle, while forming the barrier metal layer 121 in the first region I, the barrier metal layer 121 is formed in the second region II, and the barrier metal layer 121 covers the second region The bottom and sidewalls of the second groove.

In this embodiment, while the metal barrier layer 121, the insulating layer 122 and the third metal layer 123 are formed in the first region I, the metal barrier layer 121, the insulating layer 122 and the third metal layer 123 are formed in the second region II. Layer 123.

The metal barrier layer 121 in the first region I serves as the first electrode plate of the MIM capacitor, the insulating layer 122 in the first region I is the intermediate dielectric layer of the MIM capacitor, and the third metal layer 123 in the first region I It is the second electrode plate of the MIM capacitor. Since in this embodiment, a plurality of first through holes 118 are formed at the bottom of the first groove 115, and there are protrusions 120 between adjacent first through holes 118, the first electrode plate and the second electrode plate of the MIM capacitor The overlapping area includes: the bottom and sidewall area of the first groove, and the top and sidewall area of the protrusion 120 . Compared with the prior art, under the same chip area condition, the overlapping area of the first electrode plate and the second electrode plate of the MIM capacitor formed in this implementation is obviously increased, and the capacitance of the MIM capacitor of the chip per unit area is increased, thereby Improve the capacitance density of the MIM capacitor to meet the development trend of miniaturization and miniaturization of semiconductor devices.

The metal barrier layer 121 is a single-layer structure or a multi-layer structure, and the material of the metal barrier layer 121 is Ta, Ti, TaN, TiN, Co or their alloys; the material of the insulating layer 122 is SiO ₂ , SiN, SiON Or a high-k dielectric material, the high-k dielectric material is Ta ₂ O ₆ , TiO ₂ or Al ₂ O ₃ ; the material of the third metal layer 123 is Ta, Ti, W, Al, TiN, TaN or Co or their alloys.

In this embodiment, the metal barrier layer 121 is a single-layer structure made of Ti, with a thickness of 20 angstroms to 1000 angstroms, and the material of the insulating layer 122 is SiO ₂ , with a thickness of 20 angstroms to 1000 angstroms. The material of the three metal layers 123 is Ta, and the thickness is 20 angstroms to 1000 angstroms.

Referring to FIG. 9 , a photoresist layer 124 covering the third metal layer 123 of the first region I is formed.

As an example, the process steps of forming the photoresist layer 124 include: forming an initial photoresist layer covering the first region I and the second region II; exposing and developing the initial photoresist layer to remove The initial photoresist layer in the second region II forms a photoresist layer 124 covering the third metal layer 123 in the first region I.

Referring to FIG. 10 , using the photoresist layer 124 (please refer to FIG. 9 ) as a mask, etch and remove the third metal layer 123 and the insulating layer 122 in the second region II.

The second region II is the region where the interconnect structure is formed, and when the fourth metal is subsequently filled in the second groove, the metal needs to be electrically connected to the second metal layer 102. Therefore, before forming the fourth metal layer, The third metal layer 123 and the insulating layer 122 of the second region II need to be removed.

The third metal layer 123 and the insulating layer 122 in the second region II are etched and removed by using a dry etching process. As an embodiment, the dry etching process is reactive ion etching, and the process parameters of the reactive ion etching process are: the reactive gas includes CF ₄ , CHF ₃ and Ar, wherein the flow rate of CF ₄ is 50 sccm to 100 sccm , the CHF ₃ flow rate is 10 sccm to 50 sccm, the Ar flow rate is 100 sccm to 200 sccm, and the reaction chamber pressure is 50 mTorr to 500 mTorr.

After removing the third metal layer 123 and the insulating layer 122 in the second region II, a step is further included: removing the photoresist layer 124 located in the first region I. Specifically, the photoresist layer 124 in the first region I is removed by an ashing process, the process parameters of the ashing process are: the flow rate of oxygen is 100 sccm to 500 sccm, and the ashing temperature is 60 degrees to 300 degrees.

Referring to FIG. 11 , a fourth metal layer 125 filling the first groove and a fifth metal layer 126 filling the second groove are formed, and the fourth metal layer 125 covers the third metal layer 123 s surface.

The material of the fourth metal layer 125 and the fifth metal layer 126 is Cu, Al, W, CuAl alloy or CuMn alloy, and the formation process is physical vapor deposition or electroplating.

In this embodiment, the material of the fourth metal layer 125 and the fifth metal layer 126 is Cu, and the fourth metal layer 125 and the fifth metal layer 126 are formed by electroplating.

The first interlayer dielectric layer 100 is transferred to an electroplating reaction bath, and the fourth metal layer 125 and the fifth metal layer 126 are formed by electroplating. During the electroplating process, metallic copper fills the first groove and the second groove to form bulk copper.

There are electroplating solution, metal copper anode and positive and negative electrodes of power supply in the electroplating reaction pool. The electroplating solution is mainly composed of copper sulfate, sulfuric acid and water, and the electroplating solution also contains various additives such as catalysts, inhibitors and regulators.

The electroplating process is as follows: the third metal layer 123 in the first region I and the metal barrier layer 121 in the second region II are connected to the negative pole of the power supply, and the metal copper anode is connected to the positive pole of the power supply and is located on the metal copper anode The copper atoms in the first region I undergo an oxidation reaction to form metal copper ions, and the metal copper ions located near the surface of the third metal layer 123 in the first region I and the metal barrier layer 121 in the second region II undergo a reduction reaction, and the generated copper atoms are deposited on the A metal film is formed on the surface of the third metal layer 123 in the first region I and the metal barrier layer 121 in the second region II.

As an example, the step of forming the fourth metal layer 125 and the fifth metal layer 126 includes: forming a metal film that fills the first groove and the second groove, and the top of the metal film is higher than the second dielectric layer 103 top; remove the metal film higher than the top of the second dielectric layer 103, and simultaneously remove the third metal layer 123, the insulating layer 122 and the metal barrier layer 121 higher than the top of the second dielectric layer 103 to form a groove located in the first groove The fourth metal layer 125 and the fifth metal layer 126 in the second groove make the tops of the fourth metal layer 125 and the fifth metal layer 126 flush with the top of the second interlayer dielectric layer 103 .

The fourth metal layer 125 provides an electrical connection between the second electrode plate (third metal layer 123 ) of the MIM capacitor and the upper structure, and the fifth metal layer 126 is used to form an interconnection structure in a semiconductor device.

It should be noted that before forming the fourth metal layer, a seed layer covering the bottom and sidewalls of the first groove and the bottom and sidewalls of the second groove may also be formed, and the seed layer is used for forming the fourth metal layer. Provide a good interface state, help to form the fourth metal layer closely bonded to the seed layer, improve the electromigration of the interconnection structure, and improve the electrical performance of the semiconductor device.

It should also be noted that, in order to prevent the electrical connection between the fourth metal layer 125 of the first region I and the second region II from affecting the electrical performance of the semiconductor device, after forming the fourth metal layer 125, steps may be included: The fourth metal layer 125 and the fifth metal layer 126 are etched so that the tops of the fourth metal layer 125 and the fifth metal layer 126 are lower than the top of the second interlayer dielectric layer 103 , so as to improve the reliability of the semiconductor device.

In this embodiment, a MIM capacitor is formed in the second interlayer dielectric layer 103 in the first region I, and an interconnection structure is formed in the second interlayer dielectric layer 103 in the second region II; while the interconnection structure is formed, the MIM capacitor is formed , the MIM capacitor is compatible with the formation process of the interconnection structure.

Referring to FIG. 12 , a third interlayer dielectric layer 127 located on the surfaces of the second interlayer dielectric layer 103 , the fourth metal layer 125 and the fifth metal layer 126 is formed.

For the material and formation process of the third interlayer dielectric layer 127, reference may be made to the material and formation process of the first interlayer dielectric layer 100 provided in the embodiment of the present invention, which will not be repeated here.

In this embodiment, the material of the third interlayer dielectric layer 127 is silicon oxide, and the thickness is 500 angstroms to 10000 angstroms.

13, the third interlayer dielectric layer 127 is etched to form a third groove 128 and a fourth groove 129, the bottom of the third groove 128 exposes the fourth metal layer 125, the fourth groove The bottom of the groove 129 exposes the fifth metal layer 126 .

In this embodiment, the third groove 128 and the fourth groove 129 are double damascene openings; in other embodiments of the present invention, the third groove and the fourth groove may also be single damascene openings.

In this embodiment, the third groove 128 and the fourth groove 129 are exemplarily described as double damascene openings, and the formation process of the double damascene openings is to form trenches first and then form through holes.

The formation process of the third groove 128 and the fourth groove 129 can refer to the second groove (second through hole 119 (please refer to FIG. 7 ) and second groove 116 (please refer to FIG. 5 )) of the present invention. The forming process will not be repeated here.

Referring to FIG. 14 , a sixth metal layer is formed to fill the third groove 128 (please refer to FIG. 13 ), and a seventh metal layer is formed to fill the fourth groove 129 (please refer to FIG. 13 ).

In this embodiment, both the sixth metal layer and the seventh metal layer are multi-layer structures. Specifically, the sixth metal layer includes a sixth metal barrier layer 130 located on the bottom and side walls of the third groove 128 , and a sixth metal body located on the surface of the sixth metal barrier layer 130 and filling the third groove 128 Layer 131; the seventh metal layer includes a seventh barrier metal layer 132 located at the bottom and side walls of the fourth groove 129, and a seventh metal body located on the surface of the seventh barrier metal layer 132 and filling the fourth groove 129 Layer 133.

The function of the sixth metal barrier layer 130 and the seventh metal barrier layer 132 is to prevent the easily diffused ions in the materials of the sixth metal body layer 131 and the seventh metal body layer 133 from diffusing into the third interlayer dielectric layer 127 , thereby improving the reliability of semiconductor devices.

The materials of the sixth barrier metal layer 130 and the seventh barrier metal layer 132 are Ta, Ti, W, TaN, TiN, WN, Co or their alloys. The materials of the sixth metal body layer 131 and the seventh metal body layer 133 are Cu, Al, W, CuAl alloy or CuMn alloy.

The sixth metal layer provides electrical connection for the MIM capacitor in the semiconductor device and the peripheral structure, and the seventh metal layer provides electrical connection for the interconnection structure in the semiconductor device and the peripheral structure.

In summary, the technical solution of the method for forming a semiconductor device provided by the present invention has the following advantages:

First, a first groove is formed in the second interlayer dielectric layer in the first region, and the first groove includes a first trench and a plurality of first via holes located at the top of the first trench; in the first A metal barrier layer, an insulating layer and a third metal layer are sequentially formed in the region, and the metal barrier layer covers the bottom and side walls of the first groove; in this embodiment, the metal barrier layer is the first electrode of the MIM capacitor of the formed semiconductor device plate, the insulating layer is the middle insulating layer of the MIM capacitor, and the third metal layer is the second electrode plate of the MIM capacitor; since the first groove is composed of the first trench and a plurality of first through holes at the bottom of the first trench , there is a protrusion (formed after etching the second interlayer dielectric layer) between adjacent first through holes, the overlapping area of the first electrode plate and the second electrode plate includes the bottom and sidewall area of the first groove In addition, it also includes the raised top and side wall areas; compared with the prior art, the overlapping area of the first electrode plate and the second electrode plate of the MIM capacitor in the embodiment of the present invention is significantly increased, and the capacitance density of the MIM capacitor is obtained. Obvious improvement, thereby increasing the capacitance of the MIM capacitor per unit chip area, meeting the development trend of device miniaturization.

Secondly, in this embodiment, while forming the second groove in the second region, the first groove in the first region is formed, and the same mask is used for the formation of the first groove and the second groove layer; the MIM capacitor is formed while forming the interconnection structure of the semiconductor device, which saves the process cost and shortens the production cycle of the semiconductor device.

Again, in this embodiment, while the metal barrier layer is formed in the first region, a metal barrier layer is formed on the bottom and sidewalls of the second groove in the second region to prevent the easily diffused metal ions in the subsequently formed fifth metal layer. Diffusion into the second interlayer dielectric layer, thereby improving the reliability of the interconnection structure of the semiconductor device and optimizing the electrical performance of the semiconductor device.

Moreover, in the embodiment of the present invention, after forming the fourth metal layer and the fifth metal layer, etching removes part of the thickness of the fourth metal layer and the fifth metal layer, so that the top of the fourth metal layer and the top of the fifth metal layer are lower On the top of the second interlayer dielectric layer, direct electrical connection between the fourth metal layer and the fifth metal layer is avoided, thereby improving the reliability of the semiconductor device.

Please continue to refer to FIG. 11 , an embodiment of the present invention also provides a semiconductor device, including:

The first interlayer dielectric layer 100 located on the surface of the semiconductor substrate, the first interlayer dielectric layer 100 includes a first region I and a second region II, and the first interlayer dielectric layer 100 in the first region I There is a first metal layer 101, a second metal layer 102 is provided in the first interlayer dielectric layer 100 in the second region II, and the tops of the first metal layer 101 and the second metal layer 102 are connected to the first interlayer dielectric layer 100 flush at the top;

a second interlayer dielectric layer 103 located on the surface of the first interlayer dielectric layer 100;

A first groove located in the second interlayer dielectric layer 103 in the first region I, the first groove includes a first trench and a plurality of first via holes at the bottom of the first trench, adjacent to There is a protrusion 120 between the first through holes, and a second groove located in the second interlayer dielectric layer 103 in the second region II, the second groove includes a second trench and a bottom of the second trench. a second through hole, the first through hole and the second through hole respectively expose the surfaces of the first metal layer 101 and the second metal layer 102;

The metal barrier layer 121 located on the bottom and sidewall of the first groove, the insulating layer 122 located on the surface of the metal barrier layer 121, the third metal layer 123 located on the surface of the insulating layer 122, and the metal barrier layer 123 is also located on the The sidewall and top of the protrusion 120 are filled with the fourth metal layer 125 of the first groove, and the fifth metal layer 126 of the second groove is filled.

The material of the first interlayer dielectric layer 100 and the second interlayer dielectric layer 103 is silicon oxide, silicon nitride, silicon oxynitride or a low-k dielectric material, and the low-k dielectric material is carbon silicon hydroxide, boron-doped glass, fluorine-doped glass, or phosphorous-doped glass. The material of the protrusion 120 is the same as that of the second interlayer dielectric layer 103 .

The material of the metal barrier layer 121 and the third metal layer 123 is Ta, Ti, W, TaN, TiN, WN, Co or their alloys, and the metal barrier layer 121 is a single-layer structure or a laminated structure.

The material of the insulating layer 122 is SiO ₂ , SiN, SiON or high-k dielectric material.

The materials of the first metal layer 101 , the second metal layer 102 , the fourth metal layer 125 and the fifth metal layer 126 are Cu, Al, W, CuAl alloy or CuMn alloy.

As a specific embodiment, the material of the first interlayer dielectric layer 100 and the second interlayer dielectric layer 103 is silicon oxide; the material of the metal barrier layer 121 is Ti, with a thickness of 20 angstroms to 1000 angstroms; The insulating layer 122 is made of silicon oxide, with a thickness of 20 angstroms to 1000 angstroms; the material of the third metal layer 123 is Ta, with a thickness of 20 angstroms to 1000 angstroms; the fourth metal layer 125 and the fifth metal layer 126 The material is Cu.

It should be noted that, in order to prevent electrical connection between the fourth metal layer 125 and the fifth metal layer 126, the top of the fourth metal layer 125 and the top of the fifth metal layer 126 may be lower than the top of the second interlayer dielectric layer 103 ; In order to prevent easily diffused metal ions in the fifth metal layer 126 from diffusing into the second interlayer dielectric layer 103 , the bottom and sidewalls of the second groove have a metal barrier layer 121 .

In this embodiment, the barrier metal layer 121 , the insulating layer 122 and the third metal layer 123 in the first region I are respectively the first electrode plate, the intermediate insulating layer and the second electrode plate of the MIM capacitor in the semiconductor device. The overlapping area of the first electrode plate and the second electrode plate includes: the bottom and side wall area of the first groove, the top and side wall area of the protrusion; compared with the prior art, in this embodiment, the first electrode plate and the side wall area The overlapping area of the second electrode plate is significantly increased, thereby increasing the capacitance per unit area of the semiconductor device, saving chip area, and meeting the development trend of miniaturization and miniaturization of the semiconductor device.

In summary, the technical solution of the semiconductor device provided by the present invention has the following advantages:

First of all, the semiconductor device in this embodiment has superior structural performance, wherein there are a plurality of first through holes in the first groove, and there are protrusions between adjacent first through holes; There is a metal barrier layer, and the metal barrier layer is also located on the top and sidewall of the protrusion; the metal barrier layer is the first electrode plate of the MIM capacitor in the semiconductor device, and the third metal layer is the second electrode plate of the MIM capacitor, The overlapping area of the first electrode plate and the second electrode plate includes: the bottom and side wall area of the first groove, the top and side wall area of the protrusion; compared with the prior art, this embodiment increases the MIM capacitor The overlapping area of the first electrode plate and the second electrode plate increases the capacitance per unit area of the semiconductor device, increases the capacitance density, and saves the chip area.

Secondly, in this embodiment, the bottom and sidewalls of the second groove have a metal barrier layer, and the metal barrier layer blocks the easy-to-diffuse metal ions in the fifth metal layer from diffusing into the second interlayer dielectric layer, improving the semiconductor device. reliability.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (19)

1. a formation method for semiconductor device, is characterized in that, comprising:

Semiconductor substrate is provided, described semiconductor substrate surface is formed with the first interlayer dielectric layer, described first interlayer dielectric layer comprises first area and second area, the first metal layer is formed in first interlayer dielectric layer of described first area, be formed with the second metal level in first interlayer dielectric layer of described second area, and described the first metal layer and the second metal level flush with the first interlayer dielectric layer top;

Between described ground floor, dielectric layer surface forms the second interlayer dielectric layer;

Etch the second interlayer dielectric layer of described first area and second area simultaneously, the first groove is formed in the second interlayer dielectric layer of described first area, the second groove is formed in the second interlayer dielectric layer of described second area, and described first groove comprises the first groove and is positioned at multiple first through holes of the first channel bottom, between adjacent first through hole, there is projection, described second groove comprises the second groove and is positioned at the second through hole of the second channel bottom, and described first bottom portion of groove and the second bottom portion of groove expose the first metal layer and the second layer on surface of metal respectively;

Form metal barrier, insulating barrier and the 3rd metal level successively in first area, described metal barrier covers bottom and the sidewall of the first groove, and described metal barrier also covers sidewall and the top of described projection;

Form the 4th metal level of filling full described first groove and the 5th metal level of filling full second groove, and described 4th metal level is covered in the surface of the 3rd metal level.

2. the formation method of semiconductor device according to claim 1, it is characterized in that, while described first area forms metal barrier, insulating barrier and the 3rd metal level, form metal barrier, insulating barrier and the 3rd metal level at described second area, and described second area metal barrier covers bottom and the sidewall of the second groove.

3. the formation method of semiconductor device according to claim 2, is characterized in that, before formation the 4th metal level, also comprises step: form the photoresist layer covering first area; With described photoresist layer for mask, etching removes the 3rd metal level and insulating barrier of second area.

4. the formation method of semiconductor device according to claim 1, is characterized in that, the material of described metal barrier and the 3rd metal level is Ta, Ti, W, TaN, TiN, WN, Co or their alloy.

5. the formation method of semiconductor device according to claim 1, is characterized in that, described metal barrier and the 3rd metal level are single layer structure or sandwich construction.

6. the formation method of semiconductor device according to claim 1, is characterized in that, the material of described insulating barrier is SiO ₂, SiN, SiON or high K medium material.

7. the formation method of semiconductor device according to claim 1, is characterized in that, the material of described the first metal layer, the second metal level, the 4th metal level and the 5th metal level is Cu, Al, W, CuAl alloy or CuMn alloy.

8. the formation method of semiconductor device according to claim 1, is characterized in that, the forming step of described first groove and the second groove comprises: first form the first groove and the second groove, rear formation first through hole and the second through hole; Or first form the first through hole and the second through hole, rear formation first groove and the second groove.

9. the formation method of semiconductor device according to claim 8, it is characterized in that, first form the first groove and the second groove, the processing step of rear formation first through hole and the second through hole comprises: between the described second layer, dielectric layer surface forms the first mask layer, first mask layer of described first area has the first opening, and the first mask layer of described second area has the second opening; With described first mask layer for mask, etching off removes the second interlayer dielectric layer of the segment thickness of first area and second area in the same time, forms the first groove, form the second groove at described second area in described first area; Between described first channel bottom and sidewall, the second channel bottom and sidewall and the remaining second layer, dielectric layer surface forms the second mask layer, second mask layer of described first channel bottom has multiple 3rd opening, and the second mask layer of described second channel bottom has the 4th opening; With described second mask layer for mask, etching removal second interlayer dielectric layer, until expose the first metal layer and the second layer on surface of metal, forms multiple first through hole, forms the second through hole at second area in first area.

10. the formation method of semiconductor device according to claim 8, it is characterized in that, first form the first through hole and the second through hole, the processing step of rear formation first groove and the second groove comprises: between the described second layer, dielectric layer surface forms the first mask layer, first mask layer of described first area has multiple first opening, and the first mask layer of described second area has the second opening; With described first mask layer for mask, etching off removes the second interlayer dielectric layer of first area and second area in the same time, until expose the first metal layer and the second layer on surface of metal, forms multiple first through hole, form the second through hole at second area in first area; Between the remaining second layer, dielectric layer surface forms the second mask layer, second mask layer of first area has the 3rd opening, second mask layer of second area has the 4th opening, and described 3rd opening exposes the first through hole, and the 4th opening exposes the second through hole; With described second mask layer for mask, etching removes the second interlayer dielectric layer of segment thickness, forms the first groove, form the second groove at second area in first area.

The formation method of 11. semiconductor device according to claim 9 or 10, is characterized in that, adopts described second interlayer dielectric layer of dry etch process etching.

The formation method of 12. semiconductor device according to claim 11, is characterized in that, described dry etch process is plasma etching, and the technological parameter of plasma etch process is: etching gas comprises Ar, O ₂, C _af _band C _xh _yf _zgas, wherein, Ar flow is 0sccm to 500sccm, O ₂flow is 0sccm to 500sccm, C _af _bflow is 0sccm to 500sccm, C _xh _yf _zflow is 0sccm to 500sccm, and etching cavity pressure is 10 millitorr to 100 millitorrs, temperature be-20 degree to 200 degree, source power is 100 watts to 1000 watts, and bias power is 0 watt to 500 watts.

The formation method of 13. semiconductor device according to claim 1, is characterized in that, described projection is formed after dielectric layer between etching of second layer.

The formation method of 14. semiconductor device according to claim 1, is characterized in that, etches described 4th metal level and the 5th metal level, makes the 4th metal level top and the 5th metal level top lower than the second interlayer dielectric layer top.

The formation method of 15. semiconductor device according to claim 1, is characterized in that, after formation the 4th metal level, also comprises step: formed be positioned at the second interlayer dielectric layer, the 4th metal level and the 5th layer on surface of metal third layer between dielectric layer; Etch dielectric layer between described third layer and form the 3rd groove and the 4th groove, described 3rd bottom portion of groove exposes the 4th metal level, and described 4th bottom portion of groove exposes the 5th metal level; Form the 6th metal level of filling full described 3rd groove, form the 7th metal level of filling full described 4th groove simultaneously.

16. 1 kinds of semiconductor device, is characterized in that, comprising:

Be positioned at the first interlayer dielectric layer of semiconductor substrate surface, described first interlayer dielectric layer comprises first area and second area, and in the first interlayer dielectric layer of described first area, there is the first metal layer, in first interlayer dielectric layer of second area, there is the second metal level, and described the first metal layer and the second metal level top flush with the first interlayer dielectric layer top;

Be positioned at the second interlayer dielectric layer of dielectric layer surface between described ground floor;

Be positioned at the first groove of the second interlayer dielectric layer of described first area, described first groove comprises the first groove and is positioned at multiple first through holes of the first channel bottom, between adjacent first through hole, there is projection, be positioned at the second groove of the second interlayer dielectric layer of second area, described second groove comprises the second groove and is positioned at the second through hole of the second channel bottom, and described first through hole and the second through hole expose the first metal layer and the second layer on surface of metal respectively;

The metal barrier being positioned at described first bottom portion of groove and sidewall, the insulating barrier being positioned at metal barrier surface, be positioned at the 3rd metal level of surface of insulating layer, and described metal barrier is also positioned at sidewall and the top of described projection;

Fill the 4th metal level of full described first groove, fill the 5th metal level of full described second groove.

17. semiconductor device according to claim 16, is characterized in that, bottom and the sidewall of the second groove have metal barrier.

18. semiconductor device according to claim 16, is characterized in that, the material of described metal barrier and the 3rd metal level is Ta, Ti, W, TaN, TiN, WN, Co or their alloy.

19. semiconductor device according to claim 16, is characterized in that, described 4th metal level top and the 5th metal level top are lower than the second interlayer dielectric layer top.