CN108364857B - Preparation method of semiconductor chip protective layer and semiconductor chip - Google Patents
Preparation method of semiconductor chip protective layer and semiconductor chip Download PDFInfo
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Abstract
本发明适用于半导体技术领域，提供了一种半导体芯片保护层的制备方法和半导体芯片，该方法包括：在半导体芯片第一区域的上表面形成第一SiN层；其中，所述第一区域包括压点之外的区域，或所述第一区域包括所述压点之外的区域和所述压点的边缘区域；在所述第一SiN层的上表面形成有机聚合物层；在所述有机聚合物层的上表面和侧壁形成第二SiN层；其中，所述第一SiN层和所述第二SiN层完全包裹所述有机聚合物层。本发明能够显著提高半导体芯片的抗潮气性能。
The present invention is applicable to the field of semiconductor technology, and provides a method for preparing a protective layer of a semiconductor chip and a semiconductor chip. The method includes: forming a first SiN layer on the upper surface of a first region of the semiconductor chip; wherein the first region includes The area outside the pressure point, or the first area includes the area outside the pressure point and the edge area of the pressure point; an organic polymer layer is formed on the upper surface of the first SiN layer; The upper surface and sidewalls of the organic polymer layer form a second SiN layer; wherein the first SiN layer and the second SiN layer completely wrap the organic polymer layer. The invention can significantly improve the moisture resistance of the semiconductor chip.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a preparation method of a semiconductor chip protective layer and a semiconductor chip.
Background
A semiconductor chip refers to a semiconductor device fabricated by a semiconductor process on a semiconductor sheet. Semiconductor chips are often subjected to high temperature, high humidity, high pressure, etc. during use, which greatly affects the stability and reliability of the devices. For example, during the use of the GaN field effect transistor, water vapor can enter the active region through the protective layer on the surface of the chip, and once water molecules enter the periphery of the grid bars, corrosion can be caused, so that the performance of the device is degraded, and even the tube core is directly burned. Therefore, to prevent moisture intrusion and ion contamination, a layer of SiN dielectric is usually deposited on the surface of the semiconductor chip. However, the SiN dielectric layer is brittle and is prone to crack when being subjected to mechanical impact, and the SiN dielectric layer is prone to generate large stress and even crack after the thickness of the SiN dielectric layer is larger than 1 micron, so that the moisture resistance of the device is affected.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method for preparing a semiconductor chip protection layer and a semiconductor chip, so as to solve the problem that the protection layer on the surface of the semiconductor chip is prone to generate cracks to affect the moisture resistance of the device in the prior art.
A first aspect of an embodiment of the present invention provides a method for preparing a semiconductor chip protection layer, including:
forming a first SiN layer on the upper surface of a first region of a semiconductor chip; wherein the first region comprises a region other than a pressure point, or the first region comprises a region other than the pressure point and an edge region of the pressure point;
forming an organic polymer layer on an upper surface of the first SiN layer;
forming a second SiN layer on the upper surface and the side wall of the organic polymer layer; wherein the first SiN layer and the second SiN layer completely wrap the organic polymer layer.
Optionally, the forming a first SiN layer on the upper surface of the first region of the semiconductor chip includes:
forming a first SiN layer on the upper surface of the semiconductor chip;
coating a first photoresist layer on the upper surface of the first SiN layer corresponding to the first region through a photoetching process;
etching the first SiN layer through an etching process;
and removing the first photoresist layer.
Optionally, the organic polymer is a non-photosensitive material; forming an organic polymer layer on an upper surface of the first SiN layer, including:
coating an organic polymer layer on the upper surface of the semiconductor chip after the first SiN layer is formed;
coating a second photoresist layer on the upper surface of the portion of the organic polymer layer corresponding to the first region through a photolithography process;
etching the organic polymer layer by an etching process;
and removing the second photoresist layer.
Optionally, the organic polymer is a photosensitive material; forming an organic polymer layer on an upper surface of the first SiN layer, including:
coating an organic polymer layer on the upper surface of the semiconductor chip after the first SiN layer is formed;
and sequentially exposing, developing and hardening to remove the organic polymer layer corresponding to the region except the first region.
Optionally, forming a second SiN layer on the upper surface of the organic polymer layer includes:
forming a second SiN layer on the upper surface of the semiconductor chip after the organic polymer layer is formed;
covering a third photoresist layer on the upper surface of the part, corresponding to the first region, of the second SiN layer through a photoetching process;
etching the second SiN layer through an etching process;
and removing the third photoresist layer.
Optionally, the thickness of the first SiN layer is 300 nm to 800 nm; the organic polymer layer has a thickness of 3 to 5 microns; the thickness of the second SiN layer is 300-800 nm.
Optionally, the organic polymer layer is made of polyimide, polychlorinated biphenyl or poly-p-phenylene benzobisoxazole.
Optionally, the organic polymer layer has a relative dielectric constant of 2.7 to 3.0.
Optionally, the first SiN layer and the second SiN layer are grown by a plasma enhanced chemical vapor deposition method, respectively.
A second aspect of the embodiments of the present invention provides a semiconductor chip, including a semiconductor chip body, where a first SiN layer is disposed on an upper surface of a first region of the semiconductor chip body, an organic polymer layer is disposed on an upper surface of the first SiN layer, and a second SiN layer is disposed on an upper surface and a sidewall of the organic polymer layer; wherein the first SiN layer and the second SiN layer completely wrap the organic polymer layer; the first region includes a region other than the pressure point, or the first region includes a region other than the pressure point and an edge region of the pressure point.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: according to the embodiment of the invention, the first SiN layer, the organic polymer layer and the second SiN layer are sequentially formed on the upper surface of the first region of the semiconductor chip, the organic polymer layer is completely wrapped by the first SiN layer and the second SiN layer, the thickness of the protective layer can be increased by the three-layer composite layer structure of the first SiN layer, the organic polymer layer and the second SiN layer, the invasion of moisture can be effectively prevented, the organic polymer layer has the surface planarization effect, cracks can be prevented from being generated on the first SiN layer at the edge of the chip when an external force acts on the first SiN layer, and therefore, the moisture resistance of the semiconductor chip can be obviously improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of a method for manufacturing a protective layer of a semiconductor chip according to an embodiment of the present invention;
fig. 2 is a schematic flow chart illustrating an implementation of a method for manufacturing a semiconductor chip protection layer according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a semiconductor chip according to a second embodiment of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
In order to explain the technical means of the present invention, the following description will be given by way of specific examples.
The semiconductor chip according to the embodiment of the present invention is a semiconductor device manufactured by a semiconductor process on a semiconductor sheet, and includes, but is not limited to, a GaN chip, a Si chip, and a SiC chip. The semiconductor devices prepared include, but are not limited to, Field Effect Transistors (FETs), High Electron Mobility Transistors (HEMTs), diodes, and triodes.
Example one
Referring to fig. 1(1), fig. 1 shows a schematic structural diagram of only a portion of a semiconductor chip. The semiconductor chip 100 includes a substrate 101, pressure points 102, and a pattern region 103. The pressure point 102 is an energized region of the semiconductor device, and does not need to be covered by a protective layer, and the pattern region 103 is a preparation region of the semiconductor device.
Referring to fig. 2, a method for preparing a semiconductor chip protection layer includes:
step S201, forming a first SiN layer on the upper surface of a first region of a semiconductor chip; wherein the first region includes a region other than a pressure point, or the first region includes a region other than the pressure point and an edge region of the pressure point.
In the embodiment of the present invention, please refer to fig. 1(2), the first SiN layer 104 is covered on the upper surface of the first region of the semiconductor chip through the photolithography process and the etching process, and the thickness of the first SiN layer 104 is 300 nm to 800 nm. In one implementation, the area outside the pressure point 102 is covered with a protective layer to expose the pressure point, and in another implementation, the area outside the pressure point 102 and the edge area of the pressure point 102 are covered with a protective layer to expose the middle area of the pressure point 102.
Optionally, the specific implementation method of step S201 is: forming a first SiN layer on the upper surface of the semiconductor chip; coating a first photoresist layer on the upper surface of the first SiN layer corresponding to the first region through a photoetching process; etching the first SiN layer through an etching process; and removing the first photoresist layer.
In the embodiment of the invention, the semiconductor chip is firstly cleaned to obtain a clean semiconductor chip surface, then a first SiN layer is grown on the upper surface of the semiconductor chip by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, then a first photoresist layer is covered on the upper surface of the part of the first SiN layer corresponding to the first region through gluing, exposing, developing and hardening processes to expose a region to be etched, then the first SiN layer is etched by reactive ion etching or inductive coupling Plasma etching, the first SiN layer covered by the photoresist layer cannot be etched due to the protection of the photoresist, but the first SiN layer not covered by the photoresist layer is etched, finally the first photoresist layer is removed, and a first SiN layer is formed on the upper surface of the first region of the semiconductor chip.
Step S202, an organic polymer layer is formed on the upper surface of the first SiN layer.
Referring to fig. 1(3), an organic polymer layer 105 is formed on the upper surface of the first SiN layer 104. The organic polymer layer 105 is made of Polyimide (PI), polychlorinated biphenyl (PCB), or Poly-p-phenylene ben-zobisthiazole (PBO). The organic polymer layer 105 has a thickness of 3 to 5 micrometers. On the one hand, the organic polymer layer 105 can increase the thickness of the whole protective layer, and on the other hand, the organic polymer layer 105 has the function of surface planarization, and can prevent the first SiN layer 104 at the edge of the chip from generating cracks when external force acts.
Alternatively, the organic polymer layer 105 has a relative dielectric constant of 2.7 to 3.0. The organic polymer layer 105 has a low relative dielectric constant, which can reduce the parasitic parameters of the semiconductor chip.
Optionally, the organic polymer is a non-photosensitive material. The specific implementation manner of step S202 is: coating an organic polymer layer on the upper surface of the semiconductor chip after the first SiN layer is formed; covering a second photoresist layer on the upper surface of the part of the organic polymer layer corresponding to the first region through a photoetching process; etching the organic polymer layer by an etching process; and removing the second photoresist layer.
In the embodiment of the present invention, when the organic polymer is a non-photosensitive material, the organic polymer layer is formed through a photolithography and etching process. Firstly, an organic polymer layer is coated on the upper surface of the semiconductor chip after the first SiN layer is formed through a spraying method or a spin coating method, then, a second photoresist layer covers the upper surface of the part, corresponding to the first area, of the organic polymer layer through gluing, exposing, developing and hardening processes, the area to be etched is exposed, and the semiconductor chip is hardened at 300-350 ℃ for 1-2 hours, so that organic solvents can be fully removed, and crosslinking is promoted. And etching the organic polymer layer by reactive ion etching or inductively coupled plasma etching, wherein the organic polymer layer covered by the photoresist layer is protected by the photoresist and cannot be etched, and the organic polymer layer not covered by the photoresist layer is etched. And finally, removing the second photoresist layer and forming an organic polymer layer on the upper surface of the first SiN layer.
Optionally, the organic polymer is a photosensitive material. The specific implementation method of step S202 is: coating an organic polymer layer on the upper surface of the semiconductor chip after the first SiN layer is formed; and sequentially exposing, developing and hardening to remove the organic polymer layer corresponding to the region except the first region.
In the embodiment of the present invention, when the organic polymer is a photosensitive material, the organic polymer layer corresponding to the region other than the first region can be removed only by exposing, developing, and hardening.
Step S203, forming a second SiN layer on the upper surface and the side wall of the organic polymer layer; wherein the first SiN layer and the second SiN layer completely wrap the organic polymer layer.
In the embodiment of the present invention, referring to fig. 1(4), a second SiN layer 106 is formed on the upper surface and the sidewall of the organic polymer layer 105, so that the first SiN layer 104 and the second SiN layer 106 completely wrap the organic polymer layer 105 to form a protective layer having a three-layer composite structure, which can allow water vapor to penetrate through the protective layer to erode the semiconductor chip. The thickness of the second SiN layer 106 is 300 nm to 800 nm.
Optionally, the specific implementation manner of step S203 is: forming a second SiN layer on the upper surface of the semiconductor chip after the organic polymer layer is formed; covering a third photoresist layer on the upper surface of the part, corresponding to the first region, of the second SiN layer through a photoetching process; etching the second SiN layer through an etching process; and removing the third photoresist layer.
In the embodiment of the present invention, the second SiN layer is formed by a photolithography process and an etching process, and a forming method of the second SiN layer is the same as a forming method of the first SiN layer, which is not described herein again.
According to the embodiment of the invention, the first SiN layer, the organic polymer layer and the second SiN layer are sequentially formed on the upper surface of the first region of the semiconductor chip, the organic polymer layer is completely wrapped by the first SiN layer and the second SiN layer, the thickness of the protective layer can be increased by the three-layer composite layer structure of the first SiN layer, the organic polymer layer and the second SiN layer, the invasion of moisture can be effectively prevented, the organic polymer layer has the surface planarization effect, cracks can be prevented from being generated on the first SiN layer at the edge of the chip when an external force acts on the first SiN layer, and therefore, the moisture resistance of the semiconductor chip can be obviously improved.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
Example two
Referring to fig. 3, fig. 3 is a cross-sectional view of a portion of a semiconductor chip. The semiconductor chip comprises a semiconductor chip body, wherein a first SiN layer is arranged on the upper surface of a first region of the semiconductor chip body, an organic polymer layer is arranged on the upper surface of the first SiN layer, and second SiN layers are arranged on the upper surface and the side wall of the organic polymer layer; wherein the first SiN layer and the second SiN layer completely wrap the organic polymer layer; the first region includes a region other than the pressure point, or the first region includes a region other than the pressure point and an edge region of the pressure point.
In the embodiment of the present invention, the semiconductor chip body includes a substrate 101, a pressure point 102, and a pattern region 103. In one implementation, the protective layer covers the area outside the pressure point 102, and in another implementation, the protective layer covers the area outside the pressure point 102 and the edge area of the pressure point 102.
According to the embodiment of the invention, the first SiN layer, the organic polymer layer and the second SiN layer are arranged on the upper surface of the first region of the semiconductor chip, the organic polymer layer is completely wrapped by the first SiN layer and the second SiN layer, the thickness of the protective layer can be increased by the three-layer composite layer structure of the first SiN layer, the organic polymer layer and the second SiN layer, the invasion of moisture can be effectively prevented, the organic polymer layer has the effect of surface planarization, cracks can be prevented from being generated on the first SiN layer at the edge of the chip when external force acts, and therefore, the moisture resistance of the semiconductor chip can be obviously improved.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
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| WO2012086334A1 (en) * | 2010-12-22 | 2012-06-28 | Jsr株式会社 | Light-emitting body and display device |
| CN103035492A (en) * | 2012-05-28 | 2013-04-10 | 上海华虹Nec电子有限公司 | Manufacturing method for double protection layers in semiconductor device |
| CN103325951A (en) * | 2013-06-21 | 2013-09-25 | 深圳市华星光电技术有限公司 | Electroluminescent diode device |
| CN104681403A (en) * | 2013-11-26 | 2015-06-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor and forming method thereof |
| CN206022345U (en) * | 2016-08-16 | 2017-03-15 | 厦门市三安集成电路有限公司 | A kind of semiconductor structure with composite protection layer |
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| JPH05190533A (en) * | 1992-01-16 | 1993-07-30 | Oki Electric Ind Co Ltd | Surface protective film of semiconductor element and manufacture method thereof |
| JP3989761B2 (en) * | 2002-04-09 | 2007-10-10 | 株式会社半導体エネルギー研究所 | Semiconductor display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2012086334A1 (en) * | 2010-12-22 | 2012-06-28 | Jsr株式会社 | Light-emitting body and display device |
| CN103035492A (en) * | 2012-05-28 | 2013-04-10 | 上海华虹Nec电子有限公司 | Manufacturing method for double protection layers in semiconductor device |
| CN103325951A (en) * | 2013-06-21 | 2013-09-25 | 深圳市华星光电技术有限公司 | Electroluminescent diode device |
| CN104681403A (en) * | 2013-11-26 | 2015-06-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor and forming method thereof |
| CN206022345U (en) * | 2016-08-16 | 2017-03-15 | 厦门市三安集成电路有限公司 | A kind of semiconductor structure with composite protection layer |
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