CN104638024B - A kind of horizontal current regulator diode and its manufacture method based on SOI - Google Patents

Abstract

The invention provides an SOI-based lateral constant current diode and a manufacturing method thereof, belonging to the technical field of semiconductor power devices. The SOI-based lateral constant current diode is formed by a plurality of interdigitated cells with the same structure, and the cells include a substrate, an N-type lightly doped silicon, a P-type heavily doped region, and an N-type heavily doped region. , oxide dielectric layer, metal cathode, metal anode, P-type doped region, buried oxide layer; the P-type heavily doped region is located between the N-type heavily doped region and the P-type doped region, and the N-type heavily doped region part Included in the P-type heavily doped region, the N-type heavily doped region is short-circuited with the P-type heavily doped region and is in ohmic contact with the metal cathode, and the P-type doped region is in ohmic contact with the metal anode. The constant current diode of the present invention adopts a PN junction short-circuit structure, which can reduce chip area and cost; meanwhile, adopts SOI technology, which can effectively prevent adverse effects caused by substrate leakage current in an integrated system.

Description

A SOI-based lateral constant current diode and its manufacturing method

technical field

The invention belongs to the technical field of semiconductor power devices, and in particular relates to an SOI-based lateral constant current diode and a manufacturing method thereof.

Background technique

The constant current source is a commonly used electronic equipment and device, and it is widely used in electronic circuits. The constant current source is used to protect the entire circuit, even if the voltage is unstable or the load resistance changes greatly, it can ensure the stability of the supply current. A constant current diode (CRD, Current Regulative Diode) is a semiconductor constant current device, that is, a diode is used as a constant current source instead of an ordinary constant current source composed of transistors, Zener tubes and resistors. Currently, constant current diodes The output current is between a few milliamps and tens of milliamperes, which can directly drive the load, achieving the purpose of simple circuit structure, small device size and high device reliability. In addition, the peripheral circuit of the constant current diode is very simple and easy to use, and has been widely used in automatic control, instrumentation, protection circuits and other fields. However, the current high breakdown voltage of constant current diodes is generally 30-100V, so there is a problem of low breakdown voltage, and the constant current that can be provided is also low.

Contents of the invention

Aiming at the problems of high pinch-off voltage, low breakdown voltage and poor constant current capability of the constant current diode, the invention proposes an SOI-based lateral constant current diode and a manufacturing method thereof. The SOI-based lateral constant current diode provided by the present invention adopts a PN junction short-circuit structure, which can reduce the chip area and cost, and reducing the chip area is equivalent to increasing the current density of the chip when the constant current is the same, so that The constant current capability of the device is improved; the present invention adopts SOI (Silicon-On-Insulator, silicon on insulating substrate) technology, which can effectively prevent the adverse effects caused by the substrate leakage current in the integrated system, and can utilize dual load The carrier conduction increases the current density of the device, makes the linear region of the device steeper, and the pinch-off voltage is below 5V.

Technical scheme of the present invention is as follows:

An SOI-based lateral constant current diode, formed by interdigitated connection of multiple cells with the same structure, the cells include a substrate 2, an N-type lightly doped silicon 3 on an insulating layer, and a P-type heavily doped region 4 , an N-type heavily doped region 5, an oxide medium layer 6, a metal cathode 7, a metal anode 8, a P-type doped region 9, and a buried oxide layer 10; the buried oxide layer 10 is located on the substrate 2, and the N Type lightly doped silicon 3 is located on the buried oxide layer 10, and the P-type heavily doped region 4, N-type heavily doped region 5 and P-type doped region 9 are located in the N-type lightly doped silicon 3, so The P-type heavily doped region 4 is located between the N-type heavily doped region 5 and the P-type doped region 9, and the N-type heavily doped region 5 is partly included in the P-type heavily doped region 4. The N-type heavily doped region 5 is short-circuited with the P-type heavily doped region 4 and forms an ohmic contact with the metal cathode 7 , and the P-type doped region 9 forms an ohmic contact with the metal anode 8 .

Further, the N-type heavily doped region 5 in the cell may also be entirely included in the P-type heavily doped region 4 .

Further, the metal cathode 7 and the metal anode 8 in the unit cell can extend along the upper surface of the oxide medium layer 6 to form a field plate, and the length of the field plate can be adjusted so that the device can achieve better constant current capability and higher withstand voltage.

Further, the N-type heavily doped region 5 and the P-type doped region 9 have the same junction depth.

Further, the junction depths of the N-type heavily doped region 5 , the P-type doped region 9 and the P-type heavily doped region 4 are all the same.

Further, the SOI-based lateral constant current diode is formed by the interdigital connection of the same cells, wherein the adjacent P-type doped region 9 and the metal anode 8 can be shared, and the adjacent N-type heavily doped region 5 and the metal cathode 7 may or may not be shared.

Further, the semiconductor material used in the SOI-based lateral constant current diode is silicon or silicon carbide.

Further, each doping type in the SOI-based lateral constant current diode can be correspondingly changed to opposite doping, that is, when P-type doping changes to N-type doping, N-type doping changes to P-type doping .

Further, the length of the P-type heavily doped region 4 of the SOI-based lateral constant current diode can be adjusted to optimize the constant current capability and pinch-off voltage of the device; the P-type heavily doped region 4 and the P-type The distance between the doped regions 9 can be adjusted so that the device can obtain different withstand voltage values.

The method for manufacturing the SOI-based lateral constant current diode includes the following steps:

Step 1: Using SOI silicon wafer as the substrate, perform pre-oxidation before implanting the P-type heavily doped region 4, and perform window etching;

Step 2: perform implantation in the P-type heavily doped region 4, and then push junction in the P-type heavily doped region 4, and etch the redundant oxide layer;

Step 3: Pre-oxidize the N-type heavily doped region 5 before implantation, and perform window etching;

Step 4: perform N-type heavily doped region 5 implantation, and etch the redundant oxide layer;

Step 5: perform pre-oxidation before implanting the P-type doped region 9, and perform window etching;

Step 6: Implanting the P-type doped region 9 and etching the excess oxide layer, the P-type heavily doped region 4 is located between the N-type heavily doped region 5 and the P-type doped region 9;

Step 7: Pre-oxidize before deposition, deposit oxide, and compact;

Step 8: Lithographic ohmic holes;

Step 9: Depositing a metal layer and etching to form a metal cathode 8 and a metal anode 9 .

For the shallow junction P-type heavily doped region 4, the method for manufacturing the SOI-based lateral constant current diode includes the following steps:

Step 1: using an SOI silicon wafer as a substrate, performing pre-oxidation before implanting the P-type heavily doped region 4 and the P-type doped region 9, and performing window etching;

Step 2: Implanting the P-type heavily doped region 4 and the P-type doped region 9, and etching the redundant oxide layer;

Step 3: Pre-oxidize the N-type heavily doped region 5 before implantation, and perform window etching;

Step 4: Implanting the N-type heavily doped region 5 and etching the excess oxide layer, the P-type heavily doped region 4 is located between the N-type heavily doped region 5 and the P-type doped region 9;

Step 5: Pre-oxidize before deposition, deposit oxide, make dense, and activate impurity atoms at the same time;

Step 6: Lithographic ohmic holes;

Step 7: Depositing a metal layer and etching to form a metal cathode 8 and a metal anode 9 .

For devices with a shallow junction P-type heavily doped region 4 and a longer distance between the P-type heavily doped region 4 and the P-type doped region 9, the push junction process of the P-type heavily doped region 4 can be omitted, but a larger Implantation energy, even for the same implantation energy, the junction depth of implanted boron is deeper than the junction depth of implanted phosphorus, and the activation of P-type impurity atoms can be combined with the N-type The impurity atoms are activated together, thereby reducing the process and saving chip manufacturing time.

The beneficial effects of the present invention are:

1. In the SOI-based lateral constant current diode of the present invention, the P-type heavily doped region 4 and the N-type heavily doped region 5 are short-circuited to form a PN junction short circuit structure, which greatly reduces the area of the device under the same constant current size and improves The current density of the device is improved, and the constant current capability of the device is improved.

2. The present invention adopts SOI (Silicon-On-Insulator, silicon on insulating substrate) technology, and arranges a buried oxide layer on the substrate, which can effectively prevent the adverse effects caused by the leakage current of the substrate in the integrated system.

3. The SOI-based lateral constant current diode of the present invention adopts two kinds of carriers for conduction, which increases the current density of the device and improves the constant current capability of the device; makes the linear region of the device steeper, and the pinch-off voltage is below 5V.

4. The P-type heavily doped region 4 in the SOI-based lateral constant current diode of the present invention can be formed together with the P-type doped region 9 without pushing the junction, which simplifies the chip manufacturing process; the adopted process is consistent with the BCD process , which is conducive to the integration of devices and can be used in large-scale integrated circuits.

Description of drawings

Fig. 1 is the structural representation of the lateral constant current diode based on SOI that the present invention provides;

Fig. 2 is a schematic diagram of the structure of the SOI-based lateral constant current diode provided by the present invention; (a) is a structure without a metal field plate; (b) is a structure with a metal field plate.

Fig. 3 is the process simulation schematic diagram of the cell of the embodiment of the present invention;

4 is a current-voltage characteristic curve diagram of an SOI-based lateral constant current diode provided by an embodiment of the present invention;

5 is a schematic process flow diagram of a method for manufacturing an SOI-based lateral constant current diode provided by an embodiment of the present invention;

FIG. 6 is a process simulation diagram corresponding to the manufacturing process of the SOI-based lateral constant current diode provided by the embodiment of the present invention.

detailed description

The technical scheme of the present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

An SOI-based lateral constant current diode is formed by interdigitated connection of multiple cells 1(1), 1(2), 1(3)...1(i) with the same structure, and the number i of cells can be determined according to The specific current capability needs to be adjusted, and the cell includes a substrate 2, an N-type lightly doped silicon 3 on an insulating layer, a P-type heavily doped region 4, an N-type heavily doped region 5, an oxide dielectric layer 6, a metal Cathode 7, metal anode 8, P-type doped region 9, buried oxide layer 10; the buried oxide layer 10 is located on the substrate 2, and the N-type lightly doped silicon 3 is located on the buried oxide layer 10, so The P-type heavily doped region 4, the N-type heavily doped region 5 and the P-type doped region 9 are located in the N-type lightly doped silicon 3, and the oxide medium layer 6, the metal cathode 7 and the metal anode 8 cover all Said cell surface, the P-type heavily doped region 4 is located between the N-type heavily doped region 5 and the P-type doped region 9, and the N-type heavily doped region 5 is partly included in the P-type heavily doped region 4, the N-type heavily doped region 5 is short-circuited with the P-type heavily doped region 4, and the N-type heavily doped region 5, the P-type heavily doped region 4 and the metal cathode 7 form an ohmic contact, so The P-type doped region 9 forms an ohmic contact with the metal anode 8 , and there is a distance between the P-type doped region 9 and the P-type heavily doped region 4 .

Further, a conductive channel is formed between the P-type heavily doped region 4 and the buried oxide layer 10 of the SOI-based lateral constant current diode, and the width of the channel can be adjusted by adjusting the junction depth of the P-type heavily doped region 4 , so that the device can obtain different constant current values and different saturation voltage drops; the length of the P-type heavily doped region 4 can be adjusted to optimize the constant current capability and pinch-off voltage of the device; the P-type heavily doped region The distance between 4 and P-type doped region 9 can be adjusted so that the device can obtain different withstand voltage values.

Further, the N-type heavily doped region 5 in the cell may also be entirely included in the P-type heavily doped region 4 .

Further, the junction depth of the N-type heavily doped region 5 and the P-type doped region 9 is the same, and the junction depth of the N-type heavily doped region 5 and the P-type doped region 9 is the same as that of the P-type heavily doped region 4. Knot depths can be the same or different.

Further, adjacent P-type doped regions 9 and metal anodes 8 between interdigitated connected cells may be shared, and adjacent N-type heavily doped regions 5 and metal cathodes 7 may or may not be shared. As shown in Figure 1(a), the N-type heavily doped region 5 is partly contained in the P-type heavily doped region 4, and the adjacent P-type doped regions 9 and metal anodes are connected between the interdigitated cells. 8, the adjacent N-type heavily doped region 5 and the metal cathode 7 do not share.

Further, the substrate 2 is P-type or N-type doped.

Further, the metal cathode 7 and the metal anode 8 in the unit cell can extend along the upper surface of the oxide medium layer 6 to form a field plate, and the length of the field plate can be adjusted so that the device can achieve better constant current capability and higher withstand voltage.

Further, the SOI-based lateral constant current diode adopts a structure in which the P-type heavily doped region 4 and the N-type heavily doped region 5 are short-circuited, which greatly reduces the area of the device under the same constant current and improves the current of the device. density.

Further, the SOI-based lateral constant current diode adopts two types of carriers to conduct electricity, and adopts a structure of short-circuiting PN junctions, which improves the current density and constant current capability of the device.

Further, the P-type heavily doped region 4 of the SOI-based lateral constant current diode is implanted with boron ions, and then thermally diffused to push the junction. The formed P-type heavily doped region can be controlled by adjusting the boron implantation dose, energy and junction push time Junction depth and concentration of doped region 4. Finally, an oxide dielectric layer 6 and metal electrodes 7 and 8 are formed by depositing.

The operating principle of the SOI-based lateral constant current diode of the present invention is:

The SOI-based lateral constant current diode is obtained by interdigital connection of the same cells of 1(1), 1(2), 1(3)...1(i), and the number i of cells can be determined according to the specific current Capability requirements make adjustments to the design. The cell shown in Figure 2 includes a substrate 2, an N-type lightly doped silicon 3 on an insulating layer, a P-type heavily doped region 4, an N-type heavily doped region 5, an oxide dielectric layer 6, a metal cathode 7, and a metal anode 8. P-type doped region 9, buried oxide layer 10. Wherein the P-type heavily doped region 4 is located between the N-type heavily doped region 5 and the P-type doped region 9, and the N-type heavily doped region 5 is partly included in the P-type heavily doped region 4, The N-type heavily doped region 5 is short-circuited with the P-type heavily doped region 4 and forms an ohmic contact with the metal cathode 7 , and the P-type doped region 9 forms an ohmic contact with the metal anode 8 .

The metal anode 8 of the SOI-based lateral constant current diode is connected to a high potential, and the metal cathode 7 is connected to a low potential. At this time, the potential of the N-type lightly doped silicon 3 on the insulating layer near the P-type doped region 9 is relatively high. A depletion region is formed between the P-type heavily doped region 4 and the buried oxide layer 10, thereby forming a current channel between the P-type heavily doped region 4 and the buried oxide layer 10. As the applied voltage increases, the depletion layer The thickness continues to increase, and the expansion of the depletion layer narrows the conductive channel. When the channel has not been pinched off, the channel resistance is a semiconductor resistance, and the current increases with the increase of the voltage. At this time, the diode works in the linear region. When the applied voltage continues to increase until the depletion layers on both sides are in contact, the channel is pinched off, and the anode voltage at this time is called the pinch-off voltage. After the channel is pinched off, continue to increase the anode voltage, and the pinch-off point changes slowly with the increase of the anode voltage, so the device current increases slowly, forming a constant current function. At this time, the device works in the constant current region. The width of the channel can be adjusted by adjusting the junction depth of the P-type heavily doped region 4, so as to obtain devices with different constant current values.

Example

In this embodiment, an SOI-based lateral constant current diode with a withstand voltage of 200V and a current of about 3E-6A/μm is taken as an example to describe the technical solution of the present invention in detail.

With the help of TSUPREM4 and MEDICI simulation software, the process simulation of the cellular structure of the SOI-based lateral constant current diode shown in Figure 2(b) is carried out. The simulation parameters are: the initial silicon wafer thickness is about 250 μm, the N-type lightly The concentration of N-type lightly doped silicon on the heterogeneous substrate and insulating layer is 8E14cm ^-3 ; the implantation dose of P-type heavily doped region is 4E15cm ^-2 , and the implantation energy is 60keV; the implantation dose of N-type heavily doped region is 4E15cm ^-2 , the implantation energy is 60keV; the channel length is about 6μm; the implantation dose of the P-type doped region is 4E11cm ^-2 , and the implantation energy is 60keV; the distance between the P-type heavily doped region and the P-type doped region is about 16μm; the oxide layer The thickness is about 0.4 μm; the metal deposition thickness is about 2 μm.

FIG. 4 is an i-v characteristic curve obtained through simulation of an SOI-based lateral constant current diode provided by an embodiment of the present invention. It can be seen from Figure 4 that the pinch-off voltage of the device is below 5V, and the pinch-off voltage can be adjusted by adjusting the junction depth of the P-type heavily doped region 4; when it reaches the saturation region, the current basically remains constant, and the constant current characteristic is good.

FIG. 5 is a schematic process flow diagram of a method for manufacturing an SOI-based lateral constant current diode provided by an embodiment of the present invention, and FIG. 6 is a corresponding process simulation diagram during the manufacturing process of an SOI-based lateral constant current diode provided by an embodiment of the present invention. Among them, (1) is the initial silicon wafer; (2) is to form a P-type heavily doped region; (3) is to form an N-type heavily doped region; (4) is to form a P-type doped region; (5) is the final obtained device.

Claims (10)

1. A lateral constant current diode based on SOI, which is formed by the interdigitation connection of a plurality of cells with the same structure, and the cells include a substrate (2), N-type lightly doped silicon (3), P-type heavily doped Impurity region (4), N-type heavily doped region (5), oxide medium layer (6), metal cathode (7), metal anode (8), P-type doped region (9), buried oxide layer (10) The buried oxide layer (10) is located on the substrate (2), the N-type lightly doped silicon (3) is located on the buried oxide layer (10), and the P-type heavily doped region (4) , the N-type heavily doped region (5) and the P-type doped region (9) are located in the N-type lightly doped silicon (3), and the P-type heavily doped region (4) is located in the N-type heavily doped region (5) and the P-type doped region (9), the N-type heavily doped region (5) is at least partly included in the P-type heavily doped region (4), and the oxide dielectric layer (6) Located on N-type lightly doped silicon (3), the N-type heavily doped region (5) is short-circuited with the P-type heavily doped region (4) and forms an ohmic contact with the metal cathode (7), and the P The type doping region (9) forms an ohmic contact with the metal anode (8). 2. The SOI-based lateral constant current diode according to claim 1, characterized in that, all of the N-type heavily doped regions (5) are included in the P-type heavily doped regions (4). 3. The SOI-based lateral constant current diode according to claim 1, characterized in that the metal cathode (7) and metal anode (8) extend along the upper surface of the oxide medium layer (6) to form a field plate. 4. The SOI-based lateral constant current diode according to claim 1, characterized in that the N-type heavily doped region (5) and the P-type doped region (9) have the same junction depth. 5. The lateral constant current diode based on SOI according to claim 1, characterized in that, the N-type heavily doped region (5), the P-type doped region (9) and the P-type heavily doped region (4 ) have the same junction depth. 6. The SOI-based lateral constant current diode according to claim 1, characterized in that the P-type doped regions (9) and metal anodes (8) in adjacent cells are shared. 7. The SOI-based lateral constant current diode according to claim 1, wherein the semiconductor material used in the SOI-based lateral constant current diode is silicon or silicon carbide. 8. The SOI-based lateral constant current diode according to claim 1, characterized in that, each doping type in the SOI-based lateral constant current diode correspondingly becomes the opposite doping, that is, the P-type doping becomes At the same time of N-type doping, N-type doping becomes P-type doping. 9. A method for manufacturing a lateral constant current diode based on SOI, comprising the following steps: Step 1: using SOI silicon wafer as the substrate, performing pre-oxidation before implanting the P-type heavily doped region (4), and performing window etching; Step 2: perform implantation of the P-type heavily doped region (4), and then carry out push junction of the P-type heavily doped region (4), and etch the redundant oxide layer; Step 3: Pre-oxidize the N-type heavily doped region (5) before implantation, and perform window etching; Step 4: perform N-type heavily doped region (5) implantation, etch redundant oxide layer; Step 5: perform pre-oxidation before implanting the P-type doped region (9), and perform window etching; Step 6: Implanting the P-type doped region (9) and etching the excess oxide layer, the P-type heavily doped region (4) is located in the N-type heavily doped region (5) and the P-type doped region (9) )between; Step 7: Pre-oxidize before deposition, deposit oxide, and compact; Step 8: Lithographic ohmic holes; Step 9: Depositing a metal layer and etching to form a metal cathode (7) and a metal anode (8). 10. A method for manufacturing a SOI-based lateral constant current diode, comprising the following steps: Step 1: using an SOI silicon wafer as a substrate, performing pre-oxygenation before implanting the P-type heavily doped region (4) and the P-type doped region (9), and performing window etching; Step 2: implanting the P-type heavily doped region (4) and the P-type doped region (9), and etching the redundant oxide layer; Step 3: Pre-oxidize the N-type heavily doped region (5) before implantation, and perform window etching; Step 4: Implanting the N-type heavily doped region (5) and etching the excess oxide layer, the P-type heavily doped region (4) is located between the N-type heavily doped region (5) and the P-type doped region ( 9) Between; Step 5: Pre-oxidize before deposition, deposit oxide, make dense, and activate impurity atoms at the same time; Step 6: Lithographic ohmic holes; Step 7: Depositing a metal layer and etching to form a metal cathode (7) and a metal anode (8).