CN110518064B - A kind of semiconductor device and its manufacturing method - Google Patents

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof, belonging to the technical field of power semiconductors. The semiconductor device is formed by connecting a plurality of cells with the same structure in an interdigital mode, and the cell structure comprises a second conductive type substrate, a first conductive type lightly doped epitaxial layer, a diffusion second conductive type well region, an insulating medium groove, a first conductive type depletion type channel region, a first heavily doped region and a third heavily doped region with the first conductive type, a second heavily doped region with the second conductive type, an oxidation medium layer, a metal cathode and a metal anode. According to the invention, by introducing the insulating medium groove, the breakdown voltage of the device is improved, a new transverse channel is formed between the bottom of the groove and the substrate, the constant current characteristic is optimized, the dynamic impedance is improved, and the stability of the output current can be greatly enhanced. When the withstand voltage value of the device is 300V through simulation, the pinch-off voltage is below 3.5V, the dynamic impedance can reach 200MΩ, and the device has very good constant current characteristics.

Description

A kind of semiconductor device and its manufacturing method

technical field

The invention belongs to the technical field of power semiconductor devices, and in particular relates to a semiconductor device and a manufacturing method thereof.

Background technique

Constant current source is a commonly used electronic equipment and device, and it is widely used in electronic circuits. The constant current source is usually used to protect the entire circuit, even if the voltage is unstable or the load resistance value changes greatly in the circuit, it can still ensure the stability of the supply current of the entire circuit. Constant Regulating Diode (CRD, Constant Regulating Diode) is a commonly used semiconductor constant current device. The diode is used as a constant current source instead of an ordinary constant current source composed of multiple electronic components such as transistors, Zener tubes and resistors to realize the circuit structure. Simplicity and miniaturization. At present, the output current of common constant current diodes is between several milliamperes and tens of milliamperes, which can be used to directly drive loads. Due to the characteristics of small device size and high device reliability, it has great advantages compared with traditional constant current sources. . In addition, the peripheral circuit of the constant current diode is simple and easy to use, and has been widely used in the fields of automatic control, instrumentation and protection circuits. At present, the forward breakdown voltage of constant-current diodes is generally in the range of 30-100V, and there is a problem of low breakdown voltage. At the same time, the constant current value that can be provided is also low, and it is necessary to ensure a high constant-current value. The chip area, which in turn leads to an increase in cost.

Contents of the invention

The technical problem to be solved by the present invention is to provide a semiconductor device and a manufacturing method thereof for the problems existing in the prior art.

In order to solve the above-mentioned technical problems, an embodiment of the present invention provides a semiconductor device, which is formed by connecting a plurality of cells with the same structure in an interdigitated manner. The cell structure includes a second conductivity type substrate, a first conductivity type lightly doped Heterogeneous epitaxial layer, oxide dielectric layer, metal cathode and metal anode; the lightly doped epitaxial layer of the first conductivity type has diffused second conductivity type well region, first conductivity type depletion channel region, first heavily doped region , the second heavily doped region and the third heavily doped region, the first heavily doped region and the third heavily doped region are of the first conductivity type, and the second heavily doped region is of the second conductivity type;

The lightly doped epitaxial layer of the first conductivity type is located above the substrate of the second conductivity type, the diffused second conductivity type well region is arranged in the lightly doped epitaxial layer of the first conductivity type, the second heavily doped region and the first heavily doped The doped regions are located side by side on the part of the upper layer of the diffused second conductivity type well region, and the first conductive type depletion channel region is located on the upper layer of the diffused second conductive type well region next to the first heavily doped region; the third heavily doped The region is located on the upper layer side of the lightly doped epitaxial layer of the first conductivity type;

The oxide dielectric layer is located on the first part of the first heavily doped region and the depletion channel region of the first conductivity type; the metal cathode is located on the second part of the first heavily doped region, the first part of the second heavily doped region and on the oxide dielectric layer; the metal anode is located on the first part of the third heavily doped region; the first heavily doped region is short-circuited with the second heavily doped region, and forms an ohmic contact with the metal cathode, and the third heavily doped region The doped region forms an ohmic contact with the metal anode;

An insulating dielectric groove is set between the diffused second conductive type well region and the second first conductive type heavily doped region; the oxide dielectric layer is also located in the second part of the second heavily doped region and the second part of the third heavily doped region. Two parts and insulation on the medium tank.

The beneficial effects of the present invention are: the semiconductor device of the present invention injects push junctions into the epitaxial layer to form a well region, forms a channel between the surface of the well region and the middle of the two well regions, and the form of double channels improves the constant current effect and dynamic impedance of the device In addition, if the insulating dielectric groove is used in the lateral direction to withstand the voltage, and the depth of the dielectric groove and the thickness of the epitaxial layer are set reasonably, the lateral channel formed between the bottom of the dielectric groove and the substrate can optimize the constant current characteristics and improve the dynamic impedance. The output current stability of the device is greatly enhanced. In addition, the insulating dielectric groove structure is used to extend the current path inside the device. As the anode voltage increases, the depletion layer continues to expand and compress the current path, which can enhance the output of the device. Current stability; the dielectric groove structure achieves the purpose of obtaining better constant current characteristics and higher withstand voltage on a smaller chip area.

On the basis of the above technical solutions, the present invention can also be improved as follows.

Further, the metal cathode and the metal anode extend along the surface of the oxide medium layer to form a field plate structure.

The beneficial effect of adopting the above further solution is that the device can obtain a higher withstand voltage value.

Further, it also includes a doped region of the second conductivity type on the side wall of the groove, the doped region of the second conductivity type on the side wall of the groove is located between the insulating medium groove and the diffused second conductive type well region, and is connected to the diffused second conductive type well region It is in contact with the lightly doped epitaxial layer of the first conductivity type.

The beneficial effects of adopting the above further scheme are: enhancing the bottom corner of the dielectric groove and the depletion effect of the JFET channel region, not only reducing the peak value of the electric field at the corner of the dielectric groove, improving the withstand voltage value of the device, but also improving the constant current characteristics of the device and increasing the dynamic impedance of the device .

Further, it also includes a buried oxide layer, the buried oxide layer is located between the substrate of the second conductivity type and the lightly doped epitaxial layer of the first conductivity type, and the doping type of the third heavily doped region is replaced by the second conductivity type, forming a fourth heavily doped region.

The beneficial effects of adopting the above further scheme are: the anode of the device is doped with the second conductivity type, and the bipolar conduction mode can increase the constant current value; the buried oxide layer is used to isolate the leakage of the vertical parasitic PNP transistor above the substrate, which can avoid bringing Excessive degradation of device constant current characteristics.

Further, it also includes a buried oxide layer, the buried oxide layer is located between the second conductivity type substrate and the first conductivity type lightly doped epitaxial layer, and the doping of the third heavily doped region is replaced by the second conductivity type Type lightly doped to form a lightly doped region of the second conductivity type.

The beneficial effect of adopting the above-mentioned further solution is: the anode is lightly doped with the second conductivity type in order to prevent the parasitic PNP transistor from passing through the second conductivity type doped region on the side wall of the groove from premature breakdown, and reduce the hole current ratio to ensure the device Constant current characteristics.

Further, the filling material of the insulating dielectric trench is silicon dioxide, silicon nitride or a mixture of silicon dioxide and polysilicon.

Further, the material used in the semiconductor device is silicon or silicon carbide.

Further, the first conductivity type is N type, and the second conductivity type is P type; or the first conductivity type is P type, and the second conductivity type is N type.

In order to solve the above technical problems, an embodiment of the present invention also provides a method for manufacturing a semiconductor device, including the following steps:

Selecting a silicon wafer of the second conductivity type as the substrate of the second conductivity type, and using an epitaxial process to form a lightly doped epitaxial layer of the first conductivity type on the substrate;

forming diffused well regions of the second conductivity type at intervals in the lightly doped epitaxial layer of the first conductivity type;

Forming a dielectric groove on both sides of the diffused second conductivity type well region formed at intervals, filling the dielectric groove with an insulating dielectric layer to form an insulating dielectric groove;

Using an ion implantation process, ion implantation is performed on the entire surface of the lightly doped epitaxial layer of the first conductivity type to form a depletion channel region of the first conductivity type;

forming a first heavily doped region and a third heavily doped region at both ends of the upper layer of the diffused second conductivity type well region and the upper layer of the first conductivity type lightly doped epitaxial layer;

In the upper layer of the diffused well region of the second conductivity type, a second heavily doped region is formed on one side of the first heavily doped region;

Forming an oxide dielectric layer on the lightly doped epitaxial layer of the first conductivity type; photoetching and etching the oxide dielectric layer to form ohmic holes, depositing aluminum metal and reverse etching to form a metal cathode and a metal anode;

Deposit a passivation layer on the oxide dielectric layer, metal cathode and metal anode, and etch the PAD hole;

Metal is back injected under the substrate to form the back metal electrode.

In taking the above steps to realize the manufacturing process of the semiconductor device, it should be ensured that the second heavily doped region (8) and the first heavily doped region (7) are located side by side on the part of the upper layer of the diffused second conductivity type well region (4) , the first conductivity type depletion channel region (6) is located in the upper layer of the diffused second conductivity type well region (4) next to the first heavily doped region (7); the third heavily doped region (9) is located at the The upper layer side of the lightly doped epitaxial layer (3) of the first conductivity type;

The oxide dielectric layer (10) is located on the first part of the first heavily doped region (7) and the first conductivity type depletion channel region (6); the metal cathode (11) is located on the first heavily doped region (7) On the second part, the first part of the second heavily doped region (8) and the oxide medium layer (10); the metal anode (12) is located on the first part of the third heavily doped region (9); the first The heavily doped region (7) is short-circuited with the second heavily doped region (8), and forms an ohmic contact with the metal cathode (11), and the third heavily doped region (9) forms an ohmic contact with the metal anode (12). touch.

The beneficial effects of the present invention are: the semiconductor device manufacturing method of the present invention injects push junctions into the epitaxial layer to form a well region, forms a channel between the surface of the well region and the middle of the two well regions, and the form of the double channel improves the constant current effect of the device and Dynamic impedance value, in addition, in the lateral direction, the insulating dielectric groove is used to withstand the voltage, and the depth of the dielectric groove and the thickness of the epitaxial layer are set reasonably, so that the lateral channel formed between the bottom of the dielectric groove and the substrate can optimize the constant current characteristics and improve the dynamic impedance. function, which greatly enhances the stability of the output current of the device. In addition, the insulating dielectric groove structure is used to extend the current path inside the device. As the anode voltage increases, the depletion layer continues to expand and compress the current path, which can enhance The output current stability of the device; the dielectric groove structure achieves the purpose of obtaining better constant current characteristics and higher withstand voltage on a smaller chip area.

On the basis of the above technical solutions, the present invention can also be improved as follows.

Further, the diffused second conductivity type well region is formed by multiple ion implantations, wherein the energy and dose of the latter ion implantation are lower than the energy and dose of the previous ion implantation.

The beneficial effects of adopting the above further scheme are: weakening the impurity compensation degree of the surface channel and the diffusion well region, reducing the width of the transition region between the surface depletion channel and the JFET conductive channel, making it easy to pinch off the surface channel, reducing the pinch-off voltage, and improving the device Constant current characteristics.

Description of drawings

Fig. 1 (a)-Fig. 1 (d) is the sectional structure schematic diagram of a kind of semiconductor device of the first to the fourth embodiment of the present invention;

Fig. 2 (a)-Fig. 2 (b) is the cell structure diagram of a kind of semiconductor device of the first to the second embodiment of the present invention;

3 is a schematic diagram of a cellular process simulation of a semiconductor device according to a second embodiment of the present invention;

4 is a current-voltage curve diagram of a semiconductor device according to a second embodiment of the present invention;

5 is a dynamic impedance-voltage curve diagram of a semiconductor device according to the second embodiment of the present invention;

6(a)-FIG. 6(h) are schematic process flow diagrams of a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention;

7(a)-7(h) are process simulation diagrams corresponding to the manufacturing process of a semiconductor device according to the fifth embodiment of the present invention.

In the accompanying drawings, the list of parts represented by each label is as follows:

1(1), 1(2)...1(i) is the cell structure, i is a positive integer, indicating the number of cells, 2, the second conductivity type substrate, 3, the first conductivity type lightly doped epitaxial layer , 4, diffusion of the second conductivity type well region, 5, insulating medium groove, 6, the first conductivity type depletion channel region, 7, the first heavily doped region, 8, the second heavily doped region, 9, The third heavily doped region, 10, the oxide medium layer, 11, the metal cathode, 12, the metal anode, 13, the second conductivity type doped region on the groove side wall, 14, the fourth heavily doped region, 15, the buried oxide layer .

Detailed ways

The principles and features of the present invention are described below in conjunction with the accompanying drawings, and the examples given are only used to explain the present invention, and are not intended to limit the scope of the present invention.

As shown in Figures 1(a) and 2(a), a semiconductor device provided by the first embodiment of the present invention is formed by connecting multiple cells with the same structure in an interdigitated manner, and the cell structure includes a second Conduction type substrate 2, first conductivity type lightly doped epitaxial layer 3, oxide medium layer 10, metal cathode 11 and metal anode 12; first conductivity type lightly doped epitaxial layer 3 has diffused second conductivity type well region 4 , the first conductivity type depletion channel region 6, the first heavily doped region 7, the second heavily doped region 8 and the third heavily doped region 9, the first heavily doped region 7 and the third heavily doped region The region 9 is of the first conductivity type, and the second heavily doped region 8 is of the second conductivity type;

The lightly doped epitaxial layer 3 of the first conductivity type is located above the substrate 2 of the second conductivity type, and the well region 4 of the diffused second conductivity type is arranged in the lightly doped epitaxial layer 3 of the first conductivity type, and the first conductivity type is depleted Type channel region 6 is located in the upper layer of the lightly doped epitaxial layer 3 of the first conductivity type, and the first heavily doped region 7 and the second heavily doped region 8 are located side by side in a part of the upper layer of the diffused second conductivity type well region 4; the third The heavily doped region 9 is located on the upper layer side of the lightly doped epitaxial layer 3 of the first conductivity type;

The oxide dielectric layer 10 is located on the first part of the first heavily doped region 7 and the first conductivity type depletion channel region 6; the metal cathode 11 is located on the second part of the first heavily doped region 7, the second heavily doped The first part of the region 8 and the oxide dielectric layer 10; the metal anode 12 is located on the first part of the third heavily doped region 9; the first heavily doped region 7 is short-circuited with the second heavily doped region 8, and is connected with The metal cathode 11 forms an ohmic contact, and the third heavily doped region 9 forms an ohmic contact with the metal anode 12;

It is characterized in that an insulating dielectric groove 5 is set between the diffused second conductive type well region 4 and the second first conductive type heavily doped region 9; the oxide dielectric layer 10 is also located in the second part of the second heavily doped region 8 , the second part of the third heavily doped region 9 and the insulating dielectric trench 5 .

In the above-mentioned embodiments, the semiconductor device of the present invention is implanted into the epitaxial layer to form a well region, and a depletion channel and a JFET channel are respectively formed on the surface of the well region and between the two well regions. The form of the double channel improves the device. Constant current effect and dynamic impedance value. The semiconductor device of the present invention uses an insulating dielectric groove to withstand voltage in the lateral direction, and if the depth of the dielectric groove and the thickness of the epitaxial layer are reasonably set, the lateral channel formed between the bottom of the dielectric groove and the substrate can optimize the constant current characteristics and improve the dynamic impedance. , which greatly enhances the stability of the output current of the device. The simulation shows that when the device works at a voltage of 20V, its dynamic impedance value per micron is as high as 200MΩ, and it has extremely excellent constant current characteristics. The semiconductor device of the present invention adopts an insulating dielectric groove structure, which plays the role of extending the current path inside the device. As the anode voltage rises, the depletion layer continues to expand and then compress the current path, which can enhance the output current stability of the device; the dielectric groove The structure achieves the purpose of obtaining better constant current characteristics and higher withstand voltage on a smaller chip area.

The number i of the cells can be adjusted according to specific current capacity requirements. The spacing of the diffused well regions 4 of the second conductivity type can be properly adjusted to ensure that the depletion channel region 6 of the first conductivity type on the surface is pinched off before the JFET channel region or the two pinch off at the same time to obtain a lower pinch off voltage and better constant current effect.

The working principle of the present invention is introduced below with the first conductivity type being N-type and the second conductivity type being P-type. The channel region 6 is an N-type depletion-type channel region, the first heavily doped region 7 having a first conductivity type is a first N-type heavily doped region, and the second heavily doped region 8 having a second conductivity type It is the second P-type heavily doped region, the third heavily doped region 9 with the first conductivity type is the third N-type heavily doped region, and the first conductivity type lightly doped epitaxial layer 3 is N-type lightly doped epitaxial layer 3. layer. The working principle of the present invention is as follows:

The semiconductor device is obtained by connecting a plurality of cells such as 1(1), 1(2)...1(i) in an interdigitated manner, and the number i of cells can be adjusted according to specific current capacity requirements. In the present invention, phosphorous ions are implanted on the surface of the diffused P-type well region for channel adjustment, so that the surface is compensated to form an N-type depletion-type channel region, and then sequentially implanted to form the first N-type heavily doped region and the second P-type heavily doped region. and a third N-type heavily doped region. An insulating medium groove 5 is provided between the diffused P-type well region and the third N-type heavily doped region, which can not only withstand the lateral withstand voltage, but also play the role of extending the current path. After the surface channel is depleted, the lateral channel structure at the bottom of the dielectric trench will continue to be depleted as the anode voltage increases. Since all the current flows through the bottom lateral channel and is approximately perpendicular to the depletion direction of the channel-substrate junction, the path through which the device current flows continues to narrow, the dynamic resistance increases, and the device has high constant current characteristics .

In actual working conditions, the metal anode 12 of the device is connected to a high potential, and the metal cathode 11 is connected to a low potential. The interspace forms the vertical JFET channel. As the anode voltage increases, the surface depletion channel depletion layer continues to expand upward, and the widening of the depletion layer leads to narrowing of the conductive channel region. Before the channel is pinched off, its characteristics are equivalent to a semiconductor resistor, and the current increases linearly with the increase of the voltage. At this time, the device works in the linear region; when the anode voltage continues to increase to the point that the surface channel is completely consumed When the channel region is pinched off, the anode voltage at this time is called the pinch-off voltage. After the channel is pinched off, the anode voltage continues to increase. The pinch-off point changes slowly with the increase of the anode voltage, and the device current increases slowly. , the device works in the transition region at this time; then increase the anode voltage, the carrier velocity in the channel reaches saturation, and when it reaches the pinch-off point, it is swept into the first N-type heavily doped region by the strong electric field in the depletion region, and the pinch-off point is reached. The breakpoint and the current value basically do not change, and the device works in the constant current region. During this process, there is also a voltage drop at both ends of the vertical JFET channel region between adjacent diffused P-type well regions, so there will also be a similar pinch-off process in which the depletion layer expands to the middle. After the device pinches off and enters the constant current region, the lateral channel region between the bottom of the dielectric trench and the P-type substrate has not been pinched off. After the anode voltage continues to increase, the lateral channel will be continuously depleted, and the current flow path will continue to narrow, so the dynamic resistance of the device can be kept at a high level, and the device has excellent constant current characteristics.

In addition, by adjusting the spacing of the diffused P-type well region, implantation energy and junction push time, the vertical channel and the surface depleted channel region can be pinched off at the same time, which can further improve the constant current characteristics of the device; the current value can be adjusted by adjusting the channel The dosage of implanted phosphorus ions, the length of the N-type depletion channel region and the dosage of the diffused P-type well region are adjusted; the metal cathode 11 and the metal anode 12 can extend to both sides to form a field plate structure, and the length of the metal field plate can be adjusted. The type doped substrate jointly assists in depleting the epitaxial layer to achieve a higher forward breakdown voltage of the device.

As shown in Figure 1(b), 2(b), a semiconductor device provided by the second embodiment of the present invention is based on the first embodiment of the present invention, the metal cathode 11 and the metal anode 12 are oxidized along the The surface of the dielectric layer 10 extends to form a field plate structure. In this structure, the length of the field plate can be adjusted, which can effectively shield the high electric field peak at the bottom corner of the dielectric groove, optimize the electric field distribution in the device body, and enable the device to obtain a higher breakdown voltage.

As shown in Figure 1(c), a semiconductor device provided by the third embodiment of the present invention is based on the first embodiment of the present invention, and a second conductivity type doped region 13 on the side wall of the groove is also provided. The second conductivity type doped region 13 of the wall is located between the insulating medium groove 5 and the diffused second conductivity type well region (4), and is in contact with the diffused second conductivity type well region 4 and the first conductivity type lightly doped epitaxial layer 3 .

The above-mentioned embodiment can enhance the depletion effect of the bottom corner of the dielectric groove and the area under the diffusion second conductivity type well region 4, optimize the electric field at the corner of the dielectric groove, increase the withstand voltage value of the device, improve the constant current characteristic of the device, and increase the dynamic impedance of the device.

As shown in Figure 1(d), a semiconductor device provided by the fourth embodiment of the present invention is based on the first embodiment of the present invention, and further includes a buried oxide layer 15, and the buried oxide layer 15 is located in the second conductivity type Between the substrate 2 and the lightly doped epitaxial layer 3 of the first conductivity type, the doping type of the third heavily doped region 9 is replaced with the second conductivity type to form a fourth heavily doped region 14 .

In the above embodiments, the semiconductor device is a bipolar device, and the current density is higher than that of a unipolar device. Since there are two kinds of carriers involved in conduction, not only the current density is high at the same anode voltage, but also due to the conductance modulation effect in the epitaxial layer, the device will reach saturation more easily and quickly, with a smaller pinch-off voltage. The metal anode and cathode extend to both sides to form a field plate structure, which alleviates the electric field concentration effect at the bottom of the oxidation medium tank, effectively prevents premature breakdown of the device, and improves the withstand voltage value of the device. For bipolar devices, due to the inherent Early effect of the parasitic PNP transistor formed by the anode contact region, the lightly doped epitaxial layer of the first conductivity type and the diffused well region of the second conductivity type, the output curve of the device varies with the anode voltage The increase is obvious, the dynamic impedance value is small, and the constant current characteristics are generally poor. In the embodiment of the present invention, the use of insulating dielectric grooves introduces a lateral channel structure between the bottom of the groove and the substrate. As the anode voltage increases, the effective channel thickness will become narrower, which is equivalent to prolonging the effective time of the parasitic PNP transistor. The width of the base region has a certain inhibitory effect on the Early effect and ensures a high dynamic impedance value of the device. Considering the punch-through problem of the vertical parasitic PNP transistor, the SOI silicon wafer structure is adopted, and a buried oxide layer 15 is arranged between the second conductivity type substrate 2 and the first conductivity type lightly doped epitaxial layer 3, which can avoid the vertical parasitic PNP transistor. The problem of transistor leakage can avoid excessive degradation of the constant current characteristics of the device.

Optionally, a buried oxide layer 15 is also included, the buried oxide layer 15 is located between the substrate 2 of the second conductivity type and the lightly doped epitaxial layer 3 of the first conductivity type, and the doping of the third heavily doped region 9 The dopant is replaced with light doping of the second conductivity type to form a lightly doped region of the second conductivity type. The anode in this structure is lightly doped with the second conductivity type to prevent premature breakdown of the parasitic PNP transistor through the second conductivity type doped region 13 on the side wall of the trench, and to reduce the hole current ratio to ensure constant current characteristics of the device.

Optionally, the filling material of the insulating dielectric trench 5 is silicon dioxide, silicon nitride or a mixture of silicon dioxide and polysilicon. The filling material of the insulating medium groove 5 can also be other insulating materials or a mixture of multiple materials. In addition, the lateral width of the insulating dielectric groove 5 can be adjusted to enable the device to obtain different withstand voltage values; the longitudinal depth of the insulating dielectric groove 5 can be adjusted, thereby changing the current path length and the thickness of the lateral channel at the bottom of the groove to optimize the constant current characteristics of the device. Increase the dynamic impedance value of the device.

Optionally, the material used in the semiconductor device is silicon or silicon carbide.

Optionally, the first conductivity type is N type and the second conductivity type is P type; or the first conductivity type is P type and the second conductivity type is N type. At this time, the second conductivity type substrate 2 can be a P-type material substrate, which can assist in the depletion of the channel, accelerate the depletion of the conductive channel of the JFET, and the pinch-off voltage can reach below 3.5V.

The cell structure of the semiconductor device of the second embodiment of the present invention is simulated by means of MEDICI device structure simulation software. As shown in FIG. 3, the first conductivity type is N type, the second conductivity type is P type, and the forward resistance A semiconductor device with a voltage of 300V and a current of about 1.4E-5A/μm is used as an example to illustrate the simulation parameters: the initial silicon wafer thickness is about 250μm, the concentration of the P-type lightly doped substrate is 3.6E14cm ^-3 , and the N-type lightly doped The concentration of the epitaxial layer is 2.5E15cm ^-3 , the thickness of the epitaxial layer is about 10.5μm, the diffused P-type well region is doped with boron, the surface peak concentration is 4.0E17cm ^-3 , the junction depth of the well region is 4.0μm, and its lateral width is about 9.0 μm, the distance between two adjacent diffused P-type well regions is 3.0 μm; the insulating dielectric groove 5 is made of silicon dioxide material, and its lateral dimension is 10.0 μm, and its vertical dimension is 6.5 μm; the first N for ohmic contact Phosphorus is doped into the N-type heavily doped region and the third N-type heavily doped region, the peak concentration is 8.0E19cm ^-3 , and the junction depth is 0.5μm. The second P-type heavily doped region also used for ohmic contact is doped with boron. The peak concentration is also 8.0E19cm ^-3 , the junction depth is 0.5μm; the length of the depletion channel region is about 3.5μm, the thickness of the channel is about 50nm, and the doping concentration is 7.5E17cm ^-3 ; the metal cathode 11 and the metal The thickness of the anode 12 is 2.5 μm, and both of them span the dielectric groove by about 4.0 μm to form a metal field plate structure; the thickness of the oxide layer above the first N-type heavily doped region, the depletion channel region and the JFET region of the cathode part It is 0.8um. As shown in Figure 4, it can be calculated that the pinch-off voltage of the device is below 3.5V, and the pinch-off voltage and constant current value can be adjusted by adjusting the implant dose of the diffused P-type well region and the implant dose of the depleted channel region. , these two parameters have the most significant impact on the pinch-off voltage. At the same time, the distance between two adjacent diffused P-type wells and the concentration of the N-type lightly doped epitaxial layer will also have a partial impact on the pinch-off characteristics of the device. It can be seen from the figure that after reaching the constant current region, the device current basically maintains a constant value, has a high dynamic impedance value, and the constant current characteristic is very good.

As shown in Figure 5, when the device works at a voltage of 20V, its dynamic impedance value is 204MΩ, which can be increased by more than ten times compared with general constant current devices, and the output has very high stability within the normal working range. Reasonably adjusting the thickness and concentration of the N-type lightly doped epitaxial layer, the depth of the insulating dielectric groove 5 and other parameters can obtain very good constant current characteristics.

As shown in FIG. 6(a)-6(h) and FIG. 7(a)-7(h), a method for manufacturing a semiconductor device provided by the fifth embodiment of the present invention includes the following steps:

Selecting a silicon wafer of the second conductivity type as the substrate 2 of the second conductivity type, and forming a lightly doped epitaxial layer 3 of the first conductivity type on the substrate by using an epitaxial process;

Forming diffused well regions 4 of the second conductivity type at intervals in the lightly doped epitaxial layer 3 of the first conductivity type;

Form dielectric grooves on both sides of the diffused second conductivity type well regions 4 formed at intervals, and fill the dielectric grooves with an insulating dielectric layer to form insulating dielectric grooves 5;

Using an ion implantation process, ion implantation is performed on the entire surface of the lightly doped epitaxial layer 3 of the first conductivity type to form a depletion channel region 6 of the first conductivity type;

A first heavily doped region 7 and a third heavily doped region 9 are formed on part of the upper layer of the diffused second conductivity type well region 4 and at both ends of the upper layer of the first conductivity type lightly doped epitaxial layer 3;

In the upper layer of the diffused second conductivity type well region 4, a second heavily doped region 8 is formed on one side of the first heavily doped region 7;

Form an oxide medium layer 10 on the lightly doped epitaxial layer 3 of the first conductivity type; photolithography and etch the oxide medium layer 10 to form an ohmic hole, deposit aluminum metal and reverse etch to form a metal cathode 11 and a metal anode 12;

Deposit a passivation layer on the oxide medium layer 10, the metal cathode 11 and the metal anode 12, and etch the PAD hole;

Metal is back injected under the substrate to form the back metal electrode.

In the above-mentioned embodiment, the semiconductor device manufacturing method of the present invention injects push junctions into the epitaxial layer to form a well region, and forms a depletion channel and a JFET channel on the surface of the well region and the middle of the two well regions respectively, and the form of the double channel is improved. The constant current effect and dynamic impedance value of the device are improved. In addition, the insulating dielectric groove is used to withstand the voltage in the lateral direction, and the depth of the dielectric groove and the thickness of the epitaxial layer are set reasonably. The lateral channel formed between the bottom of the dielectric groove and the substrate can optimize the constant current. characteristics, the function of improving the dynamic impedance, greatly enhancing the stability of the output current of the device, and adopting the insulating dielectric groove structure, which plays the role of extending the current path inside the device. The channel is compressed to enhance the stability of the output current of the device; the dielectric groove structure achieves the purpose of obtaining better constant current characteristics and higher withstand voltage on a smaller chip area.

Among them, before the implantation of the diffused P-type well region 4, pre-oxidation treatment is performed, and then the photolithography process is used to form the diffused second conductivity type well region 4 through ion implantation and high-temperature push-in treatment, and then the excess oxidation is removed by etching. layer, and the redundant oxide layer is the oxide layer produced by the pre-oxidation treatment and the oxide layer grown on the surface of the device during the high-temperature push junction treatment. At this time, the ion implantation energy is 80keV, and the high temperature junction time is about 500 minutes;

The specific steps of forming the insulating dielectric layer 5 are: sequentially deposit an oxide layer and Si3N4 on the surface of the lightly doped epitaxial layer 3 of the first conductivity type, and use photolithography and etching processes to form a layer on the lightly doped epitaxial layer 3 of the first conductivity type. Form a dielectric groove in the middle, etch away Si3N4, deposit an insulating dielectric layer, etch the insulating dielectric layer and the oxide layer on the surface of the lightly doped epitaxial layer 3 of the first conductivity type, and form an insulating dielectric groove 5;

Before the first heavily doped region 7 and the third heavily doped region 9 are implanted, a pre-oxygen treatment is performed, and then a photolithography process is used, and then impurities of the first conductivity type are implanted through an ion implantation process, thereby forming a first heavily doped region. region 7 and the third heavily doped region 9, using a photolithography process, and then implanting impurities of the second conductivity type through an ion implantation process, thereby forming the second heavily doped region 8, and then etching to remove the redundant oxide layer, and the redundant oxide layer The layer is an oxide layer produced by pre-oxidation treatment;

Before forming the diffused second conductivity type well region 4, the first conductivity type depletion channel region 6, the first heavily doped region 7 and the third heavily doped region 9, pre-oxidize the device to prevent subsequent impurity Injection damage. The oxide medium layer 10 is dense oxide.

In addition, the implantation dose of the diffused second conductivity type well region 4 can be adjusted appropriately to match the implantation dose of the depletion channel region 6 of different first conductivity types. After the two impurities are compensated, the net dopant dose of the surface channel is formed, so that the device can obtain different current level; at the same time, the length of the depletion channel region 6 of the first conductivity type can be adjusted, thereby changing the current value and constant current characteristics of the device.

Optionally, the diffused second conductivity type well region 4 is formed by multiple ion implantations, wherein the energy and dose of the latter ion implantation are lower than the energy and dose of the previous ion implantation.

The above embodiments weaken the degree of impurity compensation between the surface channel and the diffused well region, reduce the width of the transition region between the surface depletion channel and the JFET conductive channel, facilitate the pinch-off of the surface channel, reduce the pinch-off voltage, and improve the constant current characteristics of the device. Wherein, the follow-up can be formed through a short-time push-in process.

The semiconductor device proposed by the present invention adopts the substrate of the second conductivity type, and when the thickness of the lightly doped epitaxial layer of the first conductivity type is appropriate, it can assist the depletion of the JFET between the two cell diffusion well regions of the second conductivity type The role of the region and its lower region accelerates the depletion of the conductive channel of the JFET to achieve a lower pinch-off voltage and a higher dynamic impedance; an insulating layer is provided between the diffused second conductivity type well region and the third heavily doped region The dielectric groove, combined with the upper metal field plate structure, can achieve a higher withstand voltage value on a smaller chip area; at the same time, a lateral conductive channel is formed between the bottom of the dielectric groove and the substrate, and the channel depletion direction is perpendicular to the current direction. The auxiliary depletion effect of the bottom on the lateral channel further enhances the constant current characteristics of the device, and the designed device has a high dynamic impedance value; and the introduction of the insulating medium groove increases the length of the internal current path of the device, and most of the current paths The current flow direction is perpendicular to the depletion direction, which better realizes the pinch-off characteristics of the device, and the device output has high stability; in the manufacturing process, multiple injections can be used to form a diffused second conductivity type well region, and at the same time shorten the high-temperature junction push time , weaken the impurity compensation degree of the surface depletion channel and diffused second conductivity type well region, reduce the width of the transition region between the surface depletion channel and the JFET conductive channel, facilitate the pinch-off of the surface channel, and improve the constant current capability of the device. Parameters such as the length of the metal field plate of the semiconductor device of the present invention, the width of the dielectric groove, the dopant dose of the diffused second conductivity type well region and the first conductivity type depletion channel region can be adjusted to meet different current levels and withstand voltages Value requirements, increasing the flexibility of device design.

In describing the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", " Back", "Left", "Right", "Vertical", "Horizontal", "Top", "Bottom", "Inner", "Outer", "Clockwise", "Counterclockwise", "Axial", The orientation or positional relationship indicated by "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying the referred device or element Must be in a particular orientation, be constructed in a particular orientation, and operate in a particular orientation, and therefore should not be construed as limiting the invention.

In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of these features. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

In the present invention, unless otherwise clearly specified and limited, terms such as "installation", "connection", "connection" and "fixation" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection , or integrated; it may be mechanically connected or electrically connected; it may be directly connected or indirectly connected through an intermediary, and it may be the internal communication of two components or the interaction relationship between two components, unless otherwise specified limit. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention according to specific situations.

In the present invention, unless otherwise clearly specified and limited, the first feature may be in direct contact with the first feature or the first and second feature may be in direct contact with the second feature through an intermediary. touch. Moreover, "above", "above" and "above" the first feature on the second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. "Below", "beneath" and "beneath" the first feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is less horizontally than the second feature.

In the description of this specification, descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific examples", or "some examples" mean that specific features described in connection with the embodiment or example , structure, material or characteristic is included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the described specific features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples and features of different embodiments or examples described in this specification without conflicting with each other.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within range.

Claims (10)

1. A semiconductor device is formed by connecting a plurality of cells with the same structure in an interdigital mode, wherein the cells comprise a second conductive type substrate (2), a first conductive type lightly doped epitaxial layer (3), an oxidation dielectric layer (10), a metal cathode (11) and a metal anode (12); the first conductive type lightly doped epitaxial layer (3) is provided with a diffusion second conductive type well region (4), a first conductive type depletion channel region (6), a first heavily doped region (7), a second heavily doped region (8) and a third heavily doped region (9), wherein the first heavily doped region (7) and the third heavily doped region (9) are of a first conductive type, and the second heavily doped region (8) is of a second conductive type;

the first conductive type lightly doped epitaxial layer (3) is positioned above the second conductive type substrate (2), the diffusion second conductive type well region (4) is arranged in the first conductive type lightly doped epitaxial layer (3), the second heavily doped region (8) and the first heavily doped region (7) are positioned on part of the upper layer of the diffusion second conductive type well region (4) side by side, and the first conductive type depletion channel region (6) is positioned on the upper layer of the diffusion second conductive type well region (4) beside the first heavily doped region (7); the third heavily doped region (9) is positioned on the upper layer side of the first conductive type lightly doped epitaxial layer (3);

an oxidation dielectric layer (10) is positioned on the first part of the first heavily doped region (7) and the first conductive type depletion channel region (6); the metal cathode (11) is positioned on the second part of the first heavily doped region (7), the first part of the second heavily doped region (8) and the oxidation dielectric layer (10); a metal anode (12) is located on a first portion of the third heavily doped region (9); the first heavily doped region (7) is in short circuit with the second heavily doped region (8) and forms ohmic contact with the metal cathode (11), and the third heavily doped region (9) forms ohmic contact with the metal anode (12);

the method is characterized in that an insulating medium groove (5) is arranged between the diffusion second conductive type well region (4) and the third heavily doped region (9); the oxidation dielectric layer (10) is also positioned on the second part of the second heavily doped region (8), the second part of the third heavily doped region (9) and the insulation dielectric groove (5).

2. A semiconductor device according to claim 1, characterized in that the metal cathode (11) and the metal anode (12) extend along the surface of the oxidizing medium layer (10) to form a field plate structure.

3. A semiconductor device according to claim 1, further comprising a trench sidewall second conductivity type doped region (13), the trench sidewall second conductivity type doped region (13) being located between the insulating dielectric trench (5) and the diffused second conductivity type well region (4) and being in contact with the diffused second conductivity type well region (4) and the first conductivity type lightly doped epitaxial layer (3).

4. A semiconductor device according to claim 1, further comprising a buried oxide layer (15), the buried oxide layer (15) being located between the second conductivity type substrate (2) and the first conductivity type lightly doped epitaxial layer (3), and the doping type of the third heavily doped region (9) being replaced by the second conductivity type, forming a fourth heavily doped region (14).

5. A semiconductor device according to claim 3, further comprising a buried oxide layer (15), the buried oxide layer (15) being located between the second conductivity type substrate (2) and the first conductivity type lightly doped epitaxial layer (3), and wherein the doping of the third heavily doped region (9) is replaced by a second conductivity type lightly doping to form a second conductivity type lightly doped region.

6. A semiconductor device according to claim 1, characterized in that the filling material of the insulating medium trench (5) is silicon dioxide, silicon nitride or a mixture of silicon dioxide and polysilicon.

7. A semiconductor device according to claim 1, characterized in that the material used for the semiconductor device is silicon or silicon carbide.

8. The semiconductor device of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type; or the first conductivity type is P type, and the second conductivity type is N type.

9. A method of manufacturing a semiconductor device, comprising the steps of:

selecting a second conductive type silicon wafer as a second conductive type substrate (2), and forming a first conductive type lightly doped epitaxial layer (3) on the substrate by adopting an epitaxial process;

forming diffusion second conductivity type well regions (4) in the first conductivity type lightly doped epitaxial layer (3) at intervals;

forming dielectric grooves on two sides of the diffusion second conductive type well region (4) formed at intervals, and filling the dielectric grooves with an insulating dielectric layer to form insulating dielectric grooves (5);

ion implantation is carried out on the surface of the whole diffusion second conductive type well region (4) by adopting an ion implantation process, so as to form a first conductive type depletion type channel region (6);

forming a first heavily doped region (7) on part of the upper layer of the diffusion second conductivity type well region (4), and forming a third heavily doped region (9) at two ends of the upper layer of the first conductivity type lightly doped epitaxial layer (3); so that the insulating medium groove (5) is positioned between the third heavily doped region (9) and the diffusion second conductive type well region (4);

forming a second heavily doped region (8) on one side of the first heavily doped region (7) in an upper layer of the diffusion second conductivity type well region (4);

forming an oxidation dielectric layer (10) on the lightly doped epitaxial layer (3) of the first conductivity type; photoetching and etching the oxidation dielectric layer (10) to form ohmic holes, depositing aluminum metal and carrying out back etching to form a metal cathode (11) and a metal anode (12); depositing passivation layers on the oxidation dielectric layer (10), the metal cathode (11) and the metal anode (12), and etching PAD holes; back-injecting metal below the substrate to form a back metal electrode;

in the manufacturing process of the semiconductor device by adopting the steps, the second heavily doped region (8) and the first heavily doped region (7) are ensured to be positioned on part of the upper layer of the diffused second conductive type well region (4) side by side, and the first conductive type depletion type channel region (6) is positioned on the upper layer of the diffused second conductive type well region (4) beside the first heavily doped region (7); the third heavily doped region (9) is positioned on the upper layer side of the first conductive type lightly doped epitaxial layer (3);

an oxidation dielectric layer (10) is positioned on the first part of the first heavily doped region (7) and the first conductive type depletion channel region (6); the metal cathode (11) is positioned on the second part of the first heavily doped region (7), the first part of the second heavily doped region (8) and the oxidation dielectric layer (10); a metal anode (12) is located on a first portion of the third heavily doped region (9); the first heavily doped region (7) is in short circuit with the second heavily doped region (8) and forms ohmic contact with the metal cathode (11), and the third heavily doped region (9) forms ohmic contact with the metal anode (12).

10. The method of manufacturing a semiconductor device according to claim 9, wherein the diffused second conductivity type well region (4) is formed by ion implantation a plurality of times, wherein the energy and dose of the latter ion implantation is lower than the energy and dose of the former ion implantation.

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