CN104461921A - Interleaver/de-interleaver device based on hardware system - Google Patents

Abstract

The invention discloses an interleaver/deinterleaver device based on a hardware system. The interleaving depth is L=2 ^N , where N is a positive integer. It includes a counter, a data memory, and an address selection module. The address calculator of the device generates, the address calculator of the device has N input ports and N output ports, and the N input ports and N output ports are only connected by wires or by wires and basic logic gates . The invention solves the problem that the existing interleaving/deinterleaving method is not suitable for realization on a hardware system, and either occupies a large amount of storage space or consumes a large amount of logic resources. The present invention scrambles memory address lines and performs logical operations as the core idea, realizes the function of data interleaving with a relatively small amount of storage space, logical resources and clock cycles, and is suitable for popularization and use.

Description

A kind of interleaver/deinterleaver device based on hardware system

technical field

The invention belongs to the technical field of communication, and in particular relates to an interleaver and deinterleaver device based on a hardware system.

technical background

The interleaver/deinterleaver is widely used in various communication systems today. At the beginning, the interleaver was mainly used between the channel encoder and the channel or between the outer code and the inner code of the concatenated code to scramble the burst error to reduce the length of the burst error; Product codes (so-called Turbo codes), serial concatenated convolutional codes, Turbo TCM, bit-interleaved coded modulation (BICM) systems, and chip-interleaved CDMA systems play a key role.

The most basic function of the interleaver is to make the input data sequence have a different sequence from the original sequence after interleaving, so as to realize the randomization of the input data sequence as much as possible. In different applications, the design requirements of the interleaver are also different. For example, in a Turbo code, the interleaver should be able to improve the Hamming weight distribution of the codeword to improve the error correction performance; reduce the correlation between the outputs of different component encoders, thereby helping to improve the convergence performance of the Turbo iterative decoding algorithm; satisfy No collision restrictions, etc.

At present, there are many types of interleavers, including matrix interleaver, group spiral interleaver, cyclic shift interleaver, uniform distribution interleaver, S random interleaver, row and column S random interleaver, ARP (Almost Regular Permutation) interleaver, two Sub-permutation polynomial (QPP, Quadratic Permutation Polynomial) interleaver, etc.

In a hardware system, the implementation of a serial interleaver usually includes counters, data memory, and address selection blocks. According to the different interleaving address generation methods in the address selection module, the interleaver is usually divided into two types: address storage type and real-time calculation type.

The implementation structure of the address storage interleaver is shown in Figure 1. The interleaving address is generated by the address memory in the address selection module, and the sizes of the counter, data memory and address memory are all interleaving depth L. Generally, at least 2L clock cycles are required to complete the interleaving of one frame of data.

In the first L clock cycles, the address selection module is in the write data mode, and the counter is counted one by one from 0 to L-1, and the output of the counter is used as the address input of the data memory in each clock cycle, so that the data is written in order into the data memory; in the last L clock cycles, the address selection module is in the read data mode, and the counter is accumulated and counted one by one from 0 to L-1 again, and the output of the counter is used as the address input of the address memory in each clock cycle, At the same time, the corresponding data in the interleaved address memory is output as the address input of the data memory, so that the data in the data memory is read out in the order after interleaving.

The advantage of this method is that it does not need to calculate the interleaving address in real time, but the disadvantage is that the interleaving mapping table needs to be stored, and its storage complexity is O(LLog ₂ L) bits.

The implementation structure of the real-time computing interleaver is shown in Figure 2. The interleaving address is generated by the address calculator in the address selection module. The size of the counter and the data memory are the interleaving depth L. The address calculator is composed of a combinational circuit and a sequential circuit. . If the address calculator needs K clocks to complete an address calculation (that is, the address calculation period is K clocks), then at least (K+1)L clocks are required to complete a data frame interleaving. The counter counts up one by one from 0 to (K+1)L-1. In the first L clocks, the address selection module is in the write data mode, and the output of the counter is used as the address input of the data memory in each clock, so that the data is written in the data memory in order; after the KL clocks, the address selection module In the read data mode, the address calculator is in the working state. In each address calculation cycle, the output of the counter is used as the input of the address calculator, and the output of the address calculator is used as the address input of the data memory, so that the data The data in the memory is read out in the order after interleaving.

In the currently used interleaver design methods (such as the quadratic permutation polynomial interleaver), most of the address calculators use a relatively complex interleaving function, which often includes mathematical operations such as addition, subtraction, multiplication, division, and modulus. Operation consumes a lot of logic resources, so it is not very suitable for implementation on hardware systems. If the address calculator completes an address calculation within one clock, a large transmission delay will occur; if the address calculator completes an address calculation within several clocks, the data interleaving time will be extended several times.

The advantage of this method is that it can calculate the interleaved mapping address in real time, only need to store a small number of calculation parameters, and does not need to consume a large amount of memory resources, but the disadvantage is that a large amount of logic resources are required to realize the operation.

Contents of the invention

Most of the existing interleaver/deinterleaver design methods are not designed according to the characteristics of the hardware system, and either occupy a lot of memory resources or consume a lot of logic resources. The present invention aims at the disadvantages of the above-mentioned prior art, and provides a hardware-based interleaver/deinterleaver device capable of real-time calculation in order to save memory resources and logic resources.

A kind of interleaver/deinterleaver device based on hardware system, interleaving depth is L=2 ^N , N is a positive integer, as shown in Figure 2 and Figure 3, comprising:

A counter used to count up one by one from 0 to L-1, with N output ports;

A data memory for implementing interleaved data storage, with N address input ports;

An address selection module for realizing address calculation, the interleaving address is generated by the address calculator in the address selection module, the address selection module has N input ports, which are connected to the N output ports of the counter in order, and have The N output ports are sequentially connected to the N address input ports of the data memory, and a read-write control port, and there are connections between the N input ports of the address selection module and the N output ports of the address selection module. Write data mode and read data mode are two connection modes and are controlled by the read-write control port;

When the address selection module is in the data reading mode as an interleaver or in the data writing mode as a deinterleaver in the device, the address calculator is in a working state;

It is characterized in that: the address calculator of the device has N input ports and N output ports, the N input ports of the address calculator and the N output ports of the address calculator are only connected by wires, or Connected with basic logic gates by wires; when the address calculator was in working condition, the N input ports of the address calculator were directly connected to the N input ports of the address selection module, and the N input ports of the address calculator The output ports are directly connected to the N output ports of the address selection module. The basic logic gate is at least one of a NOT gate, an exclusive OR gate, and an exclusive OR gate.

The N input ports of the address calculator are expressed as I=(i ₀ , i ₁ ,...,i _N-1 ), and the N output ports of the address calculator are expressed as O=(o ₀ , o ₁ ,...,o _N-1 ), then the relationship between the two can be expressed as O=CI, namely:

Among them, C is a coefficient matrix with N rows and N columns of full rank, and the elements c _m,n (0≤m≤N-1,0≤n≤N-1) in C can take values of 1 or 0, representing the output o _m is related or irrelevant to the input _in ; each output is obtained by setting the basic logic gates (not, exclusive or, exclusive or) between the related inputs, then for all possible different inputs, the output value The number of 0 and 1 is equal.

When the coefficient matrix C is a sparse matrix with only one 1 in each row and column, the output port O=(o ₀ ,o ₁ ,...,o _N-1 ) is the input port I=(i ₀ ,i ₁ ,...,i _N-1 ), the address calculator only has wires or only wires and NAND gates at this time, without consuming any logic resources.

In order to achieve the above object, when the device works as an interleaver, when the address selection module is in the read mode, the address calculator works to provide address input for the data memory; 2L clock cycles are required to complete an interleaving, and the implementation steps include:

(1) In the first L clock cycles, the address selection module works in the write data mode, and the counter is counted one by one from 0 to L-1, and the output of the counter is used as the address input of the data memory in each clock, so that the input Data is written into the data memory in sequence; the N input ports of the address selection module are directly connected to the N output ports of the address selection module in sequence.

(2) In the last L clock cycles, the address selection module works in the read data mode, and the counter counts from 0 to L-1 one by one. In each clock, the address calculator takes the output of the counter as input, and outputs the calculation result as The address of the data memory is input, so that the data in the data memory is read out in the order after interleaving.

When the device works as a deinterleaver, when the address selection module is in write mode, the address calculator works to provide address input for the data memory; 2L clock cycles are needed to complete a deinterleave, and the implementation steps include:

(1) In the first L clock cycles, the address selection module works in the write data mode, and the counter counts from 0 to L-1 one by one. In each clock, the address calculator takes the output of the counter as input and outputs the calculation result at the same time As the address input of the data memory, the input data is written into the data memory in an interleaved order;

(2) In the last L clock cycles, the address selection module works in the data-reading mode, and the counters are accumulated and counted one by one from 0 to L-1, and the output of the counter is used as the address input of the data memory in each clock, so that the Data reading in the data memory; the N input ports of the address selection module and the N output ports of the address selection module are directly connected in sequence.

Since the present invention only uses a small amount of logic resources in the address calculator or does not use them at all, the transmission delay of the interleaving/deinterleaving address calculation process is very small, and the calculation can be completed immediately. The storage resource that the present invention mainly consumes is that the RAM used by the data memory and a small amount of registers that the counter uses, and the logical resource that mainly consumes is that the basic logic gate that the address calculator uses (can not use at all), compares other based on mathematics The design method of the interleaver for operation, the invention greatly saves logic resources.

Description of drawings

Figure 1 is a structural diagram of an address storage interleaver

Fig. 2 is a structural diagram of a real-time computing type interleaver, which is also a structural diagram of the present invention as an interleaver device

Fig. 3 is a structural diagram of the present invention as a deinterleaver device

Detailed ways

Example 1:

The interleaver/deinterleaver device based on the hardware system, when working as an interleaver, has an interleaving depth of L=16=2 ⁴ , including:

A counter used to count up one by one from 0 to 15, with 4 output ports;

A data memory for implementing interleaved data storage, with 4 address input ports;

An address selection module for realizing interleaving address calculation, the interleaving address is generated by an address calculator in the address selection module, and the address selection module has 4 input ports connected to the 4 outputs of the counter in sequence There are 4 output ports connected to the 4 address input ports of the data memory in sequence, and a read and write control port, there are write data mode and read data mode between the 4 input ports and the 4 output ports Two connection modes and are controlled by the read-write control port;

When the address selection module is in the data writing mode, the 4 input ports and the 4 output ports are directly connected in sequence;

When the address selection module is in the data reading mode, the address calculator is in the working state.

Let the input port of the address calculator be I=(i ₀ ,i ₁ ,i ₂ ,i ₃ ), and the output port be O=(o ₀ ,o ₁ ,o ₂ ,o ₃ ), the relationship between them can be Expressed as O=CI, let it be:

$\left(\begin{array}{c}{\mathrm{<span\; class="notranslate">\; o</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}\\ {\mathrm{<span\; class="notranslate">\; o</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}\\ {\mathrm{<span\; class="notranslate">\; o</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}\\ {\mathrm{<span\; class="notranslate">\; o</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}\end{array}\right)<span\; class="notranslate">\; =</span>\left(\begin{array}{cccc}\mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}\\ \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}\\ \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}\\ \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}\end{array}\right)\left(\begin{array}{c}{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}\\ {\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}\\ {\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}\\ {\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}\end{array}\right)<span\; class="notranslate">\; .</span>$

Let its further corresponding relationship be:

${\mathrm{<span\; class="notranslate">\; o</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{<span\; class="notranslate">\; \&CirclePlus;</span>}{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}$

o ₁ =i ₂

          .

o ₂ ＝i ₀ ⊕i ₁

${\mathrm{<span\; class="notranslate">\; o</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; =</span>\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}$

where ⊕ represents XOR, means the same or.

For example, when i=5, the binary sequence expressed in reverse order is I=(i ₀ , i ₁ , i ₂ , i ₃ )=(1,0,1,0) (lower bits first, higher bits later), According to the corresponding relationship between output and input, we get:

${\mathrm{<span\; class="notranslate">\; o</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{<span\; class="notranslate">\; \&CirclePlus;</span>}{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{<span\; class="notranslate">\; \&CirclePlus;</span>}\mathrm{<span\; class="notranslate">\; 0</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}$

o ₁ =i ₂ =1

o ₂ ＝i ₀ ⊕i ₁ ＝1 ⊕0＝1

${\mathrm{<span\; class="notranslate">\; o</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; =</span>\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; =</span>\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}$

Thus, O=(o ₀ , o ₁ , o ₂ , o ₃ )=(0,1,1,0), that is, π(i=5)=6.

From the above relationship, the interleaving address mapping list can be obtained as:

i 0 1 2 3 4 5 6 7 π(i) 9 4 13 0 11 6 15 2 i 8 9 10 11 12 13 14 15 π(i) 8 5 12 1 10 7 14 3

A hardware system-based interleaver, when the interleaving depth is L= ²⁴ =16, it takes 32 clock cycles to complete one interleaving, and the implementation steps include:

(1) Write data: In the first 16 clock cycles, the address selection module works in the write data mode, the counter counts from 0 to 15 one by one, and the output of the counter is used as the address input of the data memory in each clock, so that the The input data is sequentially written into the data memory;

(2) Read data: In the last 16 clock cycles, the address selection module works in the read data mode, and the counter counts from 0 to 15 one by one. In each clock, the address calculator takes the output of the counter as input and outputs the calculation result at the same time As the address input of the data memory, the data in the data memory is read out in the order after interleaving.

Thus the input data sequence (A ₀ ,A ₁ ,A 2 ,A ₃ ,A ₄ ,A ₅ ,A ₆ ,A ₇ ,A ₈ ,A ₉ ,A ₁₀ ,A ₁₁ ,A ₁₂ , _{A 13 ,} A ₁₄ ,A ₁₅ ) are interwoven into (A ₉ ,A ₄ ,A ₁₃ ,A ₀ ,A ₁₁ ,A ₆ ,A ₁₅ ,A ₂ ,A 8 ,A ₅ ,A ₁₂ ,A ₁ , _{A 10 ,} A ₇ , A ₁₄ ,A ₃ ).

Example 2:

Compared with when the device described in Embodiment 1 is used as an interleaver, when the device is used as a deinterleaver, the implementation structure is basically the same, the difference is only that: when the interleaver address selection module is in the read mode, the address calculator works to provide data memory address input; and when the deinterleaver address selection module is in write mode, the address calculator works to provide address input for the data memory.

It takes 32 clock cycles for the de-interleaver to complete a de-interleave, and the implementation steps include:

(1) In the first 16 clock cycles, the address selection module works in the write data mode, and the counter counts from 0 to 15 one by one. In each clock, the address calculator takes the output of the counter as input, and outputs the calculation result as data at the same time The address input of the memory, so that the input data is written into the data memory in an interleaved order;

(2) In the last 16 clock cycles, the address selection module works in the data reading mode, and the counters are accumulated and counted one by one from 0 to 15, and the output of the counter is used as the address input of the data memory in each clock, so that the data memory is sequentially The data in is read out.

Thus the input data sequence (A ₉ ,A ₄ ,A ₁₃ ,A ₀ ,A ₁₁ ,A ₆ ,A ₁₅ ,A ₂ ,A 8 ,A ₅ ,A ₁₂ ,A ₁ ,A ₁₀ , _{A 7 ,} A ₁₄ ,A ₃ ) deinterleaved into (A ₀ ,A ₁ ,A ₂ ,A ₃ ,A ₄ ,A ₅ ,A ₆ ,A ₇ ,A ₈ ,A ₉ ,A 10 ,A ₁₁ ,A ₁₂ , _{A 13} ,A ₁₄ ,A ₁₅ ).

Example 3:

The interleaver/deinterleaver device based on the hardware system, when working as an interleaver, has an interleaving depth of L=16=2 ⁴ , including:

A counter used to count up one by one from 0 to 15, with 4 output ports;

A data memory for implementing interleaved data storage, with 4 address input ports;

An address selection module for realizing interleaving address calculation, the interleaving address is generated by an address calculator in the address selection module, and the address selection module has 4 input ports connected to the 4 outputs of the counter in sequence There are 4 output ports connected to the 4 address input ports of the data memory in sequence, and a read and write control port, there are write data mode and read data mode between the 4 input ports and the 4 output ports Two connection modes and are controlled by the read-write control port;

When the address selection module is in the data writing mode, the 4 input ports and the 4 output ports are directly connected in sequence;

When the address selection module is in the data reading mode, the address calculator is in the working state.

Let the input port of the address calculator be I=(i ₀ ,i ₁ ,i ₂ ,i ₃ ), and the output port be O=(o ₀ ,o ₁ ,o ₂ ,o ₃ ), the relationship between them can be Expressed as O=CI, let it be:

$\left(\begin{array}{c}{\mathrm{<span\; class="notranslate">\; o</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}\\ {\mathrm{<span\; class="notranslate">\; o</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}\\ {\mathrm{<span\; class="notranslate">\; o</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}\\ {\mathrm{<span\; class="notranslate">\; o</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}\end{array}\right)<span\; class="notranslate">\; =</span>\left(\begin{array}{cccc}\mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}\\ \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}\\ \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}\\ \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}\end{array}\right)\left(\begin{array}{c}{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}\\ {\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}\\ {\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}\\ {\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}\end{array}\right)<span\; class="notranslate">\; .</span>$

Let its further corresponding relationship be:

o ₀ =i ₃

o ₁ =i ₀

 .

o ₂ =i ₂

o ₃ =i ₁

For example, when i=5, the binary sequence expressed in reverse order is I=(i ₀ , i ₁ , i ₂ , i ₃ )=(1,0,1,0) (lower bits first, higher bits later), According to the corresponding relationship between output and input, we get:

o ₀ =i ₃ =0

o ₁ =i ₀ =1

o ₂ =i ₂ =1

o ₃ =i ₁ =0

Thus, O=(o ₀ , o ₁ , o ₂ , o ₃ )=(0,1,1,0), that is, π(i=5)=6.

From the above relationship, the interleaving address mapping list can be obtained as:

i 0 1 2 3 4 5 6 7 π(i) 0 2 8 10 4 6 12 14 i 8 9 10 11 12 13 14 15 π(i) 1 3 9 11 5 7 13 15

A hardware system-based interleaver, when the interleaving depth is L= ²⁴ =16, it takes 32 clock cycles to complete one interleaving, and the implementation steps include:

(1) Write data: In the first 16 clock cycles, the address selection module works in the write data mode, the counter counts from 0 to 15 one by one, and the output of the counter is used as the address input of the data memory in each clock, so that the The input data is sequentially written into the data memory;

(2) Read data: In the last 16 clock cycles, the address selection module works in the read data mode, and the counter counts from 0 to 15 one by one. In each clock, the address calculator takes the output of the counter as input and outputs the calculation result at the same time As the address input of the data memory, the data in the data memory is read out in the order after interleaving.

Thus the input data sequence (A ₀ ,A ₁ ,A 2 ,A ₃ ,A ₄ ,A ₅ ,A ₆ ,A ₇ ,A ₈ ,A ₉ ,A ₁₀ ,A ₁₁ ,A ₁₂ , _{A 13 ,} A ₁₄ ,A ₁₅ ) into (A ₀ ,A ₂ ,A ₈ ,A ₁₀ ,A ₄ ,A ₆ ,A ₁₂ ,A ₁₄ ,A ₁ ,A 3 ,A ₉ ,A ₁₁ ,A _{5 ,} A ₇ , A ₁₃ ,A ₁₅ ).

Example 4:

Compared with when the device described in Embodiment 3 is used as an interleaver, the implementation structure is basically the same when the device is used as a deinterleaver, the difference is only that: when the interleaver address selection module is in the read mode, the address calculator works to provide data memory address input; and when the deinterleaver address selection module is in write mode, the address calculator works to provide address input for the data memory.

It takes 32 clock cycles for the de-interleaver to complete a de-interleave, and the implementation steps include:

(1) In the first 16 clock cycles, the address selection module works in the write data mode, and the counter counts from 0 to 15 one by one. In each clock, the address calculator takes the output of the counter as input, and outputs the calculation result as data at the same time The address input of the memory, so that the input data is written into the data memory in an interleaved order;

(2) In the last 16 clock cycles, the address selection module works in the data reading mode, and the counters are accumulated and counted one by one from 0 to 15, and the output of the counter is used as the address input of the data memory in each clock, so that the data memory is sequentially The data in is read out.

Thus the input data sequence (A ₀ ,A ₂ ,A ₈ ,A ₁₀ ,A ₄ ,A ₆ ,A ₁₂ ,A ₁₄ ,A 1 ,A ₃ ,A ₉ ,A ₁₁ ,A _{5 ,} A ₇ ,A ₁₃ ,A ₁₅ ) deinterleaved into (A ₀ ,A ₁ ,A ₂ ,A ₃ ,A ₄ ,A ₅ ,A ₆ ,A ₇ ,A ₈ ,A 9 ,A ₁₀ ,A ₁₁ ,A ₁₂ , _{A 13} ,A ₁₄ ,A ₁₅ ).

Claims (5)

1., based on an interlacing device and de-interlacing device device for hardware system, interleave depth is L=2 ⁿ, N is positive integer, comprising:

By the counter of 0 to L-1 incremental count one by one, N number of output port is had for realizing;

For realizing the data-carrier store that interleaving data stores, there is N number of address input end mouth;

For realizing the address selection module of address computation, interleaving address is produced by the address calculator in described address selection module, described address selection module has N number of input port to be in turn connected to N number of output port of described counter, N number of output port is had to be in turn connected to N number of address input end mouth of described data-carrier store, and a Read-write Catrol port, write data mode connected mode and read data pattern connected mode is had also by described Read-write Catrol port controlling between N number of input port of described address selection module and N number of output port of address selection module,

When described address selection module is in read data pattern at described device as interleaver or is in write data mode as deinterleaver, described address calculator is in duty;

It is characterized in that: the address calculator of described device has N number of input port and N number of output port, is connected between N number of input port of described address calculator and N number of output port of described address calculator by means of only wire or by wire with basic logical gate; When address calculator is in running order, N number of input port of described address calculator is directly connected to N number of input port of described address selection module, and N number of output port of described address calculator is directly connected to N number of output port of described address selection module.

2. device according to claim 1, is characterized in that: N number of input port of described address calculator is expressed as I=(i ₀, i ₁..., i _n-1), N number of output port of described address calculator is expressed as O=(o ₀, o ₁..., o _n-1), then relation is therebetween expressed as O=CI, and column is expressed as:

$\left(\begin{array}{c}{o}_0\\ o_1\\ .\\ .\\ .\\ o_{N-1}\end{array}\right)=\left(\begin{array}{cccc}{c}_{\mathrm{0,0}}& ...& ...& c_{0,N-1}\\ .& & & .\\ .& ...& ...& .\\ .& & & .\\ .& & & .\\ .& ...& ...& .\\ .& & & .\\ c_{N-\mathrm{1,0}}& ...& ...& c_{N-1,N-1}\end{array}\right)\left(\begin{array}{c}{i}_0\\ i_1\\ .\\ .\\ .\\ i_{N-1}\end{array}\right)$

Wherein C is the matrix of coefficients of the capable N sequency spectrum of N, the element c in C _m,n(0≤m≤N-1,0≤n≤N-1) value is 1 or 0, and representative exports o respectively _mwith input i _nrelevant or irrelevant.

3. device according to claim 1, is characterized in that: described basic logical gate be not gate, XOR gate, with or door at least one.

4. device according to claim 1 and 2, is characterized in that: described device needs 2L clock period as completing during interleaver once to interweave, and step comprises:

1) in a front L clock period, described address selection module is operated in write data mode, described counter carries out accumulated counts one by one by 0 to L-1, in each clock, the address of the output of described counter as described data-carrier store is inputted, thus input data are write in described data-carrier store in order; Directly be connected in order between N number of input port of described address selection module and N number of output port of described address selection module;

2) in a rear L clock period, described selection module work is in read data pattern, described counter carries out accumulated counts one by one by 0 to L-1, in each clock described address calculator using the output of described counter as input, output result of calculation inputs as the address of described data-carrier store simultaneously, thus by the data in described data-carrier store by sequentially reading after intertexture.

5. device according to claim 1 and 2, is characterized in that: described device needs 2L clock period as completing a deinterleaving during deinterleaver, and step comprises:

1) in a front L clock period, described address selection module is operated in write data mode, and described counter carries out accumulated counts one by one by 0 to L-1; In each clock, described address calculator is using the output of described counter as input, and output result of calculation inputs as the address of described data-carrier store simultaneously, thus writes in described data-carrier store by input data by interleaved order;

2) in a rear L clock period, described address selection module is operated in read data pattern, described counter carries out accumulated counts one by one by 0 to L-1, in each clock, the address of the output of described counter as described data-carrier store is inputted, thus in order by the data reading in data-carrier store; Directly be connected in order between N number of input port of described address selection module and N number of output port of described address selection module.