CN102122964B

CN102122964B - Implementation method of high-speed reed-solomon (RS) codec based on field programmable gate array (FPGA)

Info

Publication number: CN102122964B
Application number: CN201110081379.XA
Authority: CN
Inventors: 宫丰奎; 彭克蓉; 葛建华
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2011-03-31
Filing date: 2011-03-31
Publication date: 2014-07-02
Anticipated expiration: 2031-03-31
Also published as: CN102122964A

Abstract

The invention discloses a method for realizing a high-speed RS codec based on FPGA, including the FPGA implementation of a high-speed RS (244, 212) encoder and the FPGA implementation of a high-speed RS (244, 212) decoder. The high-speed RS encoder is based on The polynomial division circuit, the high-speed RS decoder is based on the three-stage pipeline structure, using dual clock drive, the clock i_clk and the reverse clock i_clk180, at the same time, on the basis of the ordinary GF domain multiplier, three basic operation units are proposed, the constant coefficient The GF domain multiplier, the constant coefficient GF domain multiplier and the GF domain multiplier controlled by two clock cycles not only greatly improve the operation speed, but also reduce the hardware complexity. The invention supports high throughput and strong ability to correct burst errors , can meet various applications.

Description

A Realization Method of High Speed RS Codec Based on FPGA

技术领域 technical field

本发明属于通信中信道编译码装置领域，特别涉及一种可用于卫星高速信号处理的基于FPGA的高速RS(244，212)编译码器实现方法。The invention belongs to the field of channel encoding and decoding devices in communication, and in particular relates to an FPGA-based high-speed RS (244, 212) encoding and decoding implementation method that can be used for satellite high-speed signal processing.

背景技术 Background technique

RS码，由Reed和Solomon应用Mattson-Solomon(MS)多项式于1960年构造出来，是一类有很强纠错能力的多进制BCH码，它既能纠正随机错误又能纠正突发错误，这种良好的特性使它特别适用于信道干扰非常复杂的通信系统中。所谓的复杂信道干扰的情况，就是指信道中出现的错误类型在某一时刻可能是突发错误也可能是随机错误，但是在某一确定时刻只能有一种类型的错误。RS码不仅是一种很好的纠正随机错误的码，又是一种接近最佳的纠正突发错误的码。RS码广泛应用于工程实际之中，在数字传输系统中，如果功率受限且通信质量要求高(如深空通信、潜水通信、移动通信等)，一般都采用以RS码为外码的级联码，在深空探测中，往往需要传输大量珍贵的遥测数据和工程数据，或者需要实时地传送清晰的动态图像数据，使用符合CCSDS标准的RS纠错码技术，可以确保所传送数据的可靠性。RS code, constructed in 1960 by Reed and Solomon using Mattson-Solomon (MS) polynomial, is a kind of multi-ary BCH code with strong error correction ability, which can correct both random errors and burst errors. This good characteristic makes it especially suitable for communication systems with very complex channel interference. The so-called complex channel interference refers to the fact that the error type in the channel may be a burst error or a random error at a certain moment, but there can only be one type of error at a certain moment. The RS code is not only a good code for correcting random errors, but also a code that is close to the best for correcting burst errors. RS codes are widely used in engineering practice. In digital transmission systems, if the power is limited and the communication quality requirements are high (such as deep space communication, diving communication, mobile communication, etc.), the level with RS code as the outer code is generally used. Combined coding, in deep space exploration, it is often necessary to transmit a large amount of precious telemetry data and engineering data, or to transmit clear dynamic image data in real time, using the RS error correction code technology that complies with the CCSDS standard can ensure the reliability of the transmitted data sex.

RS的编码实现较为简单，在RS编码速度上，Zhigang Ren提出一种改进，选择Altera公司的Cyclone III(EP3C25Q240C8)，最大编码时钟频率为262.26MHz。The implementation of RS encoding is relatively simple. In terms of RS encoding speed, Zhigang Ren proposed an improvement, choosing Altera's Cyclone III (EP3C25Q240C8), and the maximum encoding clock frequency is 262.26MHz.

而在RS码的译码过程中，由于译码方法中关键方程的求解，采用了多次迭代的方法，本身实现就比较复杂，又因为译码方法的工程实现也比较困难，从而导致其工程实现成本较高，且难以达到理想的译码速度，所以，一种RS码是否能在实际中得到应用，很大程度上取决于译码算法是否可以简单、快速、经济。此前，Xilinx公司和法国MATRA MARCONI公司生产过满足CCSDS标准的(255，223)RS码的译码芯片，其中，Xilinx公司的译码芯片的两个输入码块之间的时间间隔不小于405个时钟周期，法国MATRA MARCON公司生产的译码芯片的最大数据通过率也不超过100Mbits/s，另外，专利CN100384116C中提出一种符合CCSDS标准的高速RS译码芯片，采用Xilinx公司的xcv600e-6hq240c作为实现芯片，其数据通过率大于400Mbit/s，资源使用小于18万系统门，所以，减少输入码块之间的间隔时钟周期和提高译码器部分的数据通过率是近期工程实现的迫切要求。In the decoding process of RS codes, due to the solution of the key equations in the decoding method, the method of multiple iterations is adopted, the implementation itself is more complicated, and because the engineering realization of the decoding method is also more difficult, resulting in its engineering The implementation cost is high, and it is difficult to achieve the ideal decoding speed. Therefore, whether a RS code can be applied in practice depends largely on whether the decoding algorithm can be simple, fast and economical. Previously, Xilinx and French MATRA MARCONI had produced (255, 223) RS code decoding chips that met the CCSDS standard. Among them, the time interval between two input code blocks of Xilinx's decoding chip was not less than 405 For the clock cycle, the maximum data throughput rate of the decoding chip produced by MATRA MARCON of France does not exceed 100Mbits/s. In addition, a high-speed RS decoding chip conforming to the CCSDS standard is proposed in the patent CN100384116C, and xcv600e-6hq240c of Xilinx Company is used as the To realize the chip, its data throughput rate is greater than 400Mbit/s, and the resource usage is less than 180,000 system gates. Therefore, reducing the interval clock cycle between input code blocks and improving the data throughput rate of the decoder part are urgent requirements for recent project realization.

发明内容 Contents of the invention

本发明的目的在于克服上述已有技术的不足，提出一种基于FPGA的高速RS编译码器实现方法，以提高其通用性以及其所支持的数据吞吐率，满足不同场景的通信需求。The purpose of the present invention is to overcome the deficiencies of the above-mentioned prior art, and propose a method for realizing a high-speed RS codec based on FPGA, so as to improve its versatility and the data throughput rate supported by it, and meet the communication requirements of different scenarios.

为了实现上述目的，本发明的技术方案如下：In order to achieve the above object, the technical scheme of the present invention is as follows:

本发明方法的技术原理包括RS编码原理与RS译码原理。The technical principles of the method of the present invention include RS encoding principles and RS decoding principles.

1.RS编码原理1. RS coding principle

令α为伽罗华域GF(2^m)中的本原元，可纠t个错误的RS码的生成多项式形式为：Let α be the primitive element in the Galois Field GF(2 ^m ), the generator polynomial form of the RS code that can correct t errors is:

$g g ((x x)) = = {Π Π}_{j j = = b b}^{b b + + 22 t t - - 11} ((x x - - {α α}^{sj sj})) = = {Σ Σ}_{i i = = 00}^{3232} {g g}_{i i} {x x}^{i i} - - - - - - ((11))$

其中b称为偏移量，s称为步进因子。Where b is called the offset and s is called the step factor.

注：由于缩短循环码的生成多项式与原码是相同的，所以这不影响生成多项式的形式。Note: Since the generator polynomial of the shortened cyclic code is the same as the original code, this does not affect the form of the generator polynomial.

以RS系统码(n，k)为例，其中，码字的前k位是信息位，k+1到n位是检验位，且Take the RS system code (n, k) as an example, where the first k bits of the codeword are information bits, k+1 to n bits are check bits, and

C(x)＝m(x)x^n-k+r(x) (2)C(x)＝m(x) ^xnk +r(x) (2)

首先，令需要编码的序列为：First, let the sequence to be encoded be:

m＝(m_k-1，m_k-2，Lm₁，m₀，) (3)m=(m _k-1 , m _k-2 , Lm ₁ , m ₀ ,) (3)

那么，编码多项式为：Then, the encoding polynomial is:

m(x)＝m_k-1x^k-1+m_k-2x^k-2+L+m₁x+m₀ (4)m(x)＝m _k-1 x ^k-1 +m _k-2 x ^k-2 +L+m ₁ x+m ₀ (4)

其中k＝n-2t。where k=n-2t.

在系统码形式下，2t个校验位恰是信息多项式x^2tm(x)除以生成多项式g(x)后得到的余式r(x)＝r_2t-1x^2t-1+r_2t-2x^2t-2+L+r₁x+r₀的系数。即：In the form of systematic code, the 2t check digits are exactly the remainder r(x)=r _2t-1 x ^2t-1 +r _2t obtained after dividing the information polynomial x ^2t m(x) by the generator polynomial g(x) Coefficient of _-2 x ^2t-2 +L+r ₁ x+r ₀ . Right now:

m(x)x^2t＝q(x)g(x)+r(x) (5)m(x)x ^2t ＝q(x)g(x)+r(x) (5)

此时，编码器输出的码字多项式为：At this point, the codeword polynomial output by the encoder is:

C(x)＝m(x)x^2t+r(x)＝q(x)g(x) (6)C(x)=m(x)x ^2t +r(x)=q(x)g(x) (6)

因此，RS码的编码问题就是以g(x)为模的除法问题。Therefore, the coding problem of RS code is the division problem modulo g(x).

另外，本发明实现例所涉及的RS(244，212)码，每组码字包含244个码元，其中前212个为信息码元{m₁，m₂，L，m₂₁₂}，后32个为校验码元{p₁，p₂，L，p₃₂}。In addition, for the RS(244, 212) code involved in the implementation example of the present invention, each group of codewords contains 244 symbols, of which the first 212 are information symbols {m ₁ , m ₂ , L, m ₂₁₂ }, and the last 32 One is the check symbol {p ₁ , p ₂ , L, p ₃₂ }.

其中本原多项式采用：where the primitive polynomial uses:

F(x)＝x⁸+x⁷+x²+x+1 (7)F(x)＝x ⁸ +x ⁷ +x ² +x+1 (7)

生成多项式：Generate polynomials:

$G G ((x x)) = = {Π Π}_{j j = = 112112}^{143143} ((x x - - {α α}^{1111 j j})) = = {Σ Σ}_{i i = = 00}^{3232} {g g}_{i i} {x x}^{i i}$

$= = {x x}^{3232} + + {g g}_{11} {x x}^{3131} + + {g g}_{22} {x x}^{3030} + + {g g}_{33} {x x}^{2929} + + {g g}_{44} {x x}^{2828} + + {g g}_{55} {x x}^{2727} + + {g g}_{66} {x x}^{2626} + + {g g}_{77} {x x}^{2525} + + {g g}_{88} {x x}^{24 twenty four}$

$+ + {g g}_{99} {x x}^{23 twenty three} + + {g g}_{1010} {x x}^{22 twenty two} + + {g g}_{1111} {x x}^{21 twenty one} + + {g g}_{1212} {x x}^{2020} + + {g g}_{1313} {x x}^{1919} + + {g g}_{1414} {x x}^{1818} + + {g g}_{1515} {x x}^{1717} + + {g g}_{1616} {x x}^{1616} + + {g g}_{1515} {x x}^{1515}$

$+ + {g g}_{1414} {x x}^{1414} + + {g g}_{1313} {x x}^{1313} + + {g g}_{1212} {x x}^{1212} + + {g g}_{1111} {x x}^{1111} + + {g g}_{1010} {x x}^{1010} + + {g g}_{99} {x x}^{99} + + {g g}_{88} {x x}^{88} + + {g g}_{77} {x x}^{77} + + {g g}_{66} {x x}^{66} - - - - - - ((88))$

$+ + {g g}_{55} {x x}^{55} + + {g g}_{44} {x x}^{44} + + {g g}_{33} {x x}^{33} + + {g g}_{22} {x x}^{22} + + {g g}_{11} x x + + 11$

$= = {x x}^{3232} + + 9191 {x x}^{3131} + + 127127 {x x}^{3030} + + 8686 {x x}^{2929} + + 1616 {x x}^{2828} + + 3030 {x x}^{2727} + + 1313 {x x}^{2626} + + 235235 {x x}^{2525} + + 9797 {x x}^{24 twenty four}$

$+ + 165165 {x x}^{23 twenty three} + + 88 {x x}^{22 twenty two} + + 4242 {x x}^{21 twenty one} + + 5454 {x x}^{2020} + + 8686 {x x}^{1919} + + 171171 {x x}^{1818} + + 3232 {x x}^{1717} + + 113113 {x x}^{1616} + + 3232 {x x}^{1515}$

$+ + 171171 {x x}^{1414} + + 8686 {x x}^{1313} + + 5454 {x x}^{1212} + + 4242 {x x}^{1111} + + 88 {x x}^{1010} + + 165165 {x x}^{99} + + 9797 {x x}^{88} + + 235235 {x x}^{77} + + 1313 {x x}^{66}$

$+ + {3030 x x}^{55} + + {1616 x x}^{44} + + {8686 x x}^{33} + + {127127 x x}^{22} + + 9191 x x + + 11$

2.RS译码原理2. RS decoding principle

首先，令发送端传输的码字多项式为：First, let the codeword polynomial transmitted by the sender be:

C(x)＝c_n-1x^n-1+c_n-2x^n-2L+c₁x+c₀ (9)C(x)＝c _n-1 x ^n-1 +c _n-2 x ^n-2 L+c ₁ x+c ₀ (9)

令接收端的接收序列多项式为：Let the receiving sequence polynomial at the receiving end be:

R(x)＝r_n-1x^n-1+r_n-2x^n-2L+r₁x+r₀ (10)R(x)＝r _n-1 x ^n-1 +r _n-2 x ^n-2 L+r ₁ x+r ₀ (10)

令差错图样多项式为：Let the error pattern polynomial be:

$E E. ((x x)) = = {e e}_{v v} {x x}^{{l l}_{v v}} + + {e e}_{v v - - 11} {x x}^{{l l}_{v v 11}} L L + + {e e}_{22} {x x}^{{l l}_{22}} + + {e e}_{11} {x x}^{{l l}_{11}} - - - - - - ((1111))$

其中

为错误位置数，该位置的错误值为e_i。in

is the number of error positions, and the error value of this position is e _i .

那么：So:

R(x)＝C(x)+E(x) (12)R(x)＝C(x)+E(x) (12)

RS码的传统译码方法与一般的线性码相同，分为以下三步：The traditional decoding method of RS code is the same as that of general linear code, which is divided into the following three steps:

1)由接收到的码字R(x)计算伴随式S(x)。1) Calculate the syndrome S(x) from the received codeword R(x).

2)由伴随式S(x)确定错误图样E(x)。2) Determine the error pattern E(x) from the accompanying formula S(x).

3)计算R(x)-E(x)＝C(x)，得到译码器输出码字C(x)；若译码器不能得到E(x)，则译码失败，此时译码器指出R(x)中有错误，但不能纠正。3) Calculate R(x)-E(x)=C(x) to obtain the decoder output code word C(x); if the decoder cannot obtain E(x), then the decoding fails, and at this time the decoding The compiler points out that there is an error in R(x), but cannot correct it.

其中第2)步又可以分为求错误位置多项式σ(x)和错误值多项式ω(x)两步。伴随式S(x)和σ(x)以及ω(x)之间应满足关键方程：The second step can be further divided into two steps of calculating the error position polynomial σ(x) and the error value polynomial ω(x). The key equation should be satisfied between the accompanying formula S(x) and σ(x) and ω(x):

S(x)σ(x)＝ω(x)modx^2t (13)S(x)σ(x)=ω(x)modx ^2t (13)

译码器的结构具体包括伴随多项式的计算、错误位置多项式的计算、钱搜索和错误值计算四个模块，伴随多项式计算模块生成多项式S(x)，它可用于关键方程求解模块求解关键多项式S(x)σ(x)＝ω(x)modx^2t，其中，我们可以用ME算法或BM算法来解关键方程，得到错误位置多项式σ(x)和错误值多项式ω(x)。然后，通过钱搜索模块和Forney算法模块，这两个多项式可用来得到错误位置和对应的错误值，在译码器的输出端进行纠错。另外，FIFO存贮器是根据这些模块的时延来缓存接收信号的。其中，决定译码器复杂度的主要因素在于求解关键多项式。The structure of the decoder specifically includes four modules: calculation of adjoint polynomial, calculation of error position polynomial, money search and error value calculation. The adjoint polynomial calculation module generates polynomial S(x), which can be used for key equation solving module to solve key polynomial S (x)σ(x)=ω(x)modx ^2t , where we can use ME algorithm or BM algorithm to solve key equations to obtain error position polynomial σ(x) and error value polynomial ω(x). Then, through the money search module and the Forney algorithm module, these two polynomials can be used to obtain the error position and the corresponding error value, and perform error correction at the output end of the decoder. In addition, the FIFO memory buffers the received signals according to the time delay of these modules. Among them, the main factor that determines the complexity of the decoder is to solve the key polynomial.

3.技术方案3. Technical solution

为实现高速目的，本发明所述的一种基于FPGA的高速RS编译码器实现方法包括高速RS(244，212)编码器的FPGA实现与高速RS(244，212)译码器的FPGA实现，采用双时钟驱动来实现。For realizing high-speed purpose, a kind of FPGA-based high-speed RS codec realization method of the present invention comprises the FPGA realization of high-speed RS (244,212) encoder and the FPGA realization of high-speed RS (244,212) decoder, It is realized by dual clock driving.

实现高速RS(244，212)编码器的FPGA方法如下：The FPGA method to realize the high-speed RS (244, 212) encoder is as follows:

高速RS(244，212)编码器采用双时钟驱动模式工作，提高了时钟利用率，从而提高了编码速度，且资源消耗较低。对每组串行输入的212个信息码元{m₁，m₂，L，m₂₁₂}编码得到32个校验码元{p₁，p₂，L，p₃₂}，具体实现方法包括如下步骤：The high-speed RS (244, 212) encoder works in a dual-clock driving mode, which improves the clock utilization rate, thereby increasing the encoding speed with low resource consumption. Encode the 212 information symbols {m ₁ , m ₂ , L, m ₂₁₂ } serially input for each group to obtain 32 check symbols {p ₁ , p ₂ , L, p ₃₂ }. The specific implementation methods include the following step:

(1)开关K1接a口，闭合开关K2，在时钟i_clk的驱动下，输入的第k个信息码元m_k在使能信号的控制下输入编码器，与寄存器D0进行GF域相加运算得S_md，k表示码元序号，初始为1，同时，编码器将输入信息码元m_k直接输出；(1) The switch K1 is connected to the a port, and the switch K2 is closed. Driven by the clock i_clk, the input kth information symbol m _k is input into the encoder under the control of the enable signal, and the GF domain addition operation is performed with the register D0 Get S _md , k represents the code element sequence number, which is initially 1, and at the same time, the encoder directly outputs the input information code element m _k ;

(2)在时钟i_clk180的驱动下，S_md与寄存器D1进行常系数GF域乘加运算，结果存储至寄存器D0；(2) Under the drive of the clock i_clk180, S _md and the register D1 perform multiplication and addition operations in the GF field with constant coefficients, and the result is stored in the register D0;

(3)在时钟i_clk的驱动下，S_md同时与寄存器D2～D31进行常系数GF域乘加运算，结果分别存储至寄存器D1～D30，并将S_md存储于寄存器D31中；(3) Driven by the clock i_clk, S _md performs constant coefficient GF domain multiplication and addition operations with registers D2-D31 at the same time, and the results are stored in registers D1-D30 respectively, and S _md is stored in register D31;

(4)判断信息码元是否输入完毕，如果是，执行步骤(5)，否则，输入第k+1个信息码元m_k+1到编码器，返回步骤(1)；(4) judge whether the information code element has been input, if yes, execute step (5), otherwise, input the k+1th information code element m _k+1 to encoder, return to step (1);

(5)所有信息码元计算完成后，断开开关K2，K1接b口，在时钟i_clk的驱动下，串行输出寄存器D0～D31的值作为检验码元，则该组信息码元编码完毕；(5) After all the information symbols are calculated, turn off the switch K2, K1 is connected to port b, and under the drive of the clock i_clk, the values of the serial output registers D0-D31 are used as the check symbols, and the encoding of this group of information symbols is completed ;

本发明中，所述的高速RS(244，212)编码器的FPGA方法采用基于多项式除法的电路，调用了32个常系数GF域乘加器，通过反相驱动时钟i_clk180控制其中一个常系数GF域乘加器，使其达到高速编码的效果。In the present invention, the FPGA method of the high-speed RS (244, 212) encoder adopts a circuit based on polynomial division, calls 32 constant coefficient GF domain multipliers, and controls one of the constant coefficient GF by inverting the drive clock i_clk180 Domain multiplier to achieve the effect of high-speed encoding.

实现高速RS(244，212)译码器的FPGA方法如下：The FPGA method for realizing high-speed RS (244, 212) decoder is as follows:

本发明所述高速RS(244，212)译码器的FPGA方法采用双时钟驱动，具有三级流水线结构，包括伴随式计算模块、求解关键方程模块、错误值获取模块(包括钱搜索，错误值计算，能否纠错判断)、信息存储FIFO、错误值存储FIFO以及纠正错误电路，译码后的数据由纠正错误电路输出。The FPGA method of the high-speed RS (244, 212) decoder of the present invention adopts double-clock drive, has three-stage pipeline structure, comprises adjoint calculation module, solves key equation module, error value acquisition module (comprising money search, error value calculation, error correction judgment), information storage FIFO, error value storage FIFO and error correction circuit, and the decoded data is output by the error correction circuit.

所述的双时钟驱动，在普通RS译码的流程上，对硬件实现较复杂的子模块，采用反向时钟驱动，使其达到高速运算的同时，也降低了硬件电路的复杂度。The dual-clock drive described above implements more complex sub-modules in hardware in the process of ordinary RS decoding, and adopts reverse clock drive to achieve high-speed operation while reducing the complexity of hardware circuits.

所述的三级流水线结构，其中第一级为伴随计算模块，第二级为求解关键方程模块，第三级为错误值获取模块以及纠正错误电路等，它在很大程度上提高了译码速度，减少了两输入码块之间的间隔时钟周期。In the three-stage pipeline structure, the first stage is an accompanying calculation module, the second stage is a module for solving key equations, and the third stage is an error value acquisition module and an error correction circuit, etc., which greatly improves the decoding efficiency. speed, reducing the interval clock cycles between two input code blocks.

所述伴随式计算模块，通过每组244个数据码元{c₁，c₂，L，c₂₄₄}的串行输入，计算出伴随多项式的系数{s₁，S₂，L，S₃₂}，总共分为32个子模块，分别对应32个伴随多项式的系数，其结果并行输入求解关键方程模块，用于求解错误位置多项式和错误值多项式的系数。The adjoint calculation module calculates the coefficients {s ₁ , S ₂ , L, S ₃₂ } of the adjoint polynomial through the serial input of each group of 244 data symbols {c ₁ , c ₂ , L, c ₂₄₄ } , is divided into 32 sub-modules in total, corresponding to the coefficients of 32 adjoint polynomials, and the results are input in parallel to the key equation solving module, which is used to solve the coefficients of the error position polynomial and error value polynomial.

所述的求解关键方程模块，根据所输入的伴随多项式系数{S₁，S₂，L，S₃₂}和RiBM算法来进行迭代运算，将得到的错误位置多项式的系数{σ₁，σ₂，L，σ₃₂}和错误值多项式的系数{ω₁，ω₂，L，ω₃₂}，以及错码数目，并行输入错误值获取模块，用于判断是否译码正确和计算错误位置以及错误值，其中两组多项式的系数之间是串行输出的。The module for solving key equations performs iterative operations according to the input adjoint polynomial coefficients {S ₁ , S ₂ , L, S ₃₂ } and the RiBM algorithm, and obtains the coefficients {σ ₁ , σ ₂ , L, σ ₃₂ } and the coefficients {ω ₁ , ω ₂ , L, ω ₃₂ } of the error value polynomial, and the number of error codes are input into the error value acquisition module in parallel to judge whether the decoding is correct and calculate the error position and error value , where the coefficients of the two sets of polynomials are serially output.

所述的错误值获取模块，包括钱搜索模块：将钱搜索法得到错误位置多项式的根x_i，以及错误值计算中该根相对应的错误值多项式的值

的计算，综合于一个模块之中，同时得到错误位置多项式的根x_i、错误值多项式的值以及常数项因子

在不影响速度的前提下，大大降低了错误值计算模块所需要的硬件资源和时钟周期；错误值计算模块：采用钱搜索模块得到的相应值计算出错误值。同时错误值获取模块将计算出的错误值，输出给错误值存储FIFO中存储起来。另外，钱搜索模块还输出判断使能信息，用于控制纠正错误电路。The error value acquisition module includes a money search module: the root x _i of the error position polynomial obtained by the money search method, and the value of the error value polynomial corresponding to the root in the error value calculation

The calculation of is integrated in one module, and at the same time, the root x _i of the error position polynomial and the value of the error value polynomial are obtained and the constant term factor

Under the premise of not affecting the speed, the hardware resources and clock cycles required by the error value calculation module are greatly reduced; the error value calculation module: the corresponding value obtained by the money search module is used to calculate the error value. At the same time, the error value acquisition module outputs the calculated error value to the error value storage FIFO for storage. In addition, the money search module also outputs judgment enabling information, which is used to control the error correction circuit.

所述的信息存储FIFO，用于把输入的数据码元按先后顺序存储到FPGA芯片的FIFO单元，待错误值获取模块计算完成后，根据错误情况将数据依次输出到纠正错误电路中；Described information stores FIFO, is used for storing the FIFO unit of the FPGA chip to the FIFO unit of the data symbol of input sequentially, after the calculation of error value acquisition module is completed, according to the error situation, data is output in the error correction circuit successively;

所述的错误值存储FIFO，用于把错误值获取模块的输出数据，按先后顺序存储到FPGA芯片的FIFO单元中，待获取错误值模块计算完成后，根据错误情况将所计算的错误值依次输出到纠正错误电路中；The error value storage FIFO is used to store the output data of the error value acquisition module in the FIFO unit of the FPGA chip in order, and after the calculation of the error value module is completed, the calculated error value is sequentially calculated according to the error situation output to the error correction circuit;

所述的纠正错误电路，是采用错误值获取模块输出的判断使能信息，控制信息存储FIFO和错误值存储FIFO，当判断译码器已正确译码时，则将两者存储的信息顺序输出，进行GF域相加运算，将结果作为已译码字输出，否则，直接将信息存储FIFO的信息作为输出。The error correction circuit is to use the error value to obtain the judgment enable information output by the module, control the information storage FIFO and the error value storage FIFO, and when it is judged that the decoder has decoded correctly, the information stored in the two is sequentially output , carry out the GF field addition operation, and output the result as a decoded word, otherwise, directly output the information of the information storage FIFO.

本发明中，所述的常系数GF域乘法器在普通GF域乘法器的基础上，确定其中一个变量的值，同时，针对这个确定的变量，对乘法器进行改进，大大降低其基本运算单元的复杂度，从而提高了运算速度。In the present invention, the constant-coefficient GF domain multiplier determines the value of one of the variables on the basis of the common GF domain multiplier. At the same time, for this determined variable, the multiplier is improved, and its basic operation unit is greatly reduced. complexity, thereby improving the operation speed.

本发明中，所述的常系数GF域乘加器使GF域乘法和GF域加法操作同时进行，而仅在常系数GF域乘法器的结构上增加了一个异或运算，非常易于硬件实现，同时也大大提高了运算速度。In the present invention, the constant-coefficient GF-field multiplier-adder enables GF-field multiplication and GF-field addition operations to be performed simultaneously, and only adds an XOR operation to the structure of the constant-coefficient GF-field multiplier, which is very easy to implement in hardware. At the same time, the calculation speed is greatly improved.

本发明中，所述的两时钟周期控制GF域乘法器，将普通GF域乘法器结构分成两个子结构，分段进行运算，以一个时钟的时延得到了速度的提高。In the present invention, the two clock cycles control the GF domain multiplier, the structure of the common GF domain multiplier is divided into two substructures, and operations are performed in sections, and the speed is improved with a time delay of one clock.

与现有技术相比，本发明的有益效果是：Compared with prior art, the beneficial effect of the present invention is:

1、采用双时钟驱动，高速RS编译码器的数据通过率高，如用Xilinx公司的xc4vlx160-12ff1148芯片进行综合仿真以及静态时序分析，其中，编码器最高可工作于560MHz的时钟，其数据吞吐量约为4.48Gbit/s，译码器最高可工作于370MHz的时钟，其数据吞吐量约为2.96Gbit/s。另外，其数据资源使用率也不高，如下表所列。1. Driven by dual clocks, the data throughput rate of the high-speed RS codec is high. For example, the xc4vlx160-12ff1148 chip of Xilinx Company is used for comprehensive simulation and static timing analysis. The data throughput is about 4.48Gbit/s, and the decoder can work at the highest clock speed of 370MHz, and its data throughput is about 2.96Gbit/s. In addition, its data resource usage is not high, as listed in the table below.

2、高速RS译码器采用三级流水线结构，降低了输入码块之间的间隔时钟周期，同时将钱搜索和错误值的部分计算结合于一个模块，提高了流水线结构的效率。2. The high-speed RS decoder adopts a three-stage pipeline structure, which reduces the interval clock cycle between input code blocks. At the same time, it combines money search and error value calculation into one module, which improves the efficiency of the pipeline structure.

3、提出三种基本运算单元，常系数GF域乘加器，常系数GF域乘法器，以及两时钟周期控制的GF域乘法器，几种乘法器结合运用，不仅大大提高了运算速度，还降低了硬件复杂度。3. Propose three basic operation units, constant coefficient GF domain multiplier, constant coefficient GF domain multiplier, and GF domain multiplier controlled by two clock cycles. The combination of several multipliers not only greatly improves the operation speed, but also Reduced hardware complexity.

4、整个编译码过程均在一片FPGA芯片中实现，工作性能稳定可靠，同时能够容易移植。4. The entire encoding and decoding process is implemented in an FPGA chip, the working performance is stable and reliable, and it can be easily transplanted.

5、针对不同的实际应用需求，可以在保持外部接口不变的情况下灵活地修改内部电路设计，以便于和不同的设备进行衔接。5. For different practical application requirements, the internal circuit design can be flexibly modified while keeping the external interface unchanged, so as to facilitate the connection with different devices.

6、不但可以纠正随机错误，而且具有很强的纠正突发错误的功能。6. Not only can correct random errors, but also has a strong function of correcting burst errors.

本发明针对不同环境均可应用，具有很强的选择性，采用正反双时钟驱动，在很大程序上提高了数据吞吐量，且又避免了消耗资源过大的缺点，使硬件实现的复杂度大幅降低。此外由于在硬件实现中，均采用最简单的硬件单元，非常易于硬件实现。The present invention can be applied in different environments, has strong selectivity, adopts positive and negative double clock drive, improves data throughput in a large program, and avoids the disadvantage of excessive resource consumption, which makes hardware implementation complicated significantly reduced. In addition, since the simplest hardware unit is used in hardware implementation, it is very easy to implement in hardware.

附图说明 Description of drawings

图1为本发明的高速RS编码器的实现示意图；Fig. 1 is the realization schematic diagram of the high-speed RS coder of the present invention;

图2为本发明的高速RS译码器的三级流水线结构示意图；Fig. 2 is the three-stage pipeline structure schematic diagram of the high-speed RS decoder of the present invention;

图3为本发明采用的伴随式计算子模块示意图；Fig. 3 is the schematic diagram of the adjoint calculation submodule adopted by the present invention;

图4为本发明采用的RiBM算法的流程示意图；Fig. 4 is the schematic flow chart of the RiBM algorithm that the present invention adopts;

图5为本发明采用的钱搜索计算的结构框图；Fig. 5 is the structural block diagram of the money search calculation that the present invention adopts;

图6为本发明提出的常系数GF域乘加器的电路结构示意；Fig. 6 is the schematic diagram of the circuit structure of the constant coefficient GF domain multiplier-adder proposed by the present invention;

图7为本发明提出的常系数GF域乘法器的电路结构示意；Fig. 7 is the schematic diagram of the circuit structure of the constant coefficient GF domain multiplier proposed by the present invention;

图8为本发明提出的高速RS编码器的仿真时序图；Fig. 8 is the simulation timing diagram of the high-speed RS encoder proposed by the present invention;

图9为本发明提出的高速RS译码器的仿真时序图。FIG. 9 is a simulation timing diagram of the high-speed RS decoder proposed by the present invention.

具体实施方式： Detailed ways:

为了使本发明的技术手段、创作特征与达成目的易于明白理解，以下结合具体实施例进一步阐述本发明。In order to make the technical means, creative features and objectives of the present invention easy to understand, the present invention is further described below in conjunction with specific embodiments.

本发明所述的一种基于FPGA的高速RS编译码器实现方法包括高速RS(244，212)编码器的FPGA实现与高速RS(244，212)译码器的FPGA实现，采用反向时钟来实现。A kind of FPGA-based high-speed RS codec realization method of the present invention comprises the FPGA realization of high-speed RS (244,212) encoder and the FPGA realization of high-speed RS (244,212) decoder, adopts reverse clock to accomplish.

所述高速RS(244，212)编码器采用双时钟驱动模式工作，对每组串行输入的212个信息码元{m₁，m₂，L，m₂₁₂}编码得到32个校验码元{p₁，p₂，L，p₃₂}，在不增加硬件复杂度的情况下，提高了时钟利用率，从而提高了编码速度，且资源消耗较低，如图1，具体实现方法包括如下步骤：The high-speed RS (244, 212) encoder works in a dual-clock driving mode, and encodes 212 information symbols {m ₁ , m ₂ , L, m ₂₁₂ } serially input for each group to obtain 32 check symbols {p ₁ , p ₂ , L, p ₃₂ }, without increasing the complexity of the hardware, the clock utilization rate is improved, thereby improving the encoding speed, and the resource consumption is low, as shown in Figure 1. The specific implementation methods include the following step:

(1)开关K1接a口，闭合开关K2，在时钟i clk的驱动下，输入的第k个信息码元m_k在使能信号的控制下输入编码器，与寄存器D0进行GF域相加运算得S_md，k表示码元序号，初始为1，同时，编码器将输入信息码元m_k直接输出；(1) The switch K1 is connected to the port a, and the switch K2 is closed. Driven by the clock i clk, the input k-th information symbol m _k is input into the encoder under the control of the enable signal, and is added to the register D0 in the GF domain. The calculated S _md , k represents the symbol sequence number, which is initially 1, and at the same time, the encoder directly outputs the input information symbol m _k ;

其中，所述的高速RS(244，212)编码器的FPGA方法采用基于多项式除法的电路，调用了32个常系数GF域乘加器，通过反相驱动时钟i_clk180控制其中一个常系数GF域乘加器使达到高速编码的效果，其具体编码时序仿真图如图7所示。Among them, the FPGA method of the high-speed RS (244, 212) encoder adopts a circuit based on polynomial division, calls 32 constant coefficient GF domain multipliers and adders, and controls one of the constant coefficient GF domain multipliers by inverting the drive clock i_clk180 The adder can achieve the effect of high-speed encoding, and its specific encoding timing simulation diagram is shown in Figure 7.

本发明所述高速RS(244，212)译码器的FPGA方法采用双时钟驱动，具有三级流水线结构框图如图2所示，包括伴随式计算模块、求解关键方程模块、错误值获取模块(包括钱搜索，错误值计算，能否纠错判断)、信息存储FIFO、错误值存储FIFO以及纠正错误电路，译码后的数据由纠正错误电路输出，其具体译码时序仿真图如图9所示。The FPGA method of the high-speed RS (244, 212) decoder of the present invention adopts dual-clock drive, has a three-stage pipeline structure block diagram as shown in Figure 2, comprises adjoint calculation module, solving key equation module, error value acquisition module ( Including money search, error value calculation, error correction judgment), information storage FIFO, error value storage FIFO and error correction circuit. The decoded data is output by the error correction circuit. The specific decoding timing simulation diagram is shown in Figure 9 Show.

所述的求解关键方程模块，根据所输入的伴随多项式系数{S₁，S₂，L，S₃₂}和RiBM算法来进行迭代运算，将得到的错误位置多项式的系数{σ₁，σ₂，L，σ₃₂}和错误值多项式的系数{ω₁，ω₂，L，ω₃₂}，以及错码数目，并行输入错误值获取模块，用于判断是否译码正确和计算错误位置以及错误值，其中两组多项式的系数之间是串行输出的，参看图4。The module for solving key equations performs iterative operations according to the input adjoint polynomial coefficients {S ₁ , S ₂ , L, S ₃₂ } and the RiBM algorithm, and obtains the coefficients {σ ₁ , σ ₂ , L, σ ₃₂ } and the coefficients {ω ₁ , ω ₂ , L, ω ₃₂ } of the error value polynomial, and the number of error codes are input into the error value acquisition module in parallel to judge whether the decoding is correct and calculate the error position and error value , where the coefficients of the two sets of polynomials are serially output, see Figure 4.

的计算，综合于一个模块之中，同时得到错误位置多项式的根x_i、错误值多项式的值

以及常数项因子

The calculation of is integrated in one module, and at the same time, the root x _i of the error position polynomial and the value of the error value polynomial are obtained

and the constant term factor

其中，所述的常系数GF域乘法器在普通GF域乘法器的基础上，确定其中一个变量的值，同时，针对这个确定的变量，对乘法器进行改进，如图7所示。Wherein, the constant coefficient GF domain multiplier determines the value of one of the variables on the basis of the common GF domain multiplier, and at the same time, improves the multiplier for the determined variable, as shown in FIG. 7 .

其中，所述的常系数GF域乘加器使GF域乘法和GF域加法同时进行，仅在常系数GF域乘法器结构的基础上增加了一个异或运算，如图6所示。Wherein, the constant-coefficient GF-field multiplier-adder enables GF-field multiplication and GF-field addition to be performed simultaneously, and only an exclusive-or operation is added on the basis of the structure of the constant-coefficient GF-field multiplier, as shown in FIG. 6 .

其中，所述的两时钟周期控制的GF域乘法器，将普通GF域乘法器结构分成两个子结构，分段进行运算。Wherein, the GF domain multiplier controlled by two clock cycles divides the common GF domain multiplier structure into two substructures, and performs operations in sections.

在上述的技术方案中，各部分运算电路均有限域中进行，RS编译码的复杂度很大程度上取决于基本运算单元，传统的RS码编码器中乘法器非常复杂，需要两个多项式相乘，再除以本原多项式取模，其乘法运算不是速度慢就是太复杂，本发明中大部分模块均采用常系数来设计乘法器，或改进而成的常系数GF域乘加器，将GF域乘法和加法同时进行，均只需要进行少量的异或运算即可，大大降低了乘法器实现的复杂度。对于无法采用常系数GF域乘法器的模块，为了提高速度，可采用多个时钟将普通的GF域乘法器分块处理，此处采用两个时钟，将GF域乘法器分为两块进行处理，仅增加上了一个时钟的时延，就达到了很好的效果。In the above-mentioned technical solution, each part of the operation circuit is carried out in the finite field, and the complexity of RS encoding and decoding largely depends on the basic operation unit. The multiplier in the traditional RS code encoder is very complicated, requiring two polynomial phases Multiply, then divide by the original polynomial to take the modulus, its multiplication is either slow or too complicated, most of the modules in the present invention use constant coefficients to design the multiplier, or the improved constant coefficient GF domain multiplier adder, will GF field multiplication and addition are performed simultaneously, and only a small amount of XOR operation is required, which greatly reduces the complexity of multiplier implementation. For modules that cannot use constant coefficient GF domain multipliers, in order to increase the speed, multiple clocks can be used to divide the ordinary GF domain multiplier into blocks. Here, two clocks are used to divide the GF domain multiplier into two blocks for processing. , only increasing the delay of one clock can achieve a very good effect.

本发明采用双时钟驱动，高速RS编译码器的数据通过率高，如用Xilinx公司的xc4vlx160-12ff1148芯片进行综合仿真以及静态时序分析，其中，编码器最高可工作于560MHz的时钟，其数据吞吐量约为4.48Gbit/s，译码器最高可工作于370MHz的时钟，其数据吞吐量约为2.96Gbit/s；高速RS译码器采用三级流水线结构，降低了输入码块之间的间隔时钟周期，同时将钱搜索和错误值的部分计算结合于一个模块，提高了流水线结构的效率；提出三种基本运算单元，常系数GF域乘加器，常系数GF域乘法器，以及两时钟周期控制的GF域乘法器，几种乘法器结合运用，不仅大大提高了运算速度，还降低了硬件复杂度；整个编译码过程均在一片FPGA芯片中实现，工作性能稳定可靠，同时能够容易移植；针对不同的实际应用需求，可以在保持外部接口不变的情况下灵活地修改内部电路设计，以便于和不同的设备进行衔接；不但可以纠正随机错误，而且具有很强的纠正突发错误的功能。The present invention adopts dual-clock drive, and the high-speed RS codec has a high data throughput rate. For example, the xc4vlx160-12ff1148 chip of Xilinx Company is used for comprehensive simulation and static timing analysis. The throughput is about 4.48Gbit/s, the decoder can work at a clock speed of 370MHz, and its data throughput is about 2.96Gbit/s; the high-speed RS decoder adopts a three-stage pipeline structure, which reduces the interval between input code blocks clock cycle, while combining part of the money search and error value calculations in one module, which improves the efficiency of the pipeline structure; proposes three basic arithmetic units, constant coefficient GF domain multiplier, constant coefficient GF domain multiplier, and two clocks The cycle-controlled GF domain multiplier and the combined use of several multipliers not only greatly increase the computing speed, but also reduce the hardware complexity; the entire encoding and decoding process is implemented in an FPGA chip, the working performance is stable and reliable, and it can be easily transplanted ;According to different practical application requirements, the internal circuit design can be flexibly modified while keeping the external interface unchanged, so as to facilitate connection with different devices; not only can correct random errors, but also has a strong ability to correct burst errors Function.

本发明针对不同环境均可应用，具有很强的选择性，其用途非常广泛，采用正反双时钟驱动，在很大程序上提高了数据吞吐量，且又避免了消耗资源过大的缺点，使硬件实现的复杂度大幅降低；此外由于在硬件实现中，均采用最简单的硬件单元，非常易于硬件实现。The present invention can be applied to different environments, has strong selectivity, and has a wide range of uses. It adopts positive and negative dual clock drive, which greatly improves the data throughput and avoids the disadvantage of excessive resource consumption. The complexity of hardware implementation is greatly reduced; in addition, since the simplest hardware unit is used in hardware implementation, it is very easy to implement in hardware.

(1)如图1所示，是本发明提出的高速RS编码器的实现框图，其中，Mg₁～Mg₁₆分别对应为常系数为g1～g16的常系数GF域乘加器CMS(Constant Multiply and Sum)，串行输入的212个信息码元{m₁，m₂，L，m₂₁₂}，开关K1接a口，闭合开关K2，在时钟i_clk的驱动下，输入的第k个信息码元m_k在使能信号的控制下输入编码器，与寄存器D0进行GF域相加运算得S_md，k表示码元序号，初始为1，同时，编码器将输入信息码元m_k直接输出；在时钟i_clk180的驱动下，S_md与寄存器D1进行常系数GF域乘加运算，结果存储至寄存器D0；在时钟i_clk的驱动下，S_md同时与寄存器D2～D31进行常系数GF域乘加运算，结果分别存储至寄存器D1～D30，并将S_md存储于寄存器D31中；判断信息码元是否输入完毕，如果是，断开开关K2，K1接b口，在时钟i_clk的驱动下，串行输出寄存器D0～D31的值作为检验码元，则该组信息码元编码完毕，否则，输入第k+1个信息码元m_k+1到编码器，继续编码操作；(1) As shown in Fig. 1, it is the implementation block diagram of the high-speed RS coder proposed by the present invention, wherein Mg ₁ ~ Mg ₁₆ correspond to the constant coefficient GF domain multiplier-adder CMS (Constant Multiply and Sum), the serially input 212 information symbols {m ₁ , m ₂ , L, m ₂₁₂ }, the switch K1 is connected to port a, the switch K2 is closed, and driven by the clock i_clk, the input kth information code The element m _k is input into the encoder under the control of the enable signal, and the GF domain addition operation is performed with the register D0 to obtain S _md , k represents the symbol number, which is initially 1, and at the same time, the encoder directly outputs the input information symbol m _k ; Driven by the clock i_clk180, S _md performs constant coefficient GF field multiplication and addition with register D1, and the result is stored in register D0; driven by clock i_clk, S _md simultaneously performs constant coefficient GF field multiplication and addition with registers D2~D31 operation, the results are stored in registers D1-D30 respectively, and S _md is stored in register D31; judge whether the input of the information symbol is completed, if so, turn off the switch K2, K1 is connected to port b, and under the drive of the clock i_clk, the serial The values of row output registers D0～D31 are used as check code elements, then this group of information code elements has been encoded, otherwise, input the k+1 information code element m _k+1 to the encoder to continue the encoding operation;

(2)如图2所示，是本发明提出的高速RS译码器的三级流水线结构框图，第一级为伴随式计算模块，由图3所示的伴随式计算子模块组成，第二级为求关键方程模块，其具体流程图如图4所示，第三级为错误值获取模块，其中错误值获取模块分为钱搜索模块，如图5和Forney计算错误值模块，其中，Csi为伴随多项式模块中第i个子模块用到的常系数GF域乘法器CM(Constant Multiplier)的系数，Cc₁～Cc₁₆为钱搜索模块用到的常系数GF域乘法器的系数，此外，图5中的所有加法器都由时钟i_clk驱动，所有CM都由时钟i_clk180驱动，在使能信号为高电平时，信号{σ₁，σ₂，L，σ₃₂}输入，开关同时置于a端，在使能信号为低电平时，开关则同时置于b端。(2) As shown in Figure 2, it is a three-stage pipeline structure block diagram of the high-speed RS decoder proposed by the present invention, the first stage is a concomitant calculation module, which is composed of a concomitant calculation submodule shown in Figure 3, and the second The first level is to ask the key equation module, its specific flow chart is as shown in Figure 4, the third level is the error value acquisition module, wherein the error value acquisition module is divided into money search module, as shown in Figure 5 and Forney calculates the error value module, wherein, Csi is the coefficient of the constant coefficient GF domain multiplier CM (Constant Multiplier) used by the ith sub-module in the adjoint polynomial module, and Cc ₁ ~ Cc ₁₆ are the coefficients of the constant coefficient GF domain multiplier used by the money search module. In addition, Fig. All the adders in 5 are driven by the clock i_clk, and all the CMs are driven by the clock i_clk180. When the enable signal is high, the signal {σ ₁ , σ ₂ , L, σ ₃₂ } is input, and the switch is placed at the a terminal at the same time , when the enable signal is at low level, the switch is placed at terminal b at the same time.

(3)如图6所示，为节省资源量和降低复杂度，本发明中所采用的常系数GF域乘加器，图所示为常系数为g1的常系数GF域乘加器，如图7所示为本发明例中所采用常系数为21的常系数GF域乘法器，其中d0～d7对应为所要进行乘法运算的八比特数据，a0～a7对应为所要进行加法运算的八比特数据，n0～n7为所得到的结果的八比特数据。由图可以看出，所采用的均为最简单的异或门，复杂度非常低。(3) As shown in Figure 6, in order to save resources and reduce complexity, the constant coefficient GF domain multiplier and adder adopted in the present invention, shown in the figure, is the constant coefficient GF domain multiplier with constant coefficient g1, as Fig. 7 shows that the constant coefficient adopted in the example of the present invention is the constant coefficient GF domain multiplier of 21, wherein d0～d7 correspond to the eight-bit data to be multiplied, and a0～a7 correspond to the eight-bit data to be added Data, n0~n7 are eight-bit data of the obtained result. It can be seen from the figure that the simplest XOR gate is adopted, and the complexity is very low.

(4)如图8和图9所示，为高速RS编码器和高速RS译码器的典型时序仿真图，可见其流水线的编译码方式，其中i_clk为正向时钟，i_clk180为反向时钟，i_rst为该模块的复位信号，i_data_ena为数据输入的有效使能信号，iv_data为输入的数据码元，ov_data为输出的数据码元，o_data_ena为数据输出的有效使能信号。(4) As shown in Figure 8 and Figure 9, it is a typical timing simulation diagram of a high-speed RS encoder and a high-speed RS decoder. It can be seen that the encoding and decoding methods of the pipeline, wherein i_clk is a forward clock, i_clk180 is a reverse clock, i_rst is the reset signal of the module, i_data_ena is the effective enable signal of data input, iv_data is the input data symbol, ov_data is the output data symbol, and o_data_ena is the effective enable signal of data output.

所述的基本运算单元均在GF域内进行。The basic operation units described above are all performed in the GF domain.

上述步骤描述了本发明的优选实例，显然本领域技术人员通过参考本发明的优选实例和附图可以对本发明做出各种修改和替换，这些修改和替换都应落入本发明的保护范围之内。Above-mentioned steps have described preferred example of the present invention, obviously those skilled in the art can make various modifications and replacements to the present invention by referring to preferred examples of the present invention and accompanying drawing, and these modifications and replacements all should fall within the scope of protection of the present invention Inside.

Claims

1. a high-speed RS codec implementation method based on FPGA, the method comprises the FPGA realization of high-speed RS (244,212) encoder and the FPGA realization of high-speed RS (244,212) decoder, it is characterized in that:

The FPGA implementation _method of _the described high-speed RS ( ₂₄₄ , 212) encoder obtains 32 check symbols { p ₁ , p ₂ ,..., p ₃₂ }, the specific steps are: (1) switch K1 is connected to port a, close switch K2, driven by the clock i_clk, the input kth information symbol m _k is in the enable signal Input the encoder under the control of , and perform GF domain addition operation with register D0 to get S _md , k represents the symbol sequence number, which is initially 1, and at the same time, the encoder directly outputs the input information symbol m _k ; (2) at the clock i_clk180 Driven by the clock i_clk, S _md performs constant coefficient GF field multiplication and addition operations with register D1, and the result is stored in register D0; (3) Driven by the clock i_clk, S _md simultaneously performs constant coefficient GF field multiplication and addition operations with registers D2~D31 , the results are stored in registers D1-D30 respectively, and S _md is stored in register D31; (4) judge whether the input of the information symbol is complete, if yes, perform step (5), otherwise, input the k+1th information code The element m _k+1 is sent to the encoder, and returns to step (1); (5) After the calculation of all information symbols is completed, the switch K2 is disconnected, and K1 is connected to port b. Driven by the clock i_clk, the serial output registers D0-D31 The value of is used as the check code element, then the encoding of this group of information code elements is completed;

The FPGA implementation method of the described high-speed RS (244, 212) decoder adopts a dual-clock drive and a three-stage pipeline structure, including an adjoint calculation module, a key equation module, an error value acquisition module, an information storage FIFO, an error value Storage FIFO and error correction circuit, the decoded data is output by the error correction circuit;

The dual-clock drive mentioned above adopts the reverse clock drive for some modules with complex hardware implementation, so as to achieve the purpose of high-speed implementation;

The three-stage pipeline structure, wherein the first stage is an accompanying calculation module, the second stage is a module for solving key equations, and the third stage is an error value acquisition module and an error correction circuit;

The adjoint calculation module calculates the coefficients {S ₁ , S ₂ , ..., S ₃₂ } of the adjoint polynomial through the serial input of each group of 244 data symbols {c ₁ , c ₂ , ..., c ₂₄₄ } , is divided into 32 sub-modules in total, corresponding to the coefficients of 32 adjoint polynomials, and the results are input in parallel to the key equation solving module, which is used to solve the coefficients of the error position polynomial and error value polynomial;

The module for solving key equations performs iterative operations according to the input adjoint polynomial coefficients {S ₁ , S ₂ ,..., S ₃₂ } and the RiBM algorithm, and obtains the coefficients {σ ₁ , σ ₂ , ..., σ ₃₂ } and the coefficients {ω ₁ , ω ₂ , ..., ω ₃₂ } of the error value polynomial, and the number of error codes are input in parallel to the error value acquisition module, which is used to judge whether the decoding is correct and calculate the error position and error value;

The error value acquisition module includes a money search module: the root x _i of the error position polynomial obtained by the money search method, and the value of the error value polynomial corresponding to the root in the error value calculation The calculation of is integrated in one module, and at the same time, the root x _i of the error position polynomial and the value of the error value polynomial are obtained

and the constant term factor

Wherein, i represents the serial number of the root of the error position polynomial, initially 1; the error value calculation module: the error value must be calculated by using the corresponding value obtained by the money search module; at the same time, the error value acquisition module outputs the calculated error value to the error value It is stored in the storage FIFO; in addition, the money search module also outputs judgment enabling information, which is used to control and correct the error circuit;

The information storage FIFO is used to store the input data symbols in the FIFO unit of the FPGA chip in sequence, and after the calculation of the error value acquisition module is completed, the data is sequentially output to the error correction circuit according to the error situation;

The error value storage FIFO is used to store the output data of the error value acquisition module in the FIFO unit of the FPGA chip in order, and after the calculation of the error value module is completed, the calculated error value will be calculated according to the error situation. output to the error correction circuit;

The error correction circuit is to use the error value to obtain the judgment enable information output by the module, control the information storage FIFO and the error value storage FIFO, and when it is judged that the decoder has decoded correctly, the information stored in the two is sequentially output , carry out the GF field addition operation, and output the result as a decoded word, otherwise, directly output the information of the information storage FIFO. the

2. a kind of high-speed RS codec realization method based on FPGA according to claim 1, is characterized in that: described constant coefficient GF domain multiplication and addition operation determines wherein a variable on the basis of common GF domain multiplier The value of , at the same time, for this determined variable, the multiplier is improved. the

3. a kind of high-speed RS codec realization method based on FPGA according to claim 1 is characterized in that: described constant coefficient GF domain multiplication and addition operation makes GF domain multiplication and GF domain addition carry out simultaneously, and only in An exclusive OR operation is added to the structure of the constant coefficient GF domain multiplier. the

4. a kind of high-speed RS codec realization method based on FPGA according to claim 1 is characterized in that: the described constant coefficient GF domain multiplication and addition operation of two clock cycle control, common GF domain multiplier structure is divided into two A substructure, segmented to perform operations. the