CN100508405C - Parallel decoding method and decoding device for improving turbo code decoding speed - Google Patents

Abstract

A parallel decoding method and a decoding device for improving the speed of a Turbo code decoder belong to the technical field of Turbo code decoders, and is characterized in that it is based on the existing iterative decoding and utilizes P individual The small decoder realizes the decoding of P parallelism and thus improves the speed of the decoder. Correspondingly, the design method and device of interleaver, small decoder, external information memory, received signal memory, state controller and other devices suitable for this parallel decoding structure are proposed. Using such a method and device, the decoding speed can be increased by about P times, but the total storage capacity does not increase, and the occupied resources do not increase by P times.

Description

Parallel decoding method and decoding device for improving turbo code decoding speed

technical field

A parallel decoding method and a decoding device for improving the decoding speed of Turbo codes belong to the technical field of Turbo code decoders.

Background technique

Turbo code is a kind of channel coding close to the Shannon limit. Based on the convolutional code, the error correction performance close to the Shannon limit can be obtained when the code length is long, and the decoding complexity is not very high. If The decoder can reach a certain speed to meet the increasingly higher data rate and speed requirements in 3G and future 4G communications, and it will have a wider application prospect.

The Turbo code encoding is essentially a parallel concatenated convolutional code, if its encoding is (n, k), then the encoding efficiency is k/n, and it is an encoder composed of two sub-encoders and an interleaver. The schematic diagram of the encoding structure is shown in Figure 1. Taking the code rate of 1/3 as an example, the input is 1 bit, and the output is 3 bits, including information bit X and parity bits Y, Y', and the two parity bits Y, Y' are respectively without the interleaver and after interleaving output after encoding.

1) An interleaver without read-write conflicts.

For the turbo code parallel decoding scheme, each sub-decoding block is decoded independently and simultaneously. If the random interleaving scheme is adopted, then at the same time, different positions of the same decoding sub-block may be read or read. Write operation, and for a storage structure RAM, only one location can be read or written at the same time, so a read-write conflict occurs. Therefore, to realize parallel decoding, it is necessary to design an interleaver without such read-write conflicts.

According to relevant literature research, the design idea is as follows:

Take the block length as W, and N as the code length, then P=N/W as the degree of parallelism. According to the different situations of P and W, different interleaving schemes are adopted (requiring P<=W), which are described as follows:

i. P is an integer, and P and W are mutually prime numbers, then write N as a matrix of P*W (P rows and W columns), and then read in the order of columns, each row has W elements, or P rows. There is no conflict in such an interleaving table. Elements in the same column perform simultaneous read and write operations, but belong to different RAMs, thus avoiding conflicts. For example, N=28, W=7, P=4, see Table 1 for the interleaving table.

ii. When P is an integer, but P and W are not mutually prime numbers, let K be the greatest common divisor of said P and W, then write N as a matrix of P rows and W columns, and the matrix is in the order of columns Divided into K blocks, when transforming the 0th block, read in the order of the columns, and read the block into a matrix with W elements in each row; when transforming the I-th block, refer the last I elements of this block to The head of the block is then read in the order of the columns, and the block is read into a matrix with W elements in each row, where I=1,...,K-1, thus obtaining an interleaving table; thus obtaining an interleaving table; as N=64, W=8, P=8, see Table 2 for the interleaving table. iii. When P is not an integer, add 0 to the tail of the decoded data, so that the new code length N satisfies P=N/W to become an integer, and then obtain an interleaving table according to the above method when P is an integer. The trailing 0s are discarded after decoding.

Table 1 N=28, W=7 interleaving table

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 twenty one twenty two twenty three twenty four 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

before weaving

0 8 16 twenty four 32 40 48 56 57 1 9 17 25 33 41 49 50 58 2 10 18 26 34 42 43 51 59 3 11 19 27 35 36 44 52 60 4 12 20 28 29 37 45 53 61 5 13 twenty one twenty two 30 38 46 54 62 6 14 15 twenty three 31 39 47 55 63 7

Table 2 N=64, W=8 interleaving table

The above design method can satisfy parallel reading and writing without conflict, but the randomness is obviously not enough. The relative relationship between adjacent codes is relatively fixed, for example, the distance between them is W, and the randomness of adjacent codes and codes separated by a certain relationship is not enough, and the decoding performance is not good. To make it applicable to the Turbo code decoder, it also needs to be randomized. There are many methods of randomization processing, such as intra-row interleaving, inter-row interleaving, or both intra-row and inter-row interleaving can achieve this effect. The determination of the final interleaving scheme must be realized through a large number of simulations. We finally adopt the method of performing intra-row interleaving and then inter-row interleaving, which is also a part of our invention.

2) Iterative decoding method

Turbo decoding is carried out by means of iterative decoding, and the schematic diagram of the iterative principle is shown in Figure 3. Since the principle of the specific method is already a mature technology, it will not be described in detail here.

Contents of the invention

The object of the present invention is to provide a method and a decoding device capable of increasing the speed of a Turbo code decoder.

The feature of the parallel decoding method improving the speed of Turbo code decoder of the present invention is: the method utilizes P independent small decoders based on Turbo code iterative decoding of parallel work and does not read and write when parallel decoding The conflicting interleaver is used to improve the decoding speed, and the described decoding method contains the following steps in turn:

Step 1: Initialize all memories and controllers;

Step 2: P small interleaving tables are stored in a small interleaver formed by P memories, and the P small interleaving tables are obtained according to the following steps:

When P is an integer, and P and W are mutually prime numbers, write N as a matrix of P rows and W columns, and then read and write according to the order of the columns, each row has W elements, a total of P rows, where the block length is W, N is code length, P=N/W, and described P represents degree of parallelism; Thus, obtain an interleaving table;

When P is an integer, but P and W are not mutually prime numbers, let K be the greatest common divisor of P and W, then write N as a matrix of P rows and W columns, and divide the matrix into K in the order of columns When transforming the 0th block, read it in the order of the columns, and read the block as a matrix with W elements in each row; when transforming the Ith block, refer the last I elements of the block to the beginning of the block , then read in the order of the columns, read the block into a matrix with W elements in each row, where I=1,...,K-1, thus obtaining an interleaving table;

When P is not an integer, add 0 to the tail of the decoded data, so that the new code length N satisfies P=N/W to become an integer, and then obtain an interleaving table according to the above method when P is an integer, and then decode Discard the 0 added at the end;

Then carry out intra-row interleaving and inter-row interleaving on the described interleaving table, or perform intra-row interleaving and inter-row interleaving at the same time to obtain a large interleaving table, and each row of the above-mentioned large interleaving table forms a small interleaving table to obtain parallel decoding A large interleaving table with non-conflicting reading and writing;

Step 3: Send a frame of data to be decoded to the RAM read-write controller;

Step 4: The iteration controller sends an iteration signal to the RAM read-write controller, and at the same time, the iteration number counter starts counting;

Step 5: Under the control of the iterative control signal, the RAM read-write controller reads P blocks of data from the received signal memory, and sends them to P sub-decoders in parallel, and at the same time reads out P blocks of data from P interleavers storing interleaving tables Read the interleaving table and perform segmental recursive decoding of Turbo codes;

Step 6: Each of the sub-decoders pre-push each block of input data to obtain the initial value of the forward-recursive state likelihood value, and then perform segmental recursion in each block, at this time , the forward recursion and reverse recursion are performed at the same time, and the likelihood ratio and external information are calculated at the same time as the forward recursion;

Step 7: After the P sub-decoders read the received signal and the corresponding external information after each iteration, the external information is sent to the RAM read-write controller to be written into the external information memory through iterative decoding calculation for the P sub-decoders Decoder readout for next iteration;

Step 8: After the number of iterations of the iteration count counter is full, send an iteration end signal to the iteration controller, and the P sub-decoders send hard decision information.

The feature of the parallel decoding device improving the speed of Turbo code decoder of the present invention is: RAM read-write controller, P sub-decoders, P receiving signal memory, P external information memory, P small interleavers, a An iteration controller and an iteration count counter, wherein, P=N/W, N is the code length of a frame of data to be decoded, W is the block length, and P is the degree of parallelism, wherein:

An iterative controller that outputs an iterative control signal;

The RAM read-write controller is provided with an iteration control signal input terminal, a receiving signal of data to be decoded and an input terminal of external information;

P receiving signal memory, the input terminal of the read-write control signal and write data of the memory is connected with the corresponding signal output end of the RAM read-write controller, and the output end of the memory is connected with the corresponding signal output end of the RAM read-write controller connected to the input;

The number of iterations counter, the count pulse output end of the counter is connected with the corresponding input end of the RAM read-write controller;

P external information storages, the external information data and address signal input terminals of the storage are connected to the corresponding output terminals of the RAM read-write controller;

P sub-decoders adopt programmable logic devices, and the P data and address signal input terminals of the decoding device are output with the P interleaved data to be decoded data output terminals and address signal output of the RAM read-write controller. The hard decision signal output terminals and the external information output terminals of the P sub-decoders are connected to the corresponding input terminals of the RAM read-write controller;

P small interleavers are all made of memory, and the P small interleavers form and store an interleaving table with the following steps:

When P is an integer, and P and W are mutually prime numbers, write N as a matrix of P rows and W columns, and then read and write according to the order of the columns, each row has W elements, a total of P rows, where the block length is W, N is code length, P=N/W, and described P represents degree of parallelism; Thus, obtain an interleaving table;

When P is an integer, but P and W are not mutually prime numbers, let K be the greatest common divisor of P and W, then write N as a matrix of P rows and W columns, and divide the matrix into K in the order of columns When transforming the 0th block, read it in the order of the columns, and read the block as a matrix with W elements in each row; when transforming the Ith block, refer the last I elements of the block to the beginning of the block , then read in the order of the columns, read the block into a matrix with W elements in each row, where I=1,...,K-1, thus obtaining an interleaving table;

When P is not an integer, add 0 to the tail of the decoded data, so that the new code length N satisfies P=N/W to become an integer, and then obtain an interleaving table according to the above method when P is an integer, and then decode Discard the 0 added at the end;

Then the interleaving table is first carried out in-row interleaving, then inter-row interleaving, or simultaneously in-row interleaving and inter-row interleaving, each row of the above-mentioned large interleaving table forms a small interleaving table; the small interleaving table is stored to obtain P Small interleaver.

This method can be implemented in various programmable logic devices, and a specific implementation is to use the Virtex2px2vp70ff1704-5 chip of Xilinx Company as a Turbo code decoder, and can also be realized by an application-specific integrated circuit.

Description of drawings

Figure 1 Turbo code encoding structure diagram.

Figure 2 Schematic diagram of iterative decoding of Turbo codes.

Fig. 3 is a schematic diagram of the principle of iterative decoding.

Curved arrows represent the state likelihood values before and after adjacent positions used when translating the symbol at this position, and straight arrows refer to the corresponding positions (or sequence numbers) before and after interleaving.

Figure 4. Schematic diagram of the recursive process within the block.

The horizontal axis represents code units, which are arranged in order, each grid represents a segment, and the same number represents simultaneous operations.

Figure 5. Schematic diagram of the recursion within the block.

Figure 6 is a flowchart of the decoding process.

Figure 7 is a block diagram of the implementation of the decoding device.

Detailed ways

The existing decoding algorithm is non-parallel, adopts the segmented recursive method, and the decoded data can only be processed serially, and the speed is slow, which cannot meet the increasingly higher requirements for the speed of the decoder. However, this method can greatly increase the decoding speed, and the speed can be increased by about P times by using P parallelism. Of course, the complexity of the decoder has increased, but it has not increased by a factor of P, which is an acceptable price relative to the obtained speed.

1. The method proposed by the present invention is characterized in that: it is a method for utilizing an interleaver and a parallel decoding method suitable for parallel decoding, and P decoding sub-blocks can be independently decoded independently without interfering with each other at the same time. A decoding method that works simultaneously on P decoders without parallelism. Its described decoding method contains following steps successively:

1) The decoding starts, and the corresponding counting controller is initialized.

2) A frame of data to be decoded is divided into P blocks, which are used as P pieces of data to be decoded, and information bit information and parity bit information are stored in P RAMs respectively. In the subsequent decoding process, the external information (including interleaved and non-interleaved) must be stored in the corresponding decoding sub-block RAM.

3) Each sub-block is decoded according to the method of parallel iteration. For each sub-block, the segmented recursive method is used to divide the sub-block into m small segments. When performing forward recursion to calculate the state likelihood value and likelihood ratio for a certain segment, the reverse recursion of the next segment is performed at the same time. Push computes the reverse state likelihood. That is, both reverse and forward recursion are performed within the block to improve throughput. In the process of forward recursion, the likelihood ratio and extrinsic information are calculated and stored in the corresponding RAM. The concrete iterative process is as follows: judge whether the iterative process is over, if it is over, output the decoding result, and turn to 5), otherwise the following iterations are carried out: when deciphering the first code, for storage of external information and check digits and information bit bits, etc., When reading and writing, you can directly use the address signal, and for the second code to be translated, you need to use the interleaver (see 4 for details) to find the corresponding address relationship before and after interleaving to read and write the memory correctly. The recursion process in the block is as follows: For the first section of each sub-block, first perform reverse pre-push to obtain the initial value of the first section of reverse recursion, and then perform reverse recursion on the first section to obtain the reverse recursion state Likelihood value, at the same time carry out the reverse pre-push of the next section; then perform forward recursion on one section to calculate the forward recursion state likelihood value, likelihood ratio and external information, and at the same time, perform reverse recursion on the second section Obtain the state likelihood value of reverse recursion, and recurse accordingly. That is to say, at every moment, except for the beginning of the first paragraph, there will be two reverse recursions (one pre-recursion and one formal recursion) and one forward recursion process. The recursive process of this block is shown in Figure 4. The horizontal axis marks are divided into blocks, and the serial numbers 1, 2, and 3 represent execution steps, and the same marks represent simultaneous operations. For each sub-block, the determination of the initial value of the state likelihood value of the first forward recursion: it is obtained from the record of the likelihood value recorded from the forward recursion of the last segment of the previous block to the last digit, and the last segment is reversed The initial value of the recursive state likelihood value is obtained from the record of the last bit likelihood value of the reverse recursive first segment of the next sub-block, and its schematic diagram and process are shown in Figure 5.

4) Interleaver suitable for parallel decoders. This kind of interleaver must be able to ensure that there is no conflict when reading and writing the parallel P RAMs that perform operations at the same time during the iterative process, that is, it must be able to ensure that there is one data read and write for each of the P RAMs. A random interleaver cannot meet such requirements.

5) After several iterations, it is judged that the iterative decoding process is over, and the parallel decoding results are converted into serial data and output.

The main key technical methods of the decoder are as follows:

Let the data length of a frame be N, and the degree of decoding parallelism be P, that is, the data received in a frame is divided into P sub-blocks, each block is decoded at the same time, and the block size is W=N/P. Let both P and W be integers, if not satisfied, you can add 0 after the decoded data, and do not output it after decoding. Because each block can be independently decoded independently of each other, we can simultaneously complete P decodings in one decoding cycle.

For the decoding of each block of data, the piecewise recursive method of the original scheme is adopted, and the forward recursive calculation of the state likelihood value and the reverse recursive calculation of the state likelihood value are carried out at the same time, and the calculation is performed simultaneously in the forward recursive process Likelihood ratios and extrinsic information.

Note that α is the forward recursive state likelihood value, and β is the reverse recursive state likelihood value. The intra-block decoding process is shown in Figure 4, and the specific description is as follows:

Divide a block into several segments, and use the method of "sliding blocks" between each segment, that is, first do reverse pre-push β from the second segment to obtain a more accurate initial value of β in the first segment, and then do The reverse recursion β of the first segment, and at the same time do the reverse pre-calculation β of the second segment to get the initial value, then do the forward recursion α of the first segment, calculate the likelihood ratio at the same time, and do the second The reverse recursion β of the first segment, the reverse pre-calculation β of the third segment gets the initial value...and so on. Then, in each cycle, two reverse recursions are completed, and one forward recursion is used to calculate the likelihood value at the same time. In this way, the storage capacity can be reduced by segmenting, and the method of parallelizing the two segments and pre-pushing the third segment can increase the throughput.

In Figure 4, the horizontal direction is the code length, which is divided into P blocks. Assume that the length of each segment is the same as the pre-push length, which is 32, while ①, ②, and ③ represent the sequence of time, and the same symbols are operations performed at the same time.

Let's look at the implementation of a specific example. Assuming that the data length of one frame, that is, the code length, is 4096, and the degree of parallelism P is 16, then the length of each sub-block is W=4096/16=256. Each block is required to be decoded simultaneously and independently without affecting each other. A block of data is divided into 8 segments for decoding, and the length of each segment of data in the block is 256/8=32.

When calculating the state likelihood value by forward recursion, the initial value of α in the first segment should come from the last segment of the previous block, and when calculating the state likelihood value by reverse recursion, the initial value of β in the last segment should come from in the first paragraph of the following block. That is to say, the initial value of this block comes from other blocks, so it must be pre-deduced to obtain these initial values as the input of another block. The specific pre-push scheme is as follows: at the beginning of each iteration, α pre-push is first performed on the last segment (length 32), and the α value of the last symbol is obtained as the initial pre-push of the first segment α for the next forward recursion. set value. And when the reverse recursion of the first section of each block is completed, write down the β at the beginning of the block as the initial value of the reverse recursion β of the last section of the previous block. The schematic diagram of the recursive relationship of the initial value is shown in Figure 5.

Another key technology for the realization of parallel decoding is the design and implementation of an interleaver suitable for this decoding structure. According to the basic method of designing a conflict-free interleaver introduced in the background art, the randomization process is performed: intra-row interleaving is performed first, and then inter-row interleaving is performed.

The implementation of the interleaver is described below with the code length being 64 and the unit block length being 8.

N=64, P=8, W=8, the greatest common divisor of W and P is 8, then the interleaving table for row writing and column reading needs to perform 8 cyclic transformations according to the rules introduced in the background technology. The interleaving table obtained on this basis is shown in Table 2. Because the randomness is not enough, it is necessary to perform randomization processing, that is, to interleave within and between rows on this basis. Of course, in order to ensure that there is no conflict between reading and writing, the interleaving must ensure the invariance of elements in the same column belonging to the same column. According to the code length, a method of randomization processing is given below: first perform intra-row interleaving, and the interleaving method used for each row is the same, for example

5 0 6 2 1 7 4 3

Then after in-row interleaving, the interleaving table becomes:

40 0 48 16 8 56 32 twenty four 33 57 41 9 1 49 25 17 26 50 34 2 58 42 18 10 19 43 27 59 51 35 11 3 12 36 20 52 44 28 4 60 5 29 13 45 37 twenty one 61 53

62 twenty two 6 38 30 14 54 46 55 15 63 31 twenty three 7 47 39

Table 3 Interleaving table after intra-row interleaving

Then perform inter-row interleaving on the obtained interleaving table, and adopt the mode of modulo 4, that is, the number of columns divided by 4 congruent is the same interleaving mode.

For example, the following inter-row interleaving scheme can be used:

The remainder is 0: 3 0 5 2 7 1 4 6

The remainder is 1: 5 1 7 3 0 6 4 2

The remainder is 2: 1 4 0 7 5 2 6 3

The remainder is 3: 2 7 4 0 1 5 3 6

Then the interleaving table obtained after interleaving between rows is shown in Table 4

19 29 41 2 51 twenty one 25 10 40 57 20 31 8 49 4 39 5 15 48 52 37 7 32 60 26 43 63 16 58 35 47 twenty four 55 0 13 9 twenty three 56 61 17 33 twenty two 34 45 1 14 18 53 12 36 6 59 44 28 54 3 62 50 27 38 30 42 11 46

Table 4 Interleaving table after row interleaving

Of course, for different code lengths, the mode of interleaving within a row and between rows will be different, which must be determined through a large number of simulations. The code length 64 is used as an example to illustrate the design process of the interleaver.

In summary, the decoding process is as follows:

1) Design an interleaver suitable for parallel decoding.

2) Decoding starts, and all state memories and related controllers are initialized.

3) A frame of data is divided into P sub-blocks, and the received data is processed and stored in blocks.

4) Each block is pre-deduced first to obtain the initial value of the state likelihood value of forward and backward recursion.

5) Segmented recursion is performed in each block, forward recursion and reverse recursion are performed simultaneously, and likelihood ratio and external information are calculated at the same time of forward recursion.

6) Iterative decoding, when the iteration ends, hard decision information is output.

The parallel decoding scheme with a degree of parallelism of 16 increases the throughput by 16 times compared with the original scheme without considering the working clock, and the resources occupied are not unbearably increased. Therefore, such a cost is acceptable.

The decoding device is described as follows:

The decoding device, i.e., the Turbo code decoder, includes P sub-decoders for parallel processing (including internal recursive state likelihood value memory, memory for storing small interleaving tables suitable for parallel decoding, etc.), received signal memory, external information Memory, RAM read and write controller, iterative controller.

The sub-decoder is a device that performs independent decoding at the same time. It updates the external information of each symbol according to the received data to be decoded and the calculation results of the last iteration, including an internal iteration controller and storing small interleaving tables and state likelihoods. Value storage, etc. P sub-decoders process data in parallel, and process P elements in parallel in each clock cycle.

The received signal memory is used to store the received signal, including 2*P RAMs, which are respectively used to store information bits and check bits. Each time a signal is received, it is selected and stored in RAM according to its position in the frame.

The external information memory is used to store external information, including P RAMs. In the first iteration, the extrinsic information is the initial value 0 (do not read the extrinsic information). In each iteration, the received signal and the corresponding extrinsic information are read out. After processing, the updated extrinsic information is written for the next iteration. Because the location of the external information read each time is the same as that of the received signal, the organization of the external information RAM is the same as that of the received signal RAM.

The RAM read-write controller mainly generates RAM read-write control signals and address signals.

The iterative controller mainly controls the iterative process.

The P small interleaving tables are designed according to the above interleaving principle and stored in the memory.

Claims (3)

1. improve the parallel decoding method of Turbo code decoding speed, it is characterized in that, this method be utilize the P of concurrent working independent do not have the interleaver of read/write conflict to improve decoding speed based on the little decoder of Turbo code iterative decoding with when the parallel decoding, described interpretation method contains following steps successively:

Step 1: all memories and controller are carried out initialization;

Step 2: P the table that interweaves for a short time deposited in the little interleaver that P memory constitutes, and described P the table that interweaves for a short time obtains according to following steps:

When P is an integer, and P and W prime number each other, then N is write as the matrix of the capable W row of P, then according to the order read-write of row, every behavior W element, common P is capable, and wherein, block length is W, and N is a code length, P=N/W, described P represents degree of parallelism; Thus, obtain the table that interweaves;

When P is an integer, but P and W establish the greatest common divisor that K is described P and W not each other during prime number, then N is write as the matrix of the capable W of P row, this matrix is divided into the K piece in the mode of the order of row, when the 0th of conversion, according to the sequential read of row, this piece is read as the matrix that each row has W element; When conversion I piece, the last I of this a piece element is mentioned this piece head in turn, according to the sequential read of row, this piece is read as each row matrix of W element then, I=1 wherein ..., K-1 obtains the table that interweaves thus;

When P is not integer, the decoding data afterbody is added 0, make new code length N satisfy P=N/W and become integer, again according to top method when P is integer, obtain the table that interweaves, after decoding, give up 0 of afterbody interpolation;

Again interweaving, in the ranks interweave again in the described advanced every trade of table that interweaves, interweave in perhaps going simultaneously and in the ranks interweave, the table that interweaved greatly, each row of the above-mentioned table that interweaves greatly forms the little table that interweaves, and obtains the table that interweaves greatly that the read-write of parallel decoding does not conflict;

Step 3: a frame data to decode is sent into the RAM read-write controller;

Step 4: the iteration control device sends iteration signal to affiliated RAM read-write controller, and simultaneously, the iterations counter begins counting;

Step 5: described RAM read-write controller is under the iteration control signal controlling, read the P blocks of data from described receiving signal memory, send into P sub-decoder concurrently, from P storage interweaves the interleaver of showing, read the table that interweaves simultaneously, carry out the decoding of Turbo code segmentation stepping type;

Step 6: described each sub-decoder pushes away earlier in advance to each blocks of data of input, initial value with the state likelihood value that obtains forward recursion, in each piece, carry out the segmentation recursion then, at this moment, forward recursion and reverse recursion carry out simultaneously, carry out the calculating of likelihood ratio and external information in the time of forward recursion;

Step 7:P sub-decoder read after each iteration after received signal and the corresponding external information, and calculating is sent to the RAM read-write controller with external information and is write the external information memory through iterative decoding, reads for a described P sub-decoder to be used for next iteration;

Step 8: it sends the iteration end signal to described iterations counter iterations to iteration control completely afterwards, and a described P sub-decoder sends hard decision information.

2. improve the code translator of Turbo code decoding speed, its feature mainly is: RAM read-write controller, P sub-decoder, P receiving signal memory, P external information memory, P little interleaver, iteration control device and iterations counter, wherein, P=N/W, N is a frame data to decode code length, W is a block length, and P is a degree of parallelism, wherein:

The iteration control device, output iteration control signal;

The RAM read-write controller is provided with the iteration control signal input part, the received signal of data to decode and the input of external information;

P receiving signal memory, the read-write control signal of this memory links to each other with the corresponding signal output part of described RAM read-write controller with the input of write data, and the output of this memory links to each other with the respective input of described RAM read-write controller;

The iterations counter, the count pulse output of this counter links to each other with described RAM read-write controller respective input;

P external information memory, the extrinsic information data of this memory, address signal input link to each other with the corresponding output end of described RAM read-write controller;

P sub-decoder adopts programmable logic device, and the output and the address signal output of the data to decode that the P of the P of this a code translator data, address signal input and described RAM read-write controller is individual after interweaving link to each other; The hard decision signal output part of this P sub-decoder and external information output link to each other with described RAM read-write controller respective input;

P little interleaver all is made of memory, and the individual little interleaver of described P is with following step formation and store the table that interweaves:

When P is an integer, and P and W prime number each other, then N is write as the matrix of the capable W row of P, then according to the order read-write of row, every behavior W element, common P is capable, and wherein, block length is W, and N is a code length, P=N/W, described P represents degree of parallelism; Thus, obtain the table that interweaves;

When P is an integer, but P and W establish the greatest common divisor that K is described P and W not each other during prime number, then N is write as the matrix of the capable W of P row, this matrix is divided into the K piece in the mode of the order of row, when the 0th of conversion, according to the sequential read of row, this piece is read as the matrix that each row has W element; When conversion I piece, the last I of this a piece element is mentioned this piece head in turn, according to the sequential read of row, this piece is read as each row matrix of W element then, I=1 wherein ..., K-1 obtains the table that interweaves thus;

When P is not integer, the decoding data afterbody is added 0, make new code length N satisfy P=N/W and become integer, again according to top method when P is integer, obtain the table that interweaves, after decoding, give up 0 of afterbody interpolation;

Interweaving, in the ranks interweave in the described advanced every trade of table that interweaves, interweave in perhaps going simultaneously and in the ranks interweave again, each row of the above-mentioned table that interweaves greatly forms the little table that interweaves; For a short time the table that interweaves stored obtain P little interleaver.

3. the code translator of raising Turbo code decoding speed according to claim 2 is characterized in that described Turbo code code translator has adopted the Virtex2p x2vp70ff1704-5 chip of xilinx company.

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