CN104425590A - MOS transistor and manufacturing method thereof - Google Patents

Abstract

The invention provides a MOS transistor and a manufacturing method thereof. The gate of the MOS transistor is embedded in the well region of the semiconductor substrate, and the source and drain of the MOS transistor are respectively located at opposite ends of the MOS transistor. In the above structure, after the source-drain voltage is applied to the MOS transistor, the carriers between the source and the drain migrate around the gate of the MOS transistor. Compared with the existing MOS transistor with a gate structure above the well region, the MOS transistor has Under the condition of occupying the same area on the bottom, the above technical solution can effectively increase the current density of the MOS transistor, and effectively avoid the short channel effect, thereby improving the performance of the MOS transistor.

Description

A kind of MOS transistor and its manufacturing method

technical field

The invention relates to the field of semiconductor preparation, in particular to a MOS transistor and a manufacturing method thereof.

Background technique

With the continuous development of integrated circuit (abbreviated as IC) technology, "Moore's Law" has been continuously fulfilled, the integration of integrated circuits is getting higher and higher, and the size of devices is also decreasing. challenge.

However, after the size of the MOS transistor device is reduced, the area occupied by the gate of the MOS transistor on the semiconductor substrate is reduced, which may reduce the current of the MOS transistor and finally affect the performance of the MOS transistor device.

Moreover, as shown in Figure 1, after the size of the MOS transistor device is reduced, the width L of the channel between the source (S) and drain (D) of the MOS transistor will be correspondingly smaller, and the source-drain PN junction shares the channel The ratio of the charge in the depletion region (Well) to the total charge in the channel increases accordingly, resulting in various short channel effects (Short Channel Effect, referred to as SCE), which leads to a decrease in gate control capability.

Specifically, the short channel effect includes: after a voltage is applied to the MOS transistor, the source (S) and drain (D) depletion regions of the MOS transistor expand continuously along the A direction and the B direction respectively, and when the channel After the channel width L is reduced, it is likely to cause the source-drain breakdown phenomenon (Punch Through) caused by the partial overlap of the depletion region of the source and drain, as well as the phenomenon of threshold voltage shift and the reduction of the drain induction barrier (Drain induction barrier lower, referred to as DIBL) and other undesirable phenomena.

Therefore, as the size of the MOS transistor decreases, how to increase the current of the MOS transistor without increasing the area occupied by the MOS transistor, and avoid the performance defects of the MOS transistor caused by the short channel effect to improve the performance of the integrated circuit, It is a problem that those skilled in the art need to solve urgently.

Contents of the invention

The problem solved by the present invention is to provide a MOS transistor and a manufacturing method thereof, which can effectively increase the current and current density of the MOS transistor, and can avoid defects such as short channel effects, thereby improving the performance of the MOS transistor.

In order to solve the above problems, the present invention provides a MOS transistor, comprising: a well region in a semiconductor substrate;

a well region within a semiconductor substrate;

a gate embedded in the well region;

A source and a drain are located in the well region and on both sides of the gate.

Optionally, the depth of the gate in the well region is greater than the depths of the source and drain.

Optionally, the depth of the gate is 1-5 times the depth of the source and drain.

Optionally, in plan view, the source and the drain are located on both sides of the middle section of the gate.

Optionally, it further includes a lightly doped region disposed in the well region and located on both sides of the gate, the depth of the lightly doped region is smaller than that of the source and the drain.

Optionally, the ions implanted in the lightly doped region are of the same type as the source and drain.

Optionally, the material of the gate is polysilicon.

Optionally, a gate dielectric layer is further included between the gate and the semiconductor substrate.

The present invention also provides a method for manufacturing a MOS transistor, comprising:

Provide semiconductor substrates;

implanting ions into the semiconductor substrate to form a well region;

forming a gate opening in the well region, filling the gate opening with a semiconductor material to form a gate;

In the well region, ions are respectively implanted into both sides of the gate to form a source and a drain.

Optionally, before filling the gate opening with semiconductor material, further comprising:

A gate dielectric layer is formed on the sidewall and bottom of the gate opening.

Optionally, the method for forming the gate dielectric layer is a thermal oxidation process.

Compared with the prior art, the technical solution of the present invention has the following advantages:

The gate of the MOS transistor is embedded in the well region of the semiconductor substrate, and the source and drain of the MOS transistor are respectively located at opposite ends of the MOS transistor. In the above structure, after the source-drain voltage is applied to the MOS transistor, the MOS transistor is surrounded, and the carrier migration occurs simultaneously on the side wall and the bottom surface of the gate of the MOS transistor, which is different from the existing MOS transistor with the gate above the well region. , the carriers between the source and the drain only pass through the bottom surface of the gate and the carrier migration occurs. Compared with the condition that the MOS transistor occupies the same area on the semiconductor substrate, the technical solution provided by the present invention can effectively improve the performance of the MOS transistor. Current and current density, thereby improving the performance of MOS transistors.

Description of drawings

FIG. 1 is a schematic structural diagram of an existing MOS transistor;

2 to 9 are schematic diagrams of the MOS transistor manufacturing process provided by an embodiment of the present invention;

FIG. 10 is a schematic structural diagram of a MOS transistor provided by another embodiment of the present invention;

11 and 12 are diagrams of the working principle of the MOS transistor provided by an embodiment of the present invention.

Detailed ways

As mentioned in the background art, as the integration level of integrated circuits continues to increase, the size of devices in integrated circuits is also reduced accordingly. However, after the size of MOS transistors is smaller, the area occupied by MOS transistors on the semiconductor substrate is correspondingly reduced, which in turn may The current of the MOS transistor is reduced and the performance of the MOS transistor is affected. In addition, after the size of the MOS transistor is reduced, the channel width between the source and the drain of the MOS transistor is reduced, so that the MOS transistor will appear such as source-drain breakdown phenomenon, threshold voltage shift and drain induction barrier A series of short-channel effects such as Drain induction barrier lower (DIBL for short) will reduce the performance stability of MOS transistors, and severe short-channel effects may even cause MOS transistors to fail.

Therefore, the present invention provides a MOS transistor and a manufacturing method thereof. The gate of the MOS transistor provided by the present invention is embedded in the well region of the semiconductor substrate, and the source and drain of the MOS transistor are located on both sides of the gate width direction, so after applying a voltage to the MOS transistor , the current flows around the gate. Compared with the existing MOS transistor, the MOS transistor provided by the present invention can effectively increase the current and current density of the MOS transistor without increasing the area occupied by the MOS transistor. In addition, the above structure can also effectively Reduce the probability of various short channel effects.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

The preparation method of the MOS transistor of the present invention specifically comprises:

Referring to FIG. 2 , a semiconductor substrate 100 is provided, and a shallow trench isolation region 200 is formed in the semiconductor substrate 100 .

The semiconductor substrate 100 may be a silicon substrate, or may be a germanium, silicon germanium, or gallium arsenide substrate, and common semiconductor substrates may be used as the semiconductor substrate in this embodiment.

In this embodiment, the semiconductor substrate is preferably a silicon substrate.

In this embodiment, the specific formation process of the shallow trench isolation region 200 may include: first forming an oxide layer 110 on the substrate 100; depositing a hard mask layer on the oxide layer 110 120. The hard mask layer 120 may optionally be a silicon nitride layer.

A layer of photoresist (not shown in the figure) is covered above the mask layer 120. After the photolithography process, the photoresist layer is used as a mask to pattern the hard mask layer 120, and The hard mask layer 120 is used as a mask, and the semiconductor substrate 100 is etched by using gas containing Cl ₂ , HBR, CF ₄ and the like as a dry etchant to form openings.

After that, the opening can be filled with oxide such as CVD (Chemical Vapor Deposition), so as to form the shallow trench isolation region 200 in the semiconductor substrate 100 .

Referring to FIG. 3 , FIG. 3 is a top view of the semiconductor device in FIG. 2 . The shallow trench isolation region 200 is ring-shaped. During the fabrication process of the MOS transistor, the gate, source and drain of the subsequently formed MOS transistor are all within the range surrounded by the shallow trench isolation region 200 . During the IC manufacturing process, multiple MOS transistors can be formed simultaneously on one semiconductor substrate 100 , and the shallow trench isolation region 200 is used to isolate the active regions of the sources of two adjacent MOS transistors.

Referring to FIG. 4 and FIG. 5 , FIG. 5 is a top view of the semiconductor device in FIG. 4 . After the hard mask layer 120 is removed, ions are doped into the semiconductor substrate 100 to form a well region 300 . If the MOS transistor is an nMOS transistor, the ions may be P-type ions such as B, and if the MOS transistor is a pMOS transistor, the ions may be n-type ions such as As and P.

In this embodiment, the specific process of forming the well region 300 may include: forming a photoresist layer (not shown in the figure) above the oxide layer 110, and then patterning the photoresist layer through a photolithography process. After the glue layer is formed, ions are implanted into the oxide layer 110 and the semiconductor substrate 100 using the photoresist layer as a mask, so as to form the well region 300 in the semiconductor substrate 100 .

It should be noted that, after the formation of the shallow trench isolation region 200 , the oxide layer 110 can be removed or remain.

In this embodiment, the ion implantation process is performed under the condition that the oxide layer 110 remains. During the formation of the well region 300, the oxide layer 110 can effectively prevent damage to the semiconductor substrate during the implantation process, and the oxide layer 110 can also be used as a shielding layer, which can effectively control the implantation of impurities during the implantation process. The depth improves the performance of the formed well region 300 . However, removing the oxide layer 110 does not hinder the formation of the well region 300 .

In this embodiment, the depth h1 of the well region 300 is greater than the depth h2 of the STI region 200 .

It is worth noting that this embodiment adopts the process flow of forming the shallow trench isolation region 200 first, and then forming the well region 300. In other embodiments except this embodiment, the well region 300 can also be formed first. The shallow trench isolation region 200 is formed later, which will not affect the performance of the finally obtained MOS transistor.

Referring to FIG. 6, a gate opening (not marked in the figure) is opened in the well region 300, and a layer of gate oxide layer 410 is covered on the sidewall and bottom of the gate opening, and then the gate opening is The semiconductor material is filled inside to form the gate 400 .

In this embodiment, the specific formation process of the gate includes:

A hard mask layer (not shown in the figure) may be formed on the oxide layer 110, a photoresist layer is formed on the hard mask layer, and after the photolithography process, the patterned photoresist Patterning the hard mask layer as a mask, using the hard mask layer as a mask to etch the oxide layer 110 and the semiconductor substrate 100 by a dry etching process to form the gate opening;

Afterwards, a gate oxide layer 410 is formed on the inner wall (including the bottom and the sidewall) of the gate opening.

In this embodiment, the material of the gate oxide layer 410 is silicon oxide, and its formation process is a thermal oxidation process. The thermal oxidation process includes, under the condition of 950° C. to 1050° C., passing O ₂ into the reaction chamber, so as to form a silicon oxide layer on the inner wall and bottom of the gate opening.

It is worth noting that, in other embodiments except this embodiment, the gate oxide layer can be a silicon oxide layer formed by CVD process, or can be formed by CVD process such as aluminum oxide (AL ₂ O ₃ ). , barium strontium titanate (BST), lead zirconate titanate (PZT), ZrSiO ₂ , HfSiO ₂ , HfSiON, TaO ₂ and HfO ₂ and other high-K dielectric layers. The material and formation process of the gate oxide layer do not affect the protection scope of the present invention.

After the gate oxide layer 410 is formed, semiconductor material is filled on the gate oxide layer 410 in the gate opening to form the gate 400 .

In this embodiment, the semiconductor material may be polysilicon, and the polysilicon may be formed using a CVD process. Further, the polysilicon may be doped polysilicon, and its formation process includes: using a silane material containing P plasma, filling the gate opening with a polysilicon material doped with P and other atoms by using a CVD process.

Continuing to refer to FIG. 6 , in this embodiment, the depth h3 of the gate 400 is smaller than the depth h2 of the STI region 200 . However, in other embodiments except this embodiment, the depth h3 of the gate 400 can also be greater than the depth h2 of the STI region 200 , which does not affect the performance of the formed MOS transistor. But the depth h3 of the gate 400 must be smaller than the depth h1 of the well region 300 , that is, the gate 400 must be located in the well region 300 .

FIG. 7 is a top view of the semiconductor device in FIG. 6 , as shown in FIG. 7 , the gate 400 is located in the middle of the well region 300 .

Referring to FIG. 8 , after the gate 400 is formed, ions are implanted into both sides of the gate 400 in the well region 300 to form a source 420 and a drain 430 . When the MOS transistor is a pMOS transistor, the implanted ions can be P-type ions such as B; when the MOS transistor is an nMOS transistor, the implanted ions can be n-type ions such as As and P, which are determined according to actual requirements.

In this embodiment, the depth h8 of the source 420 and the drain 430 is smaller than the depth h3 of the gate 400 in the well region 300, and the depth h8 of the source 420 and the drain 430 is smaller than the depth h8 of the shallow trench The depth h2 of the trench isolation region 200 .

The specific process of forming the source and drain electrodes may include: first covering the semiconductor substrate 100 with a photoresist layer (not shown in the figure), and after exposure and development processes, exposing the gate 400 on both sides region, and using the photoresist layer as a mask to implant corresponding ions into the semiconductor substrate 100, and activate the ions in the source and drain electrodes after annealing and other processes to form the source electrode 420 and the drain electrode 430 .

In this embodiment, the ratio of the depth h3 of the gate 400 to the depth h8 of the source 420 and the drain 430 is: 1<h3:h8≤5, for example, h8 is The h3 is preferably The specific value is determined according to the operating voltage to be applied to the formed MOS transistor, wherein the greater the operating voltage applied to the MOS transistor, the greater the values of h3:h8.

In this embodiment, the ion concentration in the source electrode 420 and the drain electrode 430 is 10 ¹³ -10 ¹⁷ /cm ³ .

Referring to FIG. 9 , FIG. 9 is a top view of the semiconductor device in FIG. 8 . The source 420 and the drain 430 are located on both sides of the middle section of the gate 400 . The length of the side of the gate 400 corresponding to the source and drain is h6, and the length of the source 420 and the drain 430 is h7, wherein h6≧h7.

In this embodiment, h6>h7, on the corresponding two sides of the gate 400 and the source 420 and the drain 430, the gate 400 extends to the outside of the source 420 and the drain 430, Sides of the source 420 and the drain 430 are completely attached to the gate 400 .

In other embodiments, when h6=h7, the sides corresponding to the gate 400 and the source 420 , and the sides corresponding to the gate 400 and the drain 430 are completely attached.

It should be noted that, in this example, the source and drain are close to the gate 400 . Referring to FIG. 10, in another embodiment of the present invention, before the formation of the source 420 and the drain 430, some ions can be implanted on both sides of the gate 400 to form two lightly doped impurity region, the first lightly doped region 440 and the second lightly doped region 450. Wherein, the ion types implanted in the two lightly doped regions 440 and 450 are the same as the ion types implanted in the source electrode 420 and the drain electrode 430 to be formed later, if the MOS transistor is a pMOS transistor, the two lightly doped regions The ions implanted in the doped regions 440 and 450 are P-type ions such as B; if the MOS transistor is an nMOS transistor, the ions implanted in the two lightly doped regions 440 and 450 are n-type ions such as As and P. .

Afterwards, the source 420 is formed on the other side of the first lightly doped region 440 opposite to the gate 400 , and on the other side of the second lightly doped region 430 opposite to the gate 400 The drain 430 is formed on the other side. The ion concentration in the first lightly doped region 440 is lower than the ion concentration in the source electrode 420, and the depth of the first lightly doped region 440 is smaller than the depth of the source electrode 420; the ion concentration in the second lightly doped region 450 is smaller than that in the drain electrode 430 The depth of the second lightly doped region 450 is smaller than the depth of the drain 430 .

In this embodiment, the width of the first lightly doped region 440 is h5, and the width of the second lightly doped region 450 is h4, and the specific values of h4 and h5 are based on the working load of the MOS transistor Voltage value for specific settings. Generally, the greater the value of the operating voltage, the greater the values of h4 and h5.

The present invention also provides a MOS transistor, the specific structure of which is shown in combination with reference to FIGS. 11 and 12 , wherein FIG. 12 is a top view of the semiconductor device shown in FIG. 11 .

The MOS transistors include:

The well region 300 in the semiconductor substrate 100; if the MOS transistor is a pMOS transistor, the well region 300 is doped with N-type ions such as As and P; if the MOS transistor is an nMOS transistor, the well region 300 is doped with P-type ions such as B.

The gate 400 embedded in the semiconductor substrate 100, wherein the depth h3 of the gate 400 in the well region 300 is smaller than the depth h1 of the well region 300, that is, the gate 400 is embedded in the well region 300 .

In this embodiment, the gate 400 may be made of intrinsic polysilicon or doped polysilicon.

A gate oxide layer 410 is provided between the gate 400 and the semiconductor substrate 100 , and the gate oxide layer 410 wraps the sidewall and the bottom of the gate 400 . The gate oxide layer 410 may be made of silicon oxide or such as aluminum oxide (AL ₂ O ₃ ), barium strontium titanate (BST), lead zirconate titanate (PZT), ZrSiO ₂ , HfSiO ₂ , HfSiON, TaO ₂ and high-K dielectric layers such as HfO ₂ .

In this embodiment, the gate oxide layer 410 is silicon oxide.

Located in the well region 300 , a source 420 and a drain 430 are arranged on both sides of the gate 400 . Wherein, the depth h8 of the source 420 and the drain 430 is smaller than the depth h3 of the gate 400 embedded in the well region 300;

Referring to FIG. 12 , the source 420 and the drain 430 are located on both sides of the middle section of the gate 400 . Specifically, the length of the side of the gate 400 corresponding to the source and drain is h6, and the length of the source 420 and the drain 430 is h7, wherein h6≧h7.

In this embodiment, h6>h7, on the corresponding two sides of the gate 400 and the source 420 and the drain 430, the gate 400 extends to the outside of the source 420 and the drain 430, Sides of the source 420 and the drain 430 are completely attached to the gate 400 .

In other embodiments, when h6=h7, the sides corresponding to the gate 400 and the source 420 , and the sides corresponding to the gate 400 and the drain 430 are completely attached.

And the sides of the source 420 and the drain 430 corresponding to the gate 400 are completely attached to the gate 400 .

It should be noted that in this implementation, the source and drain are close to the gate 400 . Referring to FIG. 10, in the MOS transistor provided in another embodiment of the present invention, a first lightly doped region 440 is provided between the source 420 and the gate 400, and the drain 430 and the A second lightly doped region 450 is disposed between the gates 400 . The specific values of the distance h4 between the first lightly doped region 440 and the gate 400 and the distance h5 between the second lightly doped region 450 and the gate 400 depend on the load of the MOS transistor. The working voltage value can be set specifically. Generally, the greater the value of the operating voltage, the greater the values of h4 and h5.

The ion concentration in the first lightly doped region 440 is lower than the ion concentration in the source 420, and the depth of the first lightly doped region 440 is smaller than the depth of the source 420; the ion concentration in the second lightly doped region 450 is lower than that in the drain The ion concentration in the electrode 430, the depth of the second lightly doped region 450 is smaller than the depth of the drain 430.

Continuing to refer to FIG. 11 , shallow trench isolation regions 200 are provided on two sides of the source 420 and the drain 430 opposite to the gate 400 . In this embodiment, parallel to the surface of the semiconductor substrate 100 , the shallow trench isolation region 200 is disposed around the gate 400 , the source 420 and the drain 430 of the MOS transistor.

In this embodiment, the depth h2 of the shallow trench isolation region 200 is smaller than the depth h1 of the well region 300, the depth h2 of the shallow trench isolation region 200 is greater than the depth of the source 420 and the drain 430, and the The depth h2 of the STI region 200 is not directly related to the depth h3 of the gate 400 .

As shown in Figure 11 and Figure 12, during the use of the MOS transistor, after the source-drain voltage is applied to the MOS transistor, the carriers go around along the f, a, and c directions (or g, b, and d directions). The sidewall and the bottom of the gate 400 flow, while the gate of the existing MOS transistor is located above the substrate, and the carriers only flow at the bottom of the gate. Compared with the existing MOS transistors, the MOS transistor provided by this embodiment greatly increases the area of the carrier flow between the source 420 and the drain 430 under the condition of occupying the same area of the semiconductor substrate 100, thereby increasing The current and current density of the MOS transistor; and, the depletion directions of the source 420 and the drain 430 and the well region are along the directions of a, b, c, d, f and g, and the channel direction I (from the source The direction to the drain) is vertical, which can effectively reduce the occurrence probability of short channel effects such as source-drain punchthrough.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (11)

1. a MOS transistor, is characterized in that, comprising:

Well region in Semiconductor substrate;

Be embedded in the grid in well region;

Be positioned at described well region, and be positioned at source electrode and the drain electrode of described grid both sides.

2. MOS transistor as claimed in claim 1, it is characterized in that, the degree of depth of described grid in described well region is greater than the degree of depth of described source electrode and drain electrode.

3. MOS transistor as claimed in claim 2, is characterized in that, the degree of depth of described grid is 1 ~ 5 times of described source electrode and the drain electrode degree of depth.

4. MOS transistor as claimed in claim 1, is characterized in that, overlook face, and described source electrode and drain electrode are positioned at the both sides at position, described grid stage casing.

5. MOS transistor as claimed in claim 1, it is characterized in that, also comprise and being arranged in described well region, and be positioned at the light doping section of described grid both sides, the degree of depth of described light doping section is less than source electrode and drain electrode.

6. MOS transistor as claimed in claim 5, is characterized in that, the ion injected in described light doping section and described source electrode are identical type with draining.

7. MOS transistor as claimed in claim 1, it is characterized in that, the material of described grid is polysilicon.

8. MOS transistor as claimed in claim 7, is characterized in that, also comprise gate dielectric layer between described grid and Semiconductor substrate.

9. a MOS transistor manufacture method, is characterized in that, comprising:

Semiconductor substrate is provided;

In described Semiconductor substrate, inject ion, form well region;

In described well region, form gate openings, in described gate openings, fill full semi-conducting material, form grid;

In described well region, inject ion respectively to described grid both sides, form source electrode and drain electrode.

10. MOS transistor manufacture method as claimed in claim 9, is characterized in that, in described gate openings before filling semiconductor material, also comprise:

At sidewall and the bottom formation gate dielectric layer of described gate openings.

11. MOS transistor manufacture methods as claimed in claim 10, is characterized in that, the method forming described gate dielectric layer is thermal oxidation technology.