CN104425351A - Trench forming method and semiconductor device manufacturing method - Google Patents

Abstract

The application discloses a method for forming a trench and a method for manufacturing a semiconductor device. An example method may include: forming a hard mask layer on a substrate; forming an etch stop defining layer on the hard mask layer; patterning the etch stop defining layer and the hard mask layer respectively to form a A pattern corresponding to the formed trench; using the patterned etch stop determining layer and the hard mask layer as a mask, the substrate is etched to form a trench therein, wherein the etching of the substrate simultaneously Etching the etching stop determining layer; and detecting a signal indicating that the etching stop determining layer is etched to an end point to determine the stop of etching the substrate.

Description

Trench forming method and semiconductor device manufacturing method

technical field

The present disclosure relates to the field of semiconductors, and more particularly, to a method for forming a trench and a method for manufacturing a semiconductor device.

Background technique

Forming recessed trenches in a substrate is desired in many applications. However, with the continuous miniaturization of devices, it is difficult to effectively control the formation of such trenches, especially their depth and depth uniformity.

Contents of the invention

The purpose of the present disclosure is at least in part to provide a trench forming method and a semiconductor device manufacturing method to better control the depth and depth uniformity of the formed trenches.

According to an aspect of the present disclosure, there is provided a method of forming a trench in a substrate, comprising: forming a hard mask layer on the substrate; forming an etch stop determining layer on the hard mask layer; Patterning the stop determining layer and the hard mask layer to form a pattern corresponding to the groove to be formed therein; using the patterned etching stop determining layer and the hard mask layer as a mask to etch the substrate, to form a trench therein, wherein the etching of the substrate is simultaneously performed on the etching stop determining layer; and detecting a signal indicating that the etching stop determining layer is etched to an end point to determine the etching of the substrate stop.

According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, comprising: according to the above method, forming a trench in a substrate; forming sidewalls on sidewalls of the trench; filling the trench with a shielding layer ; forming source/drain regions on both sides of the trench in the substrate; and removing the masking layer filled in the trench, and forming a gate stack in the trench.

According to an exemplary embodiment of the present invention, an etch stop determination layer is formed on the hard mask layer. By detecting a signal indicating that the etch stop determination layer is etched to an end point, the stop of etching of the substrate can be determined. In this way, the depth uniformity of the resulting grooves can be improved.

Description of drawings

The above and other objects, features and advantages of the present disclosure will be more clearly described through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

1-6 are schematic diagrams illustrating various stages in the process of forming a trench in a substrate according to an embodiment of the present disclosure; and

7-17 are schematic diagrams illustrating various stages in the process of manufacturing a semiconductor device based on trenches according to another embodiment of the present disclosure.

Detailed ways

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions/layers with different shapes, sizes, and relative positions can be additionally designed as required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, the layer/element can be directly on the other layer/element, or there may be intervening layers/elements in between. element. Additionally, if a layer/element is "on" another layer/element in one orientation, the layer/element can be located "below" the other layer/element when the orientation is reversed.

According to an embodiment of the present disclosure, a method of forming a trench in a substrate is provided. According to the method, a hard mask layer is formed on the substrate, which can serve as a mask when the substrate is subsequently etched. In order to strengthen the control of substrate etching, especially the control of etching depth and depth consistency, an etching stop determination layer can be formed on the hard mask layer. The material of the etch stop determining layer can be selected to be etched together with the substrate. In this way, the stop of the etching of the substrate can be determined by detecting a signal indicating that the etching stop determination layer is etched to the end (ie, substantially completely etched away). For example, the respective etching rates of the layer and the substrate can be determined according to the depth of the groove to be etched and the etching stop (for example, when the materials of the two are the same, their etching rates can be approximately the same), determine The etch stop determines the thickness of the layer.

Before etching the substrate, the etch stop determining layer and the hard mask layer may be respectively patterned to form patterns therein corresponding to trenches to be formed. In this way, the substrate can then be etched using them as a mask to form corresponding trenches therein.

After the trenches are thus formed, semiconductor devices such as field effect transistors (FETs) can be further fabricated on the basis of the trenched substrate. According to an example, a gate stack may be formed within the trench. To this end, spacers may be formed on the sidewalls of the trenches, which then serve as gate spacers. In order to avoid the influence of the source/drain formation process on the gate stack, the source/drain region can be formed first, and then the gate stack can be formed. For example, a masking layer may be filled in the trench to shield the trench (and the underlying substrate portion, which then acts as a channel region). Subsequently, source/drain regions may be formed on both sides of the trench in the substrate, for example, by means of ion implantation. Next, the masking layer can be removed, and a gate stack can be formed in the trench. The gate stack can be in various suitable forms, such as a stack of a high-K gate dielectric and a metal gate conductor (and optionally a work function adjusting layer sandwiched therebetween).

According to an advantageous example, in order to avoid the manufacturing difficulties of the contact portion of the source/drain region (especially in the case of continuous miniaturization of devices), after the source/drain region is formed, the part of the substrate located on both sides of the trench can be silicided processing to form contacts to the source/drain regions. This silicidation process has essentially no effect on the trench (and the portion of the substrate below it) due to the presence of a masking layer (usually a dielectric material) in the trench. Thus, the contacts are self-aligned to the source/drain regions on both sides of the trench. Moreover, the formation of such a contact portion does not require etching and filling of a contact hole, which simplifies the process.

The disclosure can be presented in various forms, some examples of which are described below.

As shown in FIG. 1 , a substrate 1000 is provided. The substrate 1000 may be a suitable substrate in various forms, for example, a bulk semiconductor substrate such as Si, Ge, etc., a compound semiconductor substrate such as SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, InGaSb etc., semiconductor-on-insulator substrate (SOI), etc. Here, an SOI substrate and a silicon-based material are taken as examples for description. However, it should be noted that the present disclosure is not limited thereto.

Specifically, the SOI substrate 1000 may include a stacked base substrate 1000-1, a buried insulating layer 1000-2, and an SOI layer 1000-3. For example, the base substrate 1000-1 may include bulk silicon. The buried insulating layer 1000-2 may include oxide (such as silicon oxide) with a thickness of, for example, about typical as The SOI layer 1000-3 may comprise crystalline silicon with a thickness of, for example, about typical as

In the substrate 1000, shallow trench isolations (STIs) 1002 for defining active regions are also formed. STI 1002 may, for example, comprise oxide and extend into buried insulating layer 1000-2 to ensure effective electrical isolation. Those skilled in the art can think of many ways to form this STI, which will not be repeated here. In addition, a pad oxide layer 1004 may also be formed on the surface of the substrate 1000 . The pad oxide layer 1004 can be formed, for example, by thermal oxidation or deposition, and the thickness can be about typical as

Then, as shown in FIG. 2, a hard mask layer 1006 may be formed on the substrate 1000 (or, on the pad oxide layer 1004), eg, by deposition such as low pressure chemical vapor deposition (LPCVD). For example, the hard mask layer 1006 may comprise a nitride (such as silicon nitride) or an oxynitride (such as silicon oxynitride) with a thickness of about typical as

As described above, to improve etch control, an etch stop defining layer 1010 may be formed on the hard mask layer 1006, eg, by deposition. In this example, etch stop determining layer 1010 includes the same silicon material as the substrate, such as amorphous silicon. However, the present disclosure is not limited thereto, and the etch stop determining layer 1010 may also include other materials than the substrate. In addition, in order to improve the bonding between the hard mask layer 1006 and the etch stop defining layer 1010, a pad oxide layer 1008 may be first formed (eg, deposited) on the hard mask layer 1006, and its thickness may be about typical as An etch stop defining layer 1010 is then formed on the pad oxide layer 1008 .

Here, the etch stop determining layer 1010 can be determined according to the etching rate of the substrate (specifically, the SOI layer 1000-3) and the etch stop determining layer 1010 and the depth to be etched according to the subsequently adopted etching scheme. thickness of. In this example, since both the SOI layer 1000-3 and the etching stop determining layer 1010 are silicon materials (one is crystalline silicon and the other is amorphous silicon), their etching rates can be achieved by selecting an appropriate etching scheme. Much the same. In this case, the thickness of the etch stop determining layer 1010 may be set to be substantially the same as the depth to be etched.

Next, etching can be performed. Specifically, as shown in FIG. 3, a photoresist 1012 may be formed on the etching stop determining layer 1010, and the photoresist 1012 is patterned by photolithography to form an opening corresponding to the groove to be formed therein. G1. Then, using the patterned photoresist 1012 as a mask, selective etching such as reactive ion etching (RIE) can be performed on the etch stop determining layer 1010 and the hard mask layer 1006 in sequence, so as to transfer the pattern of the opening G1 into it, thereby forming an opening G2 therein. In this example, pad oxide layers 1004 and 1008 are also etched, thereby also forming opening G2 therein. Then, the photoresist 1012 may be removed, as shown in FIG. 5 .

Next, as shown in FIG. 6, the patterned etch stop determination layer 1010 and the hard mask layer 1006 can be used as a mask to etch the substrate (specifically, the SOI layer 1000-3) such as RIE to The groove G3 is formed therein. Here, the time to stop etching the substrate can be determined according to the signal indicating that the etching stop determining layer 1010 has been etched to an end point. For example, the etching of the substrate can be stopped as soon as the end signal is detected; or, a certain degree of over-etching can be performed after the end signal is detected. For the detection of the endpoint signal, those skilled in the art can conceive of various schemes. For example, it can be judged whether the etching stop determination layer 1010 has been etched by detecting the etching product (for example, when a nitrogen-containing product is detected, it can be judged that the etching has reached the hard mask layer 1006, and thus it can be judged etch stop determining layer 1010 has been etched).

According to an example, after etching, the thickness of the SOI layer 1000-3 remaining under the trench is about 2-20 nm. This portion of the SOI layer below the trench can then act as the channel region CH of the device. Subsequently, pad oxide layer 1008, hard mask layer 1006, and pad oxide layer 1004 may be removed.

Thus, trench G3 is formed in the substrate (specifically, SOI layer 1000-3). Since the etching stop condition of the trench G3 can be effectively controlled, the depth of the trench G3 and its depth consistency can be effectively controlled.

Based on such groove G3 formed in the substrate, various structures can be fabricated. Hereinafter, an example of fabricating a semiconductor device such as a FET is described, in which a gate stack may be formed in the trench G3.

Compatible with the gate stack to be formed in the trench, gate spacers may be formed on the sidewalls of the trench. Specifically, as shown in FIG. 7 , an oxide layer 1014 (for example, by in-situ vapor growth (ISSG)) and a nitride layer 1016 (for example, by deposition) can be sequentially formed on the substrate on which the trench is formed. The thickness of the oxide layer 1014 can be about typical as ; The thickness of the nitride layer 1016 can be about typical as Afterwards, as shown in FIG. 8 , anisotropic etching such as RIE may be performed on the nitride layer 1016 to form sidewalls. It should be noted here that, according to another example, the oxide layer 1014 may not be formed, but only the nitride layer 1016 may be formed.

In the case of forming the oxide layer 1014, after forming the oxide layer 1014 and before forming the nitride layer 1016, optionally, well implantation and threshold voltage adjustment implantation may also be performed.

Subsequently, a masking layer may be filled in the trenches. Specifically, as shown in FIG. 9, a layer thick enough to fill the trench can be formed on the structure shown in FIG. 8, for example, by high aspect ratio deposition process (HARP) or high density plasma (HDP) deposition. Masking material 1018 for the slot. The masking material 1018 may include an oxide. Then, as shown in FIG. 10, a planarization process such as chemical mechanical polishing (CMP) may be performed. This planarization process may use the SOI layer 1000-3 (silicon in this example) as a stop layer. In this way, the shielding layer 1018 remains in the trench and exposes the portions of the SOI layer 1000-3 located on both sides of the trench, so as to facilitate the subsequent processing of the source/drain regions.

Then, as shown in FIG. 11 , source/drain regions (not shown) may be formed on both sides of the trench (especially both sides of the channel region CH) in the substrate, for example, by ion implantation. For example, for an n-type device, n-type impurities such as P, As, etc. can be implanted; for a p-type device B, etc., p-type impurities can be implanted. After ion implantation, annealing such as spike annealing may also be performed to activate the implanted ions.

It should be pointed out here that the method of forming the source/drain region is not limited to ion implantation. A portion of the SOI layer 1000-3 located on both sides of the trench can be removed by selective etching. Source/drain regions may then be formed by epitaxially growing an additional semiconductor layer (not shown). Simultaneously with the epitaxial growth, in-situ doping can be performed. The grown semiconductor layer may include a material different from the SOI layer 1000-3 (eg, SiGe or Si:C), so that stress may be applied to the channel region CH to enhance device performance.

According to an advantageous example, source/drain contact portions can be directly formed on both sides of the trench through silicidation. Specifically, as shown in FIG. 13 , a metal layer 1020 may be formed on the substrate, for example, by deposition. The metal layer 1020 may include Ni, Ti, Co or alloys thereof in an amount sufficient to fully react with the underlying SOI layer 1000-3 to form a metal silicide. Afterwards, annealing such as rapid thermal annealing (RTA) can be performed, so that the metal layer 1020 and the SOI layer 1000-3 (specifically, the silicon therein) undergo a silicide reaction, thereby obtaining a metal silicide 1022, and the redundant metal layer 1020 can be removed , as shown in Figure 14. This metal silicide 1022 is self-aligned to the source/drain regions formed in the SOI layer 1000-3, and thus can serve as a contact to the source/drain regions. Subsequently, as shown in FIG. 15 , the masking layer 1018 may be removed, for example, by BOE or dilute hydrofluoric acid solution.

In this case, in order to avoid damaging the formed metal silicide 1022 due to too long etching time when removing the masking layer 1018 , the masking layer 1018 may be partially removed as shown in FIG. 12 before the silicidation process. FIG. 13 shows a situation where a metal layer 1020 is formed on the structure after partial removal of the masking layer 1018 .

In the example of FIG. 14, metal suicide 1022 is shown extending the entire thickness of SOI layer 1000-3. However, the present disclosure is not limited thereto. For example, the metal silicide 1022 may be formed on the upper portion of the SOI layer 1000-3 near the surface without extending to the bottom of the SOI layer 1000-3.

Next, a gate stack may be formed inside the spacer 1016 in the trench. Specifically, as shown in FIG. 16 , a gate dielectric layer 1026 and a gate conductor layer 1030 may be sequentially formed on the structure shown in FIG. 15 . The gate dielectric layer 1026 may include a high-K gate dielectric such as HfO ₂ , with a thickness of, for example, about The gate conductor layer 1030 may include a metal gate conductor such as Ti, Ni, or the like. In addition, between the gate dielectric layer 1026 and the substrate, for example, an interface oxide layer 1024 can be formed by thermal oxidation or deposition, with a thickness of about A work function adjustment layer 1028, such as TiN, may be included between the high-K gate dielectric layer and the metal-poor conductor. Subsequently, a planarization process such as CMP may be performed to expose the source/drain contact portion 1022 . It can be seen that the gate stack has substantially the same height as the source/drain contact 1022 . This facilitates the fabrication of subsequent interconnect structures.

In this way, the semiconductor device according to this embodiment is obtained. The semiconductor device may include a gate stack embedded within a trench formed in a substrate. The gate stack may include a gate dielectric layer 1026 and a gate conductor layer 1030 (and optionally an interface oxide layer 1024 and a work function adjusting layer 1028). The part of CH in the substrate under the gate stack can be used as the channel region of the device. The semiconductor device further includes source/drain regions formed on both sides of the gate stack in the substrate (more specifically, both sides of the channel region), and source/drain contact portions 1022 formed in the substrate with the source/drain regions. The source/drain contact portion 1022 may include a metal silicide formed by siliciding the substrate portions on both sides of the trench.

It should be pointed out here that although the SOI substrate is taken as an example in the above description, the technology disclosed in the present disclosure may be applicable to various other substrates. In addition, in the above-described embodiments, trenches are formed to form gate stacks therein, but the technology of the present disclosure can be applied to various applications requiring the formation of trenches.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design a method that is not exactly the same as the method described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be advantageously used in combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the present disclosure, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims (15)

1. form a method for groove in the substrate, comprising:

Substrate forms hard mask layer;

Hard mask layer is formed etching stopping and determines layer;

Respectively etching stopping is determined that layer and hard mask layer carry out composition, with the pattern that the groove formed with will be formed is corresponding wherein;

Determine that layer and hard mask layer are for mask, etch substrate with the etching stopping of composition, to form groove wherein, wherein, to etching stopping, the etching of substrate is determined that layer etches simultaneously; And

Detect instruction etching stopping and determine that layer is etched into the signal of terminal, to determine the stopping to substrate etching.

2. method according to claim 1, wherein, substrate comprises silicon, and etching stopping determines that layer comprises amorphous silicon.

3. method according to claim 2, wherein, hard mask layer comprises nitride.

4. method according to claim 3, also comprises:

Substrate is formed the first pad oxide skin(coating), and wherein hard mask layer is formed on this first pad oxide skin(coating); And/or

Hard mask layer is formed the second pad oxide skin(coating), and wherein etching stopping determines that layer is formed on this second pad oxide skin(coating).

5. manufacture a method for semiconductor device, comprising:

According to the method such as according to any one of claim 1-4, form groove in the substrate;

Form side wall on the sidewalls of the trench;

Fill shielding layer in the trench;

Groove both sides formation source/drain region in the substrate; And

Remove the shielding layer of filling in groove, and it is stacking to form grid in the trench.

6. method according to claim 5, wherein, formation source/drain region after and removal shielding layer before, the method also comprises:

Part substrate being positioned to groove both sides carries out silicidation, to form the contact site with source/drain region.

7. method according to claim 5, wherein, substrate comprises semiconductor-on-insulator SOI substrate, and SOI substrate comprises the base substrate, buried insulating layer and the soi layer that stack gradually, and wherein the S0I layer thickness of beneath trenches is about 2-20nm.

8. method according to claim 5, wherein, forms side wall and comprises:

The fluted substrate of formation forms oxide skin(coating);

Form nitride layer on the oxide layer; And

Anisotropic etching is carried out to nitride layer, to form side wall.

9. method according to claim 5, wherein, the thickness of side wall is about 3-50nm.

10. method according to claim 5, wherein, shielding layer comprises oxide.

11. methods according to claim 5, wherein, form source/drain region and comprise:

Ion implantation is carried out to substrate.

12. methods according to claim 5, wherein, carry out silicidation and comprise:

Substrate forms metal level; And

Anneal, make metal level and substrate generation silicification reaction.

13. methods according to claim 12, wherein, before formation metal level, the method also comprises:

Part removes shielding layer.

14. methods according to claim 12, wherein, metal level comprises Ni, Ti, Co or its alloy.

15. methods according to claim 5, wherein, grid are stacking comprises high-K gate dielectric and metal gate conductor.