CN105244379A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor device, comprising: the fin structures extend and are distributed on the substrate along a first direction, wherein the material of the fin structures is different from that of the substrate; the source region, the channel region and the drain region are distributed in the top of the fin structure in an extending mode along the first direction; the grid electrode stacks extend and are distributed above the channel region along the second direction; and the grid side walls are arranged on two sides of the grid stack along the first direction. According to the semiconductor device and the manufacturing method thereof, the fin structures of the devices made of different materials are epitaxially grown from the fine grooves in the substrate, the upward propagation of interface defects is inhibited in the grooves with proper depth-to-width ratios, the reliability of the devices is improved, and the carrier mobility of the channel regions of the devices is effectively improved.

Description

Semiconductor device and manufacturing method thereof

technical field

The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a fin field effect transistor (FinFET) based on Ge material and a manufacturing method thereof.

Background technique

As the size of semiconductor devices continues to shrink, enhancing the mobility of channel carriers has become a very important technology. In the design of the substrate stress layer, different materials have different characteristics, such as lattice constant, dielectric constant, band gap, especially carrier mobility, etc., as shown in Table 1 below.

Table 1

It can be seen from Table 1 that among the above-mentioned possible substrate materials, Ge has the highest hole mobility and higher electron mobility, and using Ge as the substrate of semiconductor devices will greatly enhance the carrier mobility, thus enabling Manufacturing faster large-scale integrated circuits (LSICs).

In addition, it can be seen from Table 1 that Ge also has a lattice constant similar to that of Si materials, so Ge can be easily integrated on Si substrates commonly used in semiconductor processes, making it possible to manufacture performance Better semiconductor devices that increase performance while reducing cost.

On the other hand, in order to meet the challenges brought by the continuous miniaturization of semiconductor devices, a variety of high-performance devices have been proposed, especially in the current sub-20nm technology, three-dimensional multi-gate devices (FinFET or Tri-gate) are the main The device structure, which enhances gate control capability, suppresses leakage and short channel effects.

For example, compared with the traditional single-gate body Si or SOIMOSFET, the double-gate SOI MOSFET can suppress the short-channel effect (SCE) and drain-induced barrier lowering (DIBL) effects, and has lower junction capacitance. The channel is lightly doped, and the threshold voltage can be adjusted by setting the work function of the metal gate, which can obtain about 2 times the driving current and reduce the requirements for the effective gate oxide thickness (EOT). Compared with the double-gate device, the gate of the triple-gate device surrounds the top surface and two sides of the channel region, and the control ability of the gate is stronger. Furthermore, the full-surround nanowire multi-gate device has more advantages.

However, because the lattice constant of Ge is still different from that of Si, it is difficult to completely use Ge material to form the fin structure when forming small-scale devices, especially Fin Field Effect Transistors (FinFETs), so it is difficult to effectively further enhance the channel of FinFETs. carrier mobility in the channel region. Moreover, the defects existing at the interface between Ge and Si due to lattice mismatch will lead to the problem of reduced reliability of small-sized devices based on Ge epitaxially on Si.

Contents of the invention

Therefore, the object of the present invention is to further increase the mobility of carriers in the channel region of the FinFET to improve the electrical performance and reliability of the semiconductor device.

The present invention provides a semiconductor device, comprising: a fin structure extending and distributed on a substrate along a first direction, wherein the material of the fin structure is different from that of the substrate; The top of the fin structure extends and distributes along the first direction; the gate stack extends and distributes above the channel region along the second direction; the gate sidewalls are on both sides of the gate stack along the first direction.

Wherein, the fin structure has a downward protrusion protruding into the surface of the substrate.

Wherein, the material of the fin structure includes Ge, GaAs, GaN, InGaN, InGaAs, InP, AlGaN and combinations thereof.

Wherein, the tops of the source region and the drain region have a raised source region and a raised drain region, and have a material different from that of the fin structure to apply stress to the channel region.

Wherein, the materials of the raised source region and the raised drain region include SiGe, GeSn, SiC, SiGeC, SiGeSn, SiSn and combinations thereof.

Wherein, the middle part of the fin structure further includes a punch-through stop layer, and the punch-through stop layer is a doped region with a conductivity type opposite to that of the channel region, or an insulator.

Wherein, the gate stack includes a gate insulating layer of high-K material and a gate conductive layer of metal material.

The invention also discloses a semiconductor device manufacturing method, comprising: forming first fin structures extending along the first direction on the substrate and shallow trench isolation between the first fin structures; etching and removing the first fin structures; A fin structure, leaving a first trench between shallow trench isolations; epitaxially growing a semiconductor material different from the substrate in the first trench to form a second fin structure; forming on the second fin structure The gate stack extending along the second direction, and the source and drain regions located on both sides of the gate stack along the first direction, and the part of the second fin structure below the gate stack structure constitutes a channel region.

Wherein, forming the first trench by etching further includes etching the substrate at the bottom of the first trench to form a recess.

Wherein, the substrate is etched by wet etching to form the first trench.

Wherein, before removing the first fin structure by etching, it further includes cleaning the top of the first fin structure.

Wherein, after the epitaxial growth of the second fin structure, further includes, etching back the shallow trench isolation to expose the top of the second fin structure.

Wherein, before forming the gate stack, it further includes forming a punch-through stop layer in the middle of the second fin structure by using vertical and/or oblique ion implantation.

Wherein, implanting a dopant selected from B, In, and BF2 for _nFinFET , or implanting a dopant selected from As and P for pFinFET, forming a doped region opposite to the conductivity type of the channel region to form a punch-through stop layer; or , implanting dopants selected from C, N, O and annealing to form a punch-through stop layer of the insulator.

Wherein, the step of forming the gate stack and the source and drain regions further includes: forming dummy gate stacks and gate spacers extending along the second direction on the second fin structure; Form lightly doped source and drain regions on the top of the second fin structure on the side; epitaxially grow and lift the source and drain regions on top of the lightly doped source and drain regions; remove dummy gate stacks to form gate openings; deposit high-K materials in the gate openings The gate insulating layer and the gate conductive layer of metal material.

Wherein, the material of the second fin structure includes Ge, GaAs, GaN, InGaN, InGaAs, InP, AlGaN and combinations thereof.

Wherein, the materials of the raised source and drain regions include SiGe, GeSn, SiC, SiGeC, SiGeSn, SiSn and combinations thereof.

According to the semiconductor device and its manufacturing method of the present invention, the device fin structure of different materials is epitaxially grown from the fine groove in the substrate, which prevents the upward propagation of interface defects, improves the reliability of the device, and effectively improves the device's trench carrier mobility in the channel region.

Description of drawings

Describe technical scheme of the present invention in detail below with reference to accompanying drawing, wherein:

1 to 17 respectively show the schematic diagrams of each step of the manufacturing method of the semiconductor device according to the present invention.

detailed description

The features and technical effects of the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and in conjunction with schematic embodiments, and a Ge fin that further improves the carrier mobility in the channel region of the FinFET to improve the electrical performance and reliability of the semiconductor device is disclosed. On-chip FinFET and method of manufacturing the same. It should be pointed out that similar reference numerals represent similar structures, and the terms "first", "second", "upper", "lower" and the like used in this application can be used to modify various device structures or process steps . These modifications do not imply spatial, sequential or hierarchical relationships of the modified device structures or process steps unless otherwise specified.

Referring to the cross-sectional view of FIG. 1 , a mask pattern PR is formed on a substrate 1 . The substrate 1 can be a commonly used semiconductor silicon-based substrate such as bulk Si, Si on insulating layer (SOI), or bulk Ge, Ge on insulator (GeOI), or a compound semiconductor substrate such as SiGe, GaAs, GaN, or the like. It can be an insulating substrate such as sapphire, SiC, AlN, etc. The choice of the substrate is set according to the electrical performance requirements of the specific semiconductor device to be fabricated on it. In the present invention, the semiconductor device mentioned in the embodiment is, for example, a FinFET based on a CMOS process. Therefore, from the perspective of compatibility with other processes and cost control, bulk silicon or SOI is preferably used as the material of the substrate 1 . Using processes such as spin coating, spray coating, screen printing, CVD, etc., a mask material is formed on the top surface of the substrate 1, and a conventional exposure/etching process is used to form parallel lines extending along the first direction (perpendicular to the paper surface). A plurality of mask patterns PR. The mask pattern PR can be a soft mask of photoresist, or a hard mask of nitride, oxide or a stacked structure thereof (such as an ONO structure).

2, using the mask pattern PR as a mask, the substrate 1 is etched to form a plurality of fin structures 1F vertically upward from the top surface of the substrate 1 and parallel to the first direction. A groove 1T is left between the fin structures 1F. The etching process preferably adopts anisotropic etching method, such as adopting fluorine-based plasma dry etching, RIE, or adopting TMAH, KOH wet etching. Preferably, the etching parameters are controlled such that the aspect ratio of the fin 1F or the groove 1T is greater than 5:1 and preferably greater than 10:1.

Referring to the cross-sectional view of FIG. 3 , insulating material is filled in the groove 1T between the fin structures 1F to form an isolation structure. Preferably, the mask pattern PR is firstly removed by using a dry process such as plasma etching, ashing, or a wet process using a mixture of an oxidizing agent and an acid solution. Next, a high aspect ratio deposition process (HARP), a high density plasma chemical vapor deposition process (HDPCVD), or a flowable chemical vapor deposition process (flowableCVD) is used to fill the grooves 1T between the multiple fin structures 1F to form insulating material2. The insulating material 2 is such as silicon oxide, silicon oxynitride, or a low-k material, wherein the low-k material includes but not limited to an organic low-k material (such as an organic polymer containing an aryl group or a polycyclic ring), an inorganic low-k material (such as an amorphous Carbon nitrogen thin film, polycrystalline boron nitrogen thin film, fluorosilicate glass, BSG, PSG, BPSG), porous low-k material (such as disilatrioxane (SSQ) based porous low-k material, porous silicon dioxide, porous SiOCH, doped C silica, F-doped porous amorphous carbon, porous diamond, porous organic polymer). At this time, since the fin structure 1F has a protrusion relative to the substrate 1 , the top of the formed insulating material 2 also has a corresponding protrusion at a corresponding position on the top of the fin structure 1F.

Referring to the cross-sectional view of FIG. 4 , a planarization process is performed on the insulating material 2 until the top of the fin structure 1F is exposed. The planarization process may be CMP, or an etch-back process (etch-back) performed for the etch selectivity of the insulating material 2 and the fin structure 1F. The insulating material 2 remaining between the fin structures 1F and occupying the position of the original groove 1T constitutes an isolation structure of the device, also called shallow trench isolation (STI).

Referring to the cross-sectional view of FIG. 5 , the fin structure 1F is selectively etched away. An anisotropic etching process, such as fluorine-based plasma dry etching or RIE, or a wet etching process is preferably used. In a preferred embodiment of the present invention, dilute trimethylammonium hydroxide (dTMAH) alkaline etching solution is used for the fin structure 1F made of Si to form trenches 1T' with good vertical sidewalls. Since the corrosion rate of each crystal direction of the Si substrate is different for TAMH, for example, the (111) crystal plane is the slowest, so finally an inclined groove 1R along the (111) crystal plane will be formed in the substrate 1, and the depth of the groove is For example, only 1 to 5 nm. Preferably, before dTMAH corrodes the Si fin 1F, the top surface of the fin structure 1F is cleaned (eg, 30 seconds) with dilute hydrofluoric acid (dHF) at a volume ratio of 100:1 to remove native oxides on the surface and Improve subsequent etch selectivity and rate.

Referring to the cross-sectional view of Fig. 6, the device material layer 3 is selectively epitaxially grown in the trench 1T'. Using MOCVD, MBE, ALD, HDPCVD and other processes, the device material layer 3 is epitaxially grown in the trench 1T' between the STIs and the groove 1R at the bottom of the trench. The material is such as Ge, but it can also be in Table 1. GaAs, or other compound semiconductor materials not listed in Table 1, such as GaN, InGaN, InGaAs, InP, AlGaN, etc. Since the STI material is an insulating oxide, the epitaxial growth only starts from the groove 1R until a protrusion is formed beyond the top of the STI. This process is also called selective epitaxial growth. It is worth noting that in this process, since the epitaxial growth starts from the groove 1R with inclined sides, the thin device material that is piled up and grown at the bottom first constitutes the nucleation layer of the thick device material layer that continues to be filled above, and the device material and Defects such as dislocation and lattice mismatch at the Si interface will be confined near the original groove 1R, or will not exceed 1/3 of the STI height/trench 1T' depth, ensuring good growth quality of the top device material layer.

Referring to the cross-sectional view of FIG. 7 , the device material layer (eg, Ge layer) is planarized to expose the top of the STI. For example, CMP or an etch-back process is used to remove the device material layer 3 beyond the top of the STI, so that the remaining device material constitutes the fin structure 3F of the device. The upper part of the fin structure 3F shown in FIG. 7 is substantially conformal to the fin structure 1F shown in FIG. In fact, it can be called a dummy fin structure (dummy fin) or a sacrificial fin structure by adopting a naming rule similar to that of the gate-last process, and the final fin structure 3F composed of a device material different from that of the substrate 1 can be called the final fin structure. The sheet structure or true fin structure is used to form the channel region of future devices and define the position of the source and drain regions. The fin structure 3F has a portion protruding into the substrate 1 having the same shape as the groove 1R. As mentioned above, the defect propagation of the device material layer (eg, Ge layer) is eliminated through this portion, thereby improving device reliability.

Referring to the cross-sectional view of FIG. 8 , a part of the STI is etched away, exposing the fin structure 3F. For the STI material, an anisotropic dry etching process can be selected, or a part of the STI can be removed by wet etching of dHF or dBOE (diluted slow-release etchant). The height of the exposed fin structure 3F may depend on the topographical requirements surrounding the gate in the FinFET device. In a preferred embodiment of the present invention, the height of the exposed fin structure 3F is less than or equal to 1/2 of the height of the fin 3F.

Referring to the cross-sectional view of FIG. 9 , optionally, a punch through stop layer (PTS) 4 is formed in the middle of the fin structure 3F. Preferably, vertical and/or oblique ion implantation can be used to implant dopant ions into the middle of the fin structure 3F, followed by annealing to activate the impurities to form a through hole different from the usual intrinsic fin structure 3F material, doping type, and concentration The stop layer 4 is used to suppress and reduce the leakage current of the FinFET along the direction perpendicular to the substrate. In a preferred embodiment of the present invention, dopants such as B, In, and BF2 can be implanted into _nFinFET , and As, P, etc. dopants can be implanted into pFinFET, thereby forming a pn junction with the upper and lower materials of the fin structure 3F so that Leakage is suppressed by a reverse biased diode. In addition, in another preferred embodiment of the present invention, C, N, O and other dopant ions that are likely to chemically react with the material of the fin structure 3F can also be implanted. The dopant ions react with the material of the fin structure 3F to form PTS4 of an insulator (such as oxide, silicon nitride, carbide, etc.), thereby blocking the leakage path with the substrate through the insulator 4 . The implant dose, energy, angle and annealing temperature can be adjusted to reasonably control the position of PTS4. In a preferred embodiment of the present invention, the top surface of the PTS4 is flush with the top surface of the STI, and the area of the fin structure 3F above the PTS4 will be used to form the channel region of the device, so it is marked as 3C. In another preferred embodiment of the present invention, the bottom surface of the PTS 4 is higher than the top surface of the substrate 1 .

Referring to the cross-sectional view of FIG. 10 , a dummy gate stack layer 5 is deposited and formed on the device. Using PECVD, HDPCVD, MBE, ALD, evaporation, oxidation, sputtering and other processes, a dummy gate insulating layer 5A and a dummy gate conductive layer 5B are deposited on the entire device. The material of layer 5A is such as silicon oxide, and the material of layer 5B is such as polycrystalline silicon, amorphous silicon, microcrystalline silicon, polycrystalline germanium, amorphous germanium, amorphous carbon, etc. The materials of the two are selected to improve the etching selectivity with other surrounding materials . The stacked layer 5 completely covers the top and sidewalls of the top (3C) of the fin structure 3F, and covers the top of the STI.

Referring to the top view of FIG. 11, the dummy gate stack layer 5 is patterned to form a dummy gate stack structure extending along the second direction BB (horizontal left-right direction in FIG. 10 and FIG. 11), exposing the dummy gate stack structure along the first direction AA. (vertical direction in FIG. 10 , vertical direction in FIG. 11 ) the top 3C of the fin structure 3F on both sides.

Referring to the top view of FIG. 12 , gate spacers 6 are formed on both sides of the dummy gate stack structure 5A/ 5B along the first direction AA. For example, PECVD, sputtering and other processes are used to form insulating dielectric materials such as silicon nitride, silicon oxynitride, diamond-like amorphous carbon (DLC), and then anisotropic etching process is used to remove the horizontal part and only stack the dummy gate. The gate spacers 6 remain on both sides of the structure 5 .

Referring to the top view of FIG. 13 , lightly doped source and drain regions 3L (including source region 3LS and drain region 3LD of LDD structure) are formed in the top 3C of the fin structure 3F and on both sides of the dummy gate stack structure 5 . Dopants such as B, In, and BF2 are implanted for _pFinFET , and dopants such as As and P are implanted for nFinFET (to form a lightly doped source and drain region opposite to the doping type of the PTS4 doped region). Then, the implanted dopant is activated by processes such as spike annealing and rapid annealing.

Referring to the top view of FIG. 14, source and drain regions are formed. Preferably, the top of the lightly doped source and drain region 3LS/3LD is etched and cleaned by using a solution such as dHF to remove native oxides during implantation and annealing. In one embodiment of the present invention, heavily doped source and drain regions 3HS/3HD are formed on both sides of the dummy gate stack structure 5 along the first direction by increasing the dopant dose, implantation energy, etc., and the type of implanted ions is related to the LDD Same structure, just higher concentration. Preferably, in another embodiment of the present invention, the raised source and drain regions of different materials are epitaxially grown on the lightly doped source and drain regions by using selective epitaxial growth technology, and at the same time, high concentration is formed by using in-situ doping technology. Raise the source and drain regions by controlling the material type, for example, SiGe, SiGeC, SiC, etc. are used for NMOS of Ge channel; GeSn is used for PMOS of Ge channel (when the fin structure/channel region is made of other materials than Ge, it can be By using other materials such as GeSn, SiGeSn, SiSn, etc.), different stresses can be applied to the fin channel region 3C under the dummy gate stack structure 5, thereby effectively increasing the carrier mobility in the channel region.

Referring to FIG. 15A , it shows a cross-sectional view taken along line AA of the first direction in FIG. 14 . FIG. 15B is a cross-sectional view taken along the line BB in the second direction of FIG. 14 , which is consistent with the directions in FIGS. 1 to 9 . It can be seen from FIG. 15B that the epitaxially grown stress-included raised source and drain regions 3HS/3HD surround the side and top of the lightly doped source and drain regions 3LS/3LD of the LDD structure, such as rhombus or diamond shape in the drawing.

Referring to the cross-sectional view of FIG. 16 along the second direction BB, an interlayer dielectric layer (ILD) 7 is formed on the entire device. For example, ILD7 using spin coating, spray coating, screen printing, CVD and other processes to form low-k materials, including but not limited to organic low-k materials (such as organic polymers containing aryl or polycyclic rings), inorganic low-k materials (such as Shaped carbon-nitrogen films, polycrystalline boron-nitride films, fluorosilicate glass, BSG, PSG, BPSG), porous low-k materials (such as disilatrioxane (SSQ)-based porous low-k materials, porous silica, porous SiOCH, C-doped silica, F-doped porous amorphous carbon, porous diamond, porous organic polymer). Preferably, a CMP process is used to planarize the ILD 7 until the top of the dummy gate conductive layer 5B is exposed.

Referring to the cross-sectional view of FIG. 17 along the second direction BB, the gate-last process continues. For example, selective etching removes the dummy gate conductive layer 5B and the dummy gate insulating layer 5A, leaving a gate opening in the ILD 7 . A gate insulating layer 8A of high-k material and a gate conductive layer 8B of metal material are sequentially deposited in the gate opening by using processes such as HDPCVD, MOCVD, MBE, and ALD. Among them, high-k materials include but are not limited to nitrides (such as SiN, AlN, TiN), metal oxides (mainly subgroup and lanthanide metal element oxides, such as MgO, Al ₂ O ₃ , Ta ₂ O ₅ , TiO ₂ , ZnO, ZrO ₂ , HfO ₂ , CeO ₂ , Y ₂ O ₃ , La ₂ O ₃ ), nitrogen oxides (such as HfSiON); perovskite phase oxides (such as PbZr _x Ti _1-x O ₃ (PZT ), Ba _x Sr _1-x TiO ₃ (BST)). The gate conductive layer 8B can be polysilicon, polysilicon germanium, or metal, wherein the metal can include Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La and other metal elements, or alloys of these metals and nitrides of these metals, the gate conductive layer 8B can also be doped with C, F, N, O, B, P, As, etc. element to adjust the work function. Between the gate conductive layer 8B and the gate insulating layer 8A, a nitride barrier layer (not shown) is preferably formed by conventional methods such as PVD, CVD, ALD, etc., and the material of the barrier layer is M _x N _y , M _x Si _y N _z , M _{x Aly N z , Ma Al x Si y N z , wherein M} is Ta, Ti, Hf, Zr, Mo, W or other elements. More preferably, the gate conductive layer 8B and the barrier layer not only adopt a composite layer structure stacked up and down, but also adopt a mixed implanted doped layer structure, that is, the materials constituting the gate conductive layer 8B and the barrier layer are deposited on the gate at the same time. Therefore, the gate conductive layer includes the material of the above-mentioned barrier layer. After that, ILD7 is further etched to form contact holes exposing the raised source and drain regions 3HD/3HS, and W, Al, Cu, Ti, Ta, Mo and other metals, metal alloys, metal nitrides, etc. are filled in the contact holes to form contact plugs 9B. And it is further preferable to form a nickel-based metal silicide 9A in the contact hole before this to reduce the contact resistance.

Finally, the novel FinFET of the present invention as shown in FIG. 17 is formed, which includes: a plurality of fin structures 3F extending above the substrate 1 along the first direction, wherein the fin structures 3F have protrusions protruding into the surface of the substrate 1 Protruding downwards, the material of the fin 3F is different from that of the substrate 1; the middle part of the fin structure 3F has a punch-through stop layer 4, which has a dopant and is different from the conductivity type of other parts of the fin structure 3F to form a reverse biased PN junction The doped region, or an insulator made of insulating material; the top of the fin structure 3F includes a lightly doped source region 3LS extending along the first direction, a channel region 3C, and a lightly doped drain region 3LD; above the channel region 3C there is A gate stack 8 of a gate insulating layer 8A of high-k material and a gate conductive layer 8B of a metal material; there are gate spacers on both sides of the gate stack 8; lightly doped source and drain regions 3LD/3LS have different material The raised source and drain regions 3HS/3HD that can provide stress to the channel region 3C; the raised source and drain regions have metal silicide 9A and contact plugs 9B buried in the interlayer dielectric layer 7 . The specific materials and processes of each component are as described above, and will not be repeated here.

According to the semiconductor device and its manufacturing method of the present invention, the device fin structure of different materials is epitaxially grown from the fine groove in the substrate, which prevents the upward propagation of interface defects, improves the reliability of the device, and effectively improves the device's trench carrier mobility in the channel region.

While the invention has been described with reference to one or more exemplary embodiments, it will be apparent to those skilled in the art that various suitable changes and equivalents can be made to the process flowsheets without departing from the scope of the invention. In addition, many modifications, possibly suited to a particular situation or material, may be made from the disclosed teaching without departing from the scope of the invention. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode for carrying out this invention, but that the disclosed device structures and methods of making the same will include all embodiments falling within the scope of the invention .

Claims (17)

1. A semiconductor device, comprising: The fin structure is extended and distributed on the substrate along the first direction, wherein the material of the fin structure is different from that of the substrate; The source region, the channel region, and the drain region extend and distribute along the first direction on the top of the fin structure; a gate stack extending and distributed along the second direction above the channel region; The gate spacers are on both sides of the gate stack along the first direction. 2. The semiconductor device of claim 1, wherein the fin structure has a downward protrusion protruding into the surface of the substrate. 3. The semiconductor device according to claim 1, wherein the material of the fin structure comprises Ge, GaAs, GaN, InGaAs, InP, InGaN, AlGaN and combinations thereof. 4. The semiconductor device as claimed in claim 1, wherein the tops of the source region and the drain region have raised source region and raised drain region, and have a material different from that of the fin structure to apply stress to the channel region. 5. The semiconductor device according to claim 4, wherein the material of the raised source region and the raised drain region comprises SiGe, GeSn, SiC, SiGeC, SiGeSn, SiSn and combinations thereof. 6 . The semiconductor device according to claim 1 , wherein the middle part of the fin structure further comprises a punch-through stop layer, and the punch-through stop layer is a doped region having a conductivity type opposite to that of the channel region, or an insulator. 7. The semiconductor device of claim 1, wherein the gate stack comprises a gate insulating layer of a high-K material and a gate conductive layer of a metal material. 8. A method of manufacturing a semiconductor device, comprising: forming first fin structures extending along a first direction and shallow trench isolation between the first fin structures on the substrate; Etching and removing the first fin structure, leaving a first trench between shallow trench isolations; Epitaxially growing a semiconductor material different from the substrate in the first trench to form a second fin structure; A gate stack extending along the second direction and source and drain regions located on both sides of the gate stack along the first direction are formed on the second fin structure, and the part of the second fin structure below the gate stack structure forms a trench. road area. 9 . The method according to claim 8 , wherein the etching to form the first trench further comprises etching the substrate at the bottom of the first trench to form a recess. 10. The method of claim 8, wherein the first trench is formed by etching the substrate using wet etching. 11. The method of claim 8, wherein before etching the first fin structure away, it further comprises cleaning the top of the first fin structure. 12. The method of claim 8, wherein after epitaxially growing the second fin structure, further comprising, etching back the shallow trench isolation to expose a top of the second fin structure. 13. The method of claim 8, further comprising, before forming the gate stack, forming a punch-through stop layer in the middle of the second fin structure by using vertical and/or oblique ion implantation. 14. The method as claimed in claim 13, wherein, implanting a dopant selected from B, In, and BF for the _nFinFET , or implanting a dopant selected from As and P for the pFinFET, forming a channel region opposite to the conductivity type of the channel region. The doped region constitutes a punch-through stop layer; alternatively, a dopant selected from C, N, and O is implanted and annealed to form a punch-through stop layer of an insulator. 15. The method according to claim 8, wherein the step of forming the gate stack and the source and drain regions further comprises: forming dummy gate stacks and gate spacers extending along the second direction on the second fin structure; Lightly doped source and drain regions are formed on the top of the second fin structure on both sides of the gate spacer along the first direction; epitaxially growing and lifting the source and drain regions on top of the lightly doped source and drain regions; dummy gate stacks are removed to form gate openings; A gate insulating layer of high-K material and a gate conductive layer of metal material are deposited in the gate opening. 16. The method of claim 8, wherein the material of the second fin structure comprises Ge, GaAs, GaN, InGaAs, InP, InGaN, AlGaN and combinations thereof. 17. The method of claim 15, wherein the material of the raised source and drain regions comprises SiGe, GeSn, SiC, SiGeC, SiGeSn, SiSn and combinations thereof.