CN102956466A - Fin-shaped transistor and manufacturing method thereof - Google Patents

Abstract

The invention provides a fin-shaped transistor and a manufacturing method thereof. The manufacturing method comprises the steps of firstly providing a substrate and forming a mask layer on the substrate. Then, a first trench is formed in the mask layer and the substrate, and a semiconductor layer is formed in the first trench. The mask layer is then removed, so that the semiconductor layer forms a fin structure embedded in the substrate and protruding out of the substrate. Finally, a gate is formed on the fin structure.

Description

Fin transistor and method for making same

technical field

The present invention relates to a fin transistor and its fabrication method, in particular to a fin transistor with an embedded fin structure and its fabrication method.

Background technique

In recent years, with the continuous miniaturization of various consumer electronic products, the design size of semiconductor components has also been continuously reduced to meet the trend and product requirements of high integration, high efficiency and low power consumption.

However, with the development of miniaturization of electronic products, existing planar transistors can no longer meet the requirements of the products. Therefore, a non-planar fin transistor (Fin-FET) technology has been developed, which has a three-dimensional gate channel (channel) structure, which can effectively reduce the leakage of the substrate and reduce the short channel. effect, and has a higher drive current. However, since the fin transistor is a three-dimensional structure, it is more complicated than the traditional structure, and the manufacturing difficulty is relatively high. Generally, it is usually formed on a silicon-on-insulator (SOI) substrate. If it is to be compatible with the existing silicon The substrate process is somewhat difficult.

Therefore, there is also a need for a novel fabrication method of a fin transistor device.

Contents of the invention

The present invention thus proposes a fin transistor structure and a manufacturing method thereof, which can be applied to common silicon substrates and have good product quality.

According to an embodiment, the present invention provides a method for manufacturing a fin transistor. Firstly, a base is provided, and a mask layer is formed on the base. Then a first trench is formed in the mask layer and the substrate, and a semiconductor layer is formed in the first trench. Then the mask layer is removed, so that the semiconductor layer forms a fin structure embedded in the substrate and protrudes above the substrate. Finally, a gate is formed on the fin structure.

According to another embodiment, the present invention provides a structure of a fin transistor, including a substrate, a fin structure, a gate dielectric layer, and a gate layer. The fin-like structure is embedded in the base and protrudes above the base. The gate dielectric layer covers the surface of the fin structure, and the gate covers the gate dielectric layer.

The invention uses a selective epitaxial growth process to form the fin structure, and cooperates with the tapered side wall and the cyclic annealing process to ensure the quality of the fin structure and improve the yield rate of the product. On the other hand, compared with the conventional fin transistors that are mostly formed on silicon insulating substrates, the method provided by the present invention can be operated on general silicon substrates, which further increases the flexibility of the process.

Description of drawings

1 to 11 are schematic diagrams illustrating the manufacturing method of the fin transistor of the present invention.

FIG. 12 is a schematic diagram of the structure of the fin transistor of the present invention.

Explanation of reference signs

300 Base 314 Bottom anti-reflection layer

302 Substance layer 316 Patterned photoresist layer

304 mask layer 318 second trench

306 bottom anti-reflection layer 320 insulation layer

308 patterned photoresist layer 321 shallow trench isolation

310 first trench 322 gate dielectric layer

312 semiconductor layer 324 gate layer

313 fin structure 326 fin transistor

313a source region 328 active region

313b drain region

Detailed ways

In order for those skilled in the art to have a better understanding of the present invention, several preferred embodiments of the present invention are enumerated below, together with the accompanying drawings, to describe in detail the composition and desired effects of the present invention.

First, please refer to FIG. 12 , which is a schematic structural diagram of the fin transistor of the present invention. As shown in FIG. 12 , the fin transistor 326 of the present invention is disposed in the active region surrounded by the shallow trench isolation 321 . The fin transistor 326 includes a substrate 300 , at least one fin structure 313 , a material layer 302 , a gate dielectric layer 322 and a gate layer 324 . The substrate 300 is, for example, a silicon substrate (bulk silicon) or a germanium (Ge) substrate, and may also be a silicon-on-insulator (SOI) substrate. The substance layer 302 is disposed on the substrate 300, and in a preferred embodiment of the present invention, the substance layer 302 includes silicon dioxide (SiO ₂ ).

The fin structures 313 are embedded in the substrate 300 and protrude above the substrate 300 through the material layer 302 , and each fin structure 313 generally extends along the y direction and is parallel to the x direction. As shown in FIG. 12 , each fin structure 313 has a width W, a height H1 protruding from the material layer 302 in the z direction, a thickness H2 in the material layer 302 , and a depth H3 in the substrate 300 . In a preferred embodiment of the present invention, W is generally between 100 angstroms and 200 angstroms, and H1 can be about 0.5 times W, or 0.5 times to twice W, or more than twice W, depending on product design , H2 is generally greater than or equal to W, and H3 is generally between 100 angstroms and 500 angstroms. In addition, the fin structure 313 of the present invention has a tapered structure toward the base 300 . Preferably, the angle θ of the taper is less than 30 degrees. The fin structure 313 is, for example, a silicon layer, a germanium layer (Ge), a silicon germanium layer (SiGe), or a combination thereof. The fin structure 313 may further include a source region 313 a and a drain region 313 b separated by a gate layer 324 and include dopants of appropriate electrical properties and doping concentrations.

The gate layer 324 is disposed on the gate dielectric layer 322 and extends along the x direction to cover at least one fin structure 313 . The gate layer 324 may include various conductive materials, such as polysilicon or metal. The gate dielectric layer 322 is disposed between the fin structure 313 and the gate layer 324, and covers the surface of the fin structure 313. In detail, the gate dielectric layer 322 is disposed on the portion protruding above the material layer 302 The sidewall and/or the top surface of the fin structure 313 (ie, the region with the height H1). The gate dielectric layer 322 can be, for example, silicon dioxide or a high-k dielectric layer. The high dielectric constant dielectric layer can be selected from, for example, hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), hafnium silicon oxynitride (HfSiON), aluminum oxide (aluminum oxide, Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), zirconia oxide, ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ), strontium bismuth tantalum oxide (strontium bismuth tantalate, SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (lead zirconate titanate, PbZr _x Ti _1-x O ₃ , PZT) and barium strontium titanate (Ba _x Sr _1-x TiO ₃ , BST) group.

It can be understood that the aforementioned x-direction, y-direction and z-direction are only references for relative positions. If the substrate 300 is rotated 90 degrees counterclockwise or clockwise, for example, the fin structures 313 extend along the x-direction and are parallel to each other. y direction, while the gate layer 324 extends along the y direction, and its arrangement is still the equivalent change and modification of the present invention, which should fall within the scope of the present invention.

In order to increase the electrical performance of the fin transistor 326, the present invention also provides the following implementation examples. In an embodiment of the present invention, the fin transistor 326 may further include a silicon stress layer (not shown) disposed between the fin structure 313 and the gate dielectric layer 322 , such as disposed on the sidewall of the fin structure 313 or top surface. In another embodiment, if the fin structure 313 includes a relaxed SiGe layer (relaxed SiGe), a second SiGe layer (not shown) may be disposed between the fin structure 313 and the gate dielectric layer 322, And the content of germanium in the second silicon germanium layer is greater than the content of germanium in the fin structure 313 .

Please refer to FIG. 1 to FIG. 11 , which are schematic diagrams of the manufacturing method of the fin transistor of the present invention, which are drawn along the tangent line AA' in FIG. 12 . As shown in FIG. 1 , a substrate 300 such as a silicon substrate is provided first. Next, a substance layer 302 and a mask layer 304 are sequentially formed on the substrate 300 . In a preferred embodiment of the present invention, the material of the substance layer 302 includes silicon dioxide (SiO ₂ ), and the material of the mask layer 304 includes silicon nitride (SiN).

As shown in FIG. 2 , a patterned photoresist layer 308 is formed on the mask layer 304 to define the position of each fin structure 313 . In a preferred embodiment, a single-layer or multi-layer bottom antireflection layer (bottom antireflection coating, BARC) 306 can be selectively formed between the patterned photoresist layer 308 and the mask layer 304; In one embodiment, the bottom anti-reflection layer 306 may not be formed.

As shown in FIG. 3 , at least one etching process is performed using the patterned photoresist layer 308 as a mask. The etching process removes the mask layer 304 and the substance layer 302 not covered by the patterned photoresist layer 308 , and further etches the substrate 300 to form a plurality of first trenches 310 . In a preferred embodiment of the present invention, the first trench 310 has tapered sidewalls, and the tapered angle is less than 30 degrees. Next, the patterned photoresist layer 308 and the antireflection layer 306 are removed.

As shown in FIG. 4 , a selective epitaxial growth process (selective epitaxial growth) is performed using the substrate 300 as a seed layer to form a semiconductor layer (semiconductor layer) 312 in each first trench 310 . The semiconductor layer 312 grows from the bottom of the first trench 310 and grows upward beyond the top surface of the mask layer 304 . In an embodiment of the present invention, the semiconductor layer 312 includes, for example, a silicon layer (Si), a germanium layer (Ge), a silicon germanium layer (SiGe), or a combination thereof. The semiconductor layer 312 may also have a one-layer or multi-layer structure with appropriate stress. Generally speaking, if the substrate 300 is a silicon substrate, when a germanium layer or a silicon germanium layer is selectively epitaxially grown, lattice defects such as dislocations usually occur at a position 30 degrees relative to the silicon (001) plane. Taking FIG. 12 as an example, the silicon (001) plane is parallel to the surface (x-axis direction) of the silicon substrate 300, and the tapering angle is the angle θ between the tapering sidewall and the z-axis. During the selective epitaxial growth process, since the first trench 310 has tapered sidewalls, and the tapered angle θ is less than 30 degrees, lattice defects such as dislocations in the semiconductor layer 312 will be along the The tapered sidewalls of the first trench 310 gradually move upward. When dislocations move upward to the material layer 302 of silicon dioxide, the dislocations will be absorbed by the material layer 302 due to aspect ratio trapping (ART) phenomenon. Therefore, the semiconductor layer 312 of the present invention can avoid generation of dislocations, and has preferable quality. It is worth noting that although the locations where lattice defects are prone to occur will change with the epitaxial materials of the substrate 300 and the semiconductor layer 312, since the epitaxial materials of the substrate 300 and the semiconductor layer 312 are mostly diamond-like structures, Lattice defects such as dislocations usually occur at a position of 30 degrees relative to the silicon (001) plane, so the present invention uses tapered sidewalls with less than 30 degrees to overcome most of the lattice defects.

In another embodiment of the present invention, after the selective epitaxial growth is completed, a cyclic thermal annealing (CTA) process can also be performed, including first performing a high-temperature annealing step, and then performing a low-temperature annealing step, and continuing for several cycles . In an embodiment of the present invention, the high temperature annealing is carried out at 850°C to 950°C for 5 minutes, preferably 900°C, and the low temperature annealing is carried out at 350°C to 450°C for 5 minutes, preferably at 400°C, and repeated cycles The number of times is, for example, three times. Since the thermal expansion coefficient (thermal expansion coefficient) between the semiconductor layer 312 and the substrate 300 is different, performing a cyclic annealing process can promote dislocations in the semiconductor layer 312 to move toward the material layer 302, thereby reducing the crystal lattice of dislocations and the like. The occurrence of defects.

As shown in FIG. 5 , a planarization step, such as a chemical mechanical polish (CMP) process, is performed to remove the semiconductor layer 312 on the top surface of the mask layer 304, so that the semiconductor layer 312 and the mask layer 304 are aligned. high. In this step, the semiconductor layer 312 then forms a plurality of fin structures 313 . Each fin structure 313 is substantially parallel to each other, and is disposed in each first trench 310 , protrudes above the substrate 300 and is flush with the mask layer 304 .

As shown in FIG. 6 , a selective bottom antireflection layer 314 and a patterned photoresist layer 316 are formed on the mask layer 304 to define an active region 328 and shallow trench isolations surrounding the active region 328 , wherein the fin structure 313 will be located in the active region 328 . Next, as shown in FIG. 7, an etching process is performed using the patterned photoresist layer 316 as a mask to remove the mask layer 304 and the substance layer 302 not covered by the patterned photoresist layer 316, And further etch to the substrate 300 to form a plurality of second trenches 318 in the substrate 300 . The depth of the second trench 318 is greater than the depth of the first trench 310. In one embodiment, the depth of the second trench 318 is generally between 2000 angstroms and 3000 angstroms. Then, the patterned photoresist layer 316 and the antireflection layer 314 are removed.

As shown in FIG. 8 , an insulating layer 320 is fully formed on the substrate 300 such that it at least fills up each second trench 318 . The method of forming the insulating layer 320 is, for example, a deposition process, including plasma-enhanced chemical vapor deposition (plasma-Enhanced CVD, PECVD) and the like. The insulating layer 320 is, for example, a silicon dioxide layer. Next, as shown in FIG. 9 , a planarization process is performed to remove the insulating layer 320 above the mask layer 304 . Then, an etch-back process is performed to remove part of the insulating layer 320 in the second trench 318 , so that the height of the insulating layer 320 is slightly higher than that of the substance layer 302 , thereby forming a plurality of shallow trench isolations 321 . It should be noted that, in FIGS. 1 to 4 in the foregoing embodiments, after the fin structure 313 is formed, the shallow trench isolation 321 is formed in FIGS. 5 to 8 . In another embodiment of the present invention, the shallow trench isolation 321 may also be formed first, and then the fin structure 313 is formed.

As shown in FIG. 10 , an etching process is performed to remove the mask layer 304 . In the embodiment of the present invention, when the mask layer 304 is silicon nitride, it can be removed by hot phosphoric acid. In an embodiment of the present invention, a silicon stress layer (not shown) may also be formed on the sidewall or top surface of the fin structure 313 . In another embodiment, if the fin structure 313 includes a relaxed SiGe layer (relaxed SiGe), a second SiGe layer (not shown) may also be formed on the fin structure 313, and the second SiGe layer The germanium content is greater than the germanium content in the fin structure 313 .

Finally, as shown in FIG. 11 , a gate dielectric layer 322 is formed on the substrate 300 to cover each fin structure 313 . The gate dielectric layer 322 can be, for example, silicon dioxide or a high-k dielectric layer. Then, a gate layer 324 is formed on the gate dielectric layer 322 , and the gate layer 324 may include various conductive materials, such as polysilicon or metal. Subsequently, after patterning the gate layer 324 to form the desired gate structure, an ion implantation process is performed to form the source region 313 a and the drain region 313 b in the fin structure 313 as shown in FIG. 12 . Through the above steps, the structure shown in Figure 12 can be formed. In an embodiment of the present invention, an inter-layer dielectric layer (inter-layer dielectric, ILD) (not shown) may also be formed on the fin transistor 326, and appropriate contact holes may be formed in the inter-layer dielectric layer (FIG. not shown) as an output/input channel with external circuits.

Those skilled in the art should understand that the foregoing embodiments are "gate-first processes". The present invention can also be used in the "last gate (gate last) process". For example, in another embodiment, the gate layer 324 can be a sacrificial gate (sacrifice gate). After the electrical layer, the sacrificial gate layer 324 can be further removed, and a low-resistance gate (not shown), such as a metal gate, can be formed to complete the gate-last process.

It should be noted that the width W, height H1 , height H2 and height H3 of the fin structure 313 in FIG. 12 can be obtained by controlling different parameters in the aforementioned process. For example, the width W and the height H3 are determined by the first trench 310 formed in FIG. 3 , while the heights H1 and H2 are determined by the thicknesses of the mask layer 304 and the substance layer 302 in FIG. 1 . Since the parameters of the process can be adjusted to determine the ratio of the width W and the height H1, the present invention can form different electrical non-planar transistors (non-planer transistors) depending on the product design, such as FIN-FET (when H1 is greater than or equal to twice W), trigate (when H1 is about 1 times W) or segment-FET (when H1 is about 0.5 times W). In addition, the present invention uses a selective epitaxial growth process to form the fin structure, and cooperates with the tapered sidewall and the cyclic annealing process to ensure the quality of the fin structure and improve the yield of the product. On the other hand, compared with the conventional fin transistors that are mostly formed on silicon insulating substrates, the method provided by the present invention can be operated on general silicon substrates, which further increases the flexibility of the process.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (20)

1. method that forms fin transistor comprises:

Substrate is provided;

In this substrate, form mask layer;

In this mask layer and this substrate, form the first groove;

In this first groove, form semiconductor layer;

Remove this mask layer, so that this semiconductor layer formation fin structure is embedded in this substrate and protrudes from this substrate; And

Forming grid covers on this fin structure.

2. the method for formation fin transistor as claimed in claim 1 also comprises forming shallow trench isolation to define active area.

3. the method for formation fin transistor as claimed in claim 2, wherein form first this shallow trench isolation from, remove again this mask layer.

4. the method for formation fin transistor as claimed in claim 1, the method that wherein forms this semiconductor layer comprises selective epitaxial growth process.

5. the method for formation fin transistor as claimed in claim 1, the method that wherein forms this semiconductor layer comprises cycle annealing technique.

6. the method for formation fin transistor as claimed in claim 1 also is included between this substrate and this mask layer and forms material layer.

7. the method for formation fin transistor as claimed in claim 6, wherein this material layer comprises silicon dioxide.

8. the method for formation fin transistor as claimed in claim 1, wherein this semiconductor layer comprises silicon layer, germanium layer, germanium-silicon layer or above-mentioned combination.

9. method that forms fin transistor comprises:

Substrate is provided;

In this substrate, form mask layer;

In this mask layer and this substrate, form the first groove;

In this first groove, form semiconductor layer;

Form shallow trench isolation to define active area, wherein this semiconductor layer is arranged in this active area;

Form this shallow trench isolation from rear, remove this mask layer, so that this semiconductor layer formation fin structure is embedded in this substrate and protrudes from this substrate;

Form grid on this fin structure.

10. the method for formation fin transistor as claimed in claim 9, the method that wherein forms this semiconductor layer comprises selective epitaxial growth process.

11. the method for formation fin transistor as claimed in claim 9, the method that wherein forms this semiconductor layer comprises cycle annealing technique.

12. the method for formation fin transistor as claimed in claim 9 also is included between this substrate and this mask layer and forms material layer.

13. the method for formation fin transistor as claimed in claim 12, wherein this material layer comprises silicon dioxide.

14. the method for formation fin transistor as claimed in claim 9, wherein this semiconductor layer comprises silicon layer, germanium layer, germanium-silicon layer or above-mentioned combination.

15. a fin transistor comprises:

Substrate;

Fin structure is embedded in this substrate, and this fin structure protrudes from this substrate;

Gate dielectric covers the surface of this fin structure; And

Grid covers on this gate dielectric.

16. fin transistor as claimed in claim 15, wherein this fin structure comprises silicon layer, germanium layer, germanium-silicon layer or above-mentioned combination.

17. fin transistor as claimed in claim 15, wherein this fin structure has the structure towards the substrate convergent.

18. fin transistor as claimed in claim 15 also comprises the silicon stressor layers, this stressor layers is arranged between this fin structure and this gate dielectric.

19. fin transistor as claimed in claim 15, wherein this fin structure comprises the extension germanium-silicon layer, and this fin transistor comprises that also the second germanium-silicon layer is arranged between this fin structure and this gate dielectric, and in this second germanium-silicon layer the content of germanium greater than the content of germanium in this fin structure.

20. fin transistor as claimed in claim 15, wherein this fin structure comprises the extension germanium-silicon layer, and this fin transistor comprises that also the silicon stressor layers is arranged at the sidewall of this fin structure.

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