CN102299156A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

In the invention, in the process of preparing a CMOS transistor by a Gate Replacement process (Replacement Gate or Gate last), after high-k Gate dielectric layers are formed in an NMOS device region and a PMOS device region, a first work function adjusting dielectric layer belonging to the NMOS region and a second work function adjusting dielectric layer belonging to the PMOS region are respectively formed so as to respectively adjust the threshold voltages of the NMOS device and the PMOS device.

Description

A kind of semiconductor device and its manufacturing method

technical field

The present invention generally relates to a semiconductor device and a manufacturing method thereof, in particular to a high-k gate dielectric/metal gate device based on a gate replacement process and a manufacturing method thereof.

Background technique

With the development of semiconductor technology, integrated circuits with higher performance and stronger functions require greater component density, and the size, size and space of each component, between components or each component itself also need to be further reduced. The application of 22nm and below process integrated circuit core technology has become an inevitable trend in the development of integrated circuits, and it is also one of the topics that major international semiconductor companies and research organizations are competing to research and develop. CMOS device gate engineering research centered on "high-k gate dielectric/metal gate" technology is the most representative core process in 22nm and below technologies, and related materials, processes and structures have been extensively studied . At present, the research on high-k gate dielectric/metal gate technology can be roughly divided into two directions, namely the front gate process and the gate replacement process. The gate of the front gate process is formed before the generation of the source and drain, and the gate replacement process The gate of the process is formed after the source and drain are formed, and the gate does not need to withstand a high annealing temperature in this process.

In the traditional gate replacement process, the typical process includes forming a dummy gate of polysilicon or silicon nitride, and after the source/drain is formed, the dummy gate is etched away to form a gate trench, and then sequentially in the gate trench Deposit high-k gate dielectric and dual-metal gate electrode materials. For dual-metal gate electrode materials, metals with different work functions need to be formed in the gate trench regions of nMOS and pMOS devices to adjust the threshold voltage of the device. However, due to the metal etching process The complexity on the surface brings difficulty to the integration of CMOS integration process.

Therefore, it is necessary to propose a semiconductor device based on a gate-last process that can effectively adjust the threshold voltage of the device and whose process integration is relatively simple.

Contents of the invention

In view of the above problems, the present invention provides a semiconductor device comprising: a semiconductor substrate having an NMOS region and a PMOS region; a source region and a drain region respectively belonging to the NMOS region and the PMOS region formed in the semiconductor substrate An electrode region; a first gate stack formed on the NMOS region and a second gate stack formed on the PMOS region; wherein, the first gate stack includes: a first interface layer; formed on the first The first high-k gate dielectric layer on the interface layer; the first work function adjustment dielectric layer formed on the first high-k gate dielectric layer; the first metal gate formed on the first work function adjustment dielectric layer The electrode; the second gate stack includes: a second interface layer; a second high-k gate dielectric layer formed on the second interface layer; a second work function formed on the second high-k gate dielectric layer adjusting medium layer; a second metal gate electrode formed on the second work function adjusting medium layer; wherein the first work function adjusting medium layer and the second work function adjusting medium layer are formed of different materials for respectively adjusting The work function of the NMOS device and the PMOS device.

The present invention also provides a method for manufacturing the above-mentioned semiconductor device, the method comprising: providing a semiconductor substrate having an NMOS region and a PMOS region; forming a first interface layer belonging to the NMOS region, a dummy gate and a Its sidewalls form a second interface layer belonging to the PMOS region, a dummy gate and its sidewalls, and respectively form a source region and a drain region belonging to the NMOS region and the PMOS region in the semiconductor substrate, and cover the The source region and the drain region of the NMOS and PMOS regions form an interlayer dielectric layer; the dummy gates of the NMOS region and the PMOS region are removed to form a first opening and a second opening; the first high-k gate dielectric layer of the first interface layer, and form a second high-k gate dielectric layer covering the second interface layer in the second opening; on the first high-k gate dielectric layer Forming a first work function adjusting medium layer, forming a second work function adjusting medium layer on the second high-k gate dielectric layer; forming a first metal layer filling the first opening on the first work function adjusting medium layer A gate electrode, forming a second metal gate electrode filling the second opening on the second work function adjusting dielectric layer; processing the device to form a first gate stack belonging to the NMOS region and a gate stack belonging to the PMOS region, respectively. The second gate stack in the region, wherein the first and second work function adjusting dielectric layers are formed of different materials, so as to adjust the work function of the NMOS device and the PMOS device respectively.

By adopting the device of the present invention, the device forms a high-k dielectric layer on the NMOS device region and the PMOS device region respectively, and introduces work function adjustment dielectric layers of different materials thereon, which not only effectively adjusts the NMOS device and PMOS The threshold voltage of the device, and the work function adjustment dielectric layer is formed of different dielectric materials, which is easier to selectively etch, which is conducive to process control, and also relieves the pressure on the research of double metal gate materials. In addition, due to the high k For the gate dielectric layer, a relatively stable dielectric material at high temperature is selected, so the metal atoms in the material will not have a significant degradation effect on the channel carrier mobility of the device due to diffusion problems at a certain annealing temperature.

Description of drawings

1-11 illustrate schematic diagrams of various manufacturing stages of a semiconductor device according to an embodiment of the present invention.

Detailed ways

The present invention generally relates to a semiconductor device and a method of manufacturing the same. The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, components and arrangements of specific examples are described below. Of course, they are only examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and/or letters in different instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or arrangements discussed. In addition, various specific process and material examples are provided herein, but one of ordinary skill in the art will recognize the applicability of other processes and/or the use of other materials. Additionally, configurations described below in which a first feature is "on" a second feature may include embodiments where the first and second features are formed in direct contact, and may include additional features formed between the first and second features. For example, such that the first and second features may not be in direct contact.

Referring to FIG. 11 , FIG. 11 shows a schematic structural diagram of a semiconductor device according to an embodiment of the present invention. As shown in FIG. 11 , the device includes: a semiconductor substrate 202 having an NMOS region 204 and a PMOS region 206; a source region and a drain formed in the semiconductor substrate 202 and respectively belonging to the NMOS region 204 and the PMOS region 206 Regions 214, 216; the first gate stack 300 formed on the NMOS region 204 and the second gate stack 400 formed on the PMOS region 206; wherein, the first gate stack 300 includes: a first interface layer 208: the first high-k gate dielectric layer 224 on the first interface layer 208; the first work function adjusting dielectric layer 226 on the first high-k gate dielectric layer 224; formed on the first work The first metal gate electrode 230 on the function adjustment dielectric layer 226; the second gate stack 400 includes: the second interface layer 208; the second high-k gate dielectric layer 224 on the second interface layer 208; The second work function adjusting dielectric layer 228 on the second high-k gate dielectric layer 224; the second metal gate electrode 230 formed on the second work function adjusting dielectric layer 228; the first 226 and the second The work function adjusting medium layer 228 is formed by using different materials to adjust the work functions of the NMOS device and the PMOS device respectively.

Preferably, the first and second high-k gate dielectric layers 224 are selected from high-k dielectric materials that are relatively stable at high temperatures, and the metal atoms in the material will not be loaded on the channel of the device due to diffusion problems at a certain annealing temperature. The flow carrier mobility produces a significant degradation effect, which can be formed by selecting elements from the group consisting of: HfO ₂ , HfSiO _x , HfON _x , HfZrO _x , HfSiON _x , HfLaO _x , LaAlO _x , or combinations thereof, which are only example, the present invention is not limited thereto. The thickness of the first and second high-k gate dielectric layers 224 is about 1-3 nm.

Negative dipoles or a large number of positively charged charges are formed between the first work function adjusting medium layer 226 and the underlying layer 224 to adjust the effective work function. The first work function adjusting medium layer includes: MgO _x , oxides of rare earth and rare earth-like metal elements or their silicides, nitrides, or their combinations, examples of the first work function adjusting dielectric layer include: La ₂ O ₃ , Sc ₂ O ₃ , Gd ₂ O ₃ , MgO _x , or their silicides, nitrides, or other rare earth oxides or their silicides, nitrides, etc., are just examples, and the present invention is not limited thereto.

A positive dipole or a large amount of negatively charged charges are formed between the second work function adjusting medium layer 228 and the underlying layer 224 to adjust the effective work function. The second work function adjusting medium layer includes: Oxides of other active metal elements other than rare earth and rare earth-like metal elements or their silicides and nitrides. Examples of the second work function adjustment medium layer 228 include: Al ₂ O ₃ , TiO ₂ , ZrO ₂ , HfAlO _x , HfTiO _x , TaO _x , HfTaO _x , or their silicides, nitrides, or combinations thereof are just examples, and the present invention is not limited thereto. The thickness of the first 226 and the second work function adjustment medium layer 228 is about 0.1-2 nm. The first and second metal gate electrodes 230 have a one-layer or multi-layer structure.

The manufacture and implementation of the embodiment will be described in detail below with reference to FIGS. 1-11.

Referring to FIG. 1, a semiconductor substrate 202 is provided having an NMOS region 204 and a PMOS region 206, and an interfacial layer 208 is formed thereon.

Specifically, firstly, a semiconductor substrate 202 is provided. The substrate 202 has been pre-processed, and the processing operations include pre-cleaning, forming a well region and forming a shallow trench isolation region. In this embodiment, the substrate 202 is a silicon substrate. In other implementations In an example, the substrate 202 may also include other compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide or indium phosphide. The substrate 202 may include various doping configurations according to design requirements known in the art (eg, p-type substrate or n-type substrate). In addition, preferably, the substrate 202 includes an epitaxial layer, and the substrate 202 may also include a silicon-on-insulator (SOI) structure.

Then, an interface layer 208 is formed thereon. The interfacial layer 208 may be formed directly on the substrate 202 . In this embodiment, the interface layer 208 may be SiO ₂ , SiON or Si ₃ N ₄ . The thickness of the interface layer 208 is about 0.5-2 nm, and atomic layer deposition, chemical vapor deposition (CVD), high density plasma CVD, sputtering or other suitable methods can be used. The above is merely an example and not limited thereto.

Referring to FIG. 2 , a dummy gate 210 is formed on the interface layer 208 . The dummy gate 210 is a sacrificial layer, which can be formed by depositing polysilicon on the interface layer 208 , and its thickness is about 30-200 nm. The dummy gate 210 can also be formed by depositing other materials, such as amorphous silicon.

Referring to FIG. 3 , the interface layer 208 and the dummy gate 210 are patterned. By forming a mask layer (not shown in the figure) on the dummy gate 210, and then patterning the interface layer 208 and the dummy gate 210 using a dry or wet etching technique, to form The first interface layer 208 and dummy gate 210 of 204 belong to the second interface layer 208 and dummy gate 210 of the second region 206 .

Referring to FIG. 4, the sidewall 212 of the dummy gate belonging to the NMOS region 204 is formed, the sidewall 212 of the dummy gate belonging to the PMOS region 206 is formed, and the dummy gate sidewall 212 belonging to the NMOS region 204 and the PMOS region 206 are respectively formed in the semiconductor substrate 202. Source and drain regions 214,216.

The side wall 212 may be a one-layer or multi-layer structure, and in the embodiment of the present invention, it is a three-layer structure side wall. First, in the first region 204 and the second region 206, a nitride layer, such as silicon nitride or silicon oxynitride, is deposited by chemical deposition, such as atomic layer deposition or plasma enhanced chemical vapor deposition, and dry Etching technology, such as RIE method, is patterned to form the first spacer 212-1, and then, preferably, ion implantation of the source/drain extension region and/or the halo region can be performed, which can be performed according to the desired transistor The structure is formed by implanting p-type or n-type dopants or impurities into the substrate 202 in the first region 204 and the second region 206 . Then, an oxide material, such as silicon dioxide, is deposited on the device, and is patterned by using a dry etching technique, such as RIE, to form the second sidewall 212-2. Afterwards, another nitride material layer, such as silicon nitride or silicon oxynitride, is deposited on the device, and patterned by dry etching technology, such as RIE, to form the third side wall 212-3. The above side wall structure and its forming materials and methods are just examples, and are only examples, not limited thereto. In order to simplify the description, in the following descriptions and illustrations, the three-layer structure side walls including the first side wall 212-1, the second side wall 212-2, and the third side wall 212-3 are all described as side walls 212 .

After forming the spacers 212, ion implantation of the source region and the drain region may be performed by implanting p-type or n-type dopants or impurities into the substrates of the first region 204 and the second region 206 according to the desired transistor structure. The bottom 202 may be formed by methods including photolithography, ion implantation, diffusion and/or other suitable processes.

Referring to FIG. 5 , an inner dielectric layer (ILD) 218 is formed on the substrate 202 between the sidewall 212 of the first region 204 and the sidewall 212 of the second region 206 . First, deposit a dielectric material on the device, such as SiO ₂ , and then planarize it, such as CMP (Chemical Mechanical Polishing), to remove the dielectric material on the dummy gate 210 until the upper surface of the dummy gate 210 is exposed . The inner dielectric layer 218 may be, but not limited to, undoped silicon oxide (SiO ₂ ), doped silicon oxide (such as borosilicate glass, borophosphosilicate glass, etc.) and silicon nitride (Si ₃ N ₄ ). The inner dielectric layer 218 can be formed by methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) and/or other suitable techniques.

Referring to FIG. 6 , the dummy gates 210 of the NMOS region and the PMOS region are removed to form a first opening 220 and a second opening 222 . In one embodiment, the dummy gate 210 is etched and removed using a dry method, such as RIE, or a wet etching technique, such as tetramethylammonium hydroxide (TMAH), KOH or other suitable etchant solutions, Thus, a first opening 220 and a second opening 222 exposing the interface layer 208 are formed. In another embodiment, the interface layer 208 can be further removed by dry or wet etching techniques to form the first opening 220 and the second opening 222 of the substrate exposing the first region 204 and the second region 206 (Fig. not shown), and then redeposit the dielectric material to form a first interface layer in the first opening and a second interface layer in the second opening. The dielectric material can be SiO ₂ , SiON or Si ₃ N ₄ , to To improve the quality of the interface layer, the first and second interface layers are formed on the inner wall of the opening in this embodiment.

Referring to FIG. 7, a high-k gate dielectric layer 224 is formed on the device, which can be formed by depositing a high-k dielectric material (for example, a material with a high dielectric constant compared with silicon oxide) on the device, preferably Therefore, the high-k dielectric material is a dielectric material with stable performance at high temperature, and the metal atoms in the material will not have a significant degradation effect on the channel carrier mobility of the device due to diffusion problems at a certain annealing temperature, such as HfO _2. HfSiO _x , HfON _x , HfZrO _x , HfSiON _x , HfLaO _x , LaAlO _x and their combinations and/or other suitable materials can be formed by chemical vapor deposition, atomic layer deposition (ALD) or other suitable methods, and the thickness is about 1-3nm. This is just an example, and the present invention is not limited thereto.

Referring to FIG. 8, a first work function adjusting medium layer 226 is formed on the high-k gate dielectric layer 224 of the NMOS region 204, and a second work function adjusting medium is formed on the high-k gate dielectric layer 226 of the PMOS region 206. Layer 228. After the high-k gate dielectric layer 224 is formed, the first work function adjustment dielectric layer 226 belonging to the NMOS region 204 can be deposited thereon, and a negative dipole is formed between the first work function adjustment dielectric layer 226 and the underlying layer 224 Or a large number of positively charged charges, the negative dipole or positive charge will play a role in adjusting the effective work function, and the first work function adjusting dielectric layer can include: MgO _x , oxidation of rare earth and rare earth-like metal elements or their silicides, nitrides, or their combinations, examples of the first work function adjusting dielectric layer include: La ₂ O ₃ , Sc ₂ O ₃ , Gd ₂ O ₃ , MgO _x , or their silicides , nitride, or other rare earth oxides and their silicides and nitrides, etc., these are just examples, and the present invention is not limited thereto. And on the high-k gate dielectric layer 224, a second work function adjustment dielectric layer 228 belonging to the PMOS region 206 is formed, and a positive dipole or a large number of negatively charged The charge of the positive dipole or negative charge will play a role in adjusting the effective work function, and the second work function adjustment medium layer includes: oxides containing other active metal elements except rare earth and rare earth metal elements Or its silicide, nitride, the example of the second work function adjusting dielectric layer 228 includes: Al ₂ O ₃ , TiO ₂ , ZrO ₂ , HfAlO x , HfTiO _x , _{TaO x ,} HfTaO _x , or their silicides , nitride, or a combination thereof, which are just examples, and the present invention is not limited thereto. The thickness of the first and second work function adjusting medium layers is about 0.1-2 nm. The work function adjusting medium layers 226 and 228 can be sputtered, PLD, MOCVD, ALD, PEALD or other suitable methods.

Referring to FIGS. 9-10 , metal gate electrodes 230 belonging to the NMOS region 204 and the PMOS region 206 are formed on the device. The metal gate electrode 230 can be a one-layer or multi-layer structure. The metal gate electrodes on the NMOS region 204 and the PMOS region 206 can have the same or different materials, preferably the same material. In the embodiment of the present invention, the metal gate electrodes are A two-layer structure, and the metal gate electrodes on the NMOS region 204 and the PMOS region 206 have the same material, first deposit a metal material layer 230-1 on the device, such as TiN, etc., and then deposit on the metal material layer 230-1 Another metal material layer 230 - 2 filling the openings 220 , 222 is formed thereon, such as low-resistance metal Al, Ti, TiAl, W, etc. This is just an example, and the present invention is not limited thereto. The metal gate electrode may be formed by selecting an element from the group consisting of TiN, TaN, MoN, HfN, HfC, TaC, TiC, MoC, TiAlN, TaAlN, HfAlN, HfTbN, TaTbN, TaErN, TaYbN, TaSiN, TaHfN, TiHfN, HfSiN, MoSiN, MoAlN, _RuTax , _NiTax , polysilicon, metal silicide, or combinations thereof.

Referring to FIG. 11 , a first gate stack belonging to the NMOS region and a second gate stack belonging to the PMOS region are respectively formed. The previously formed layer stack is patterned to form a gate stack 300 for devices in the NMOS region, and a gate stack 400 for devices in the PMOS region. The formation of the gate stack 300 and the gate stack 400 can be accomplished by performing one or more etchings on the previous layer stack. Further, a semiconductor device according to an embodiment of the present invention is formed.

In the present invention, in the process of preparing a CMOS transistor by a gate replacement process (Replacement gate or Gate last), after forming a high-k gate dielectric layer in the gate NMOS device region and the PMOS device region, respectively form the first work function adjustment belonging to the NMOS region The dielectric layer and the second work function adjustment dielectric layer belonging to the PMOS region, where the high-k gate dielectric layer is selected to be a dielectric that will not have a significant degradation effect on the channel carrier mobility of the device due to diffusion problems at a certain annealing temperature materials, and the first work function adjusting medium layer contains elements that can adjust the threshold voltage of NMOS devices, such as La, Sc, Gd, etc., and the second work function adjusting medium layer contains elements that can adjust the threshold voltage of PMOS devices, such as Al, Ti, etc., to adjust the threshold voltage of NMOS devices and PMOS devices respectively, and because of the use of dielectric materials, it is easier to selectively etch, which is conducive to process control, and also relieves the pressure on the research of double metal gate materials.

Although the example embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made to these embodiments without departing from the spirit and scope of the invention as defined by the appended claims. For other examples, those of ordinary skill in the art will readily understand that the order of process steps may be varied while remaining within the scope of the present invention.

In addition, the scope of application of the present invention is not limited to the process, mechanism, manufacture, material composition, means, method and steps of the specific embodiments described in the specification. From the disclosure of the present invention, those of ordinary skill in the art will easily understand that for the processes, mechanisms, manufacturing, material compositions, means, methods or steps that currently exist or will be developed in the future, they are implemented in accordance with the present invention Corresponding embodiments described which function substantially the same or achieve substantially the same results may be applied in accordance with the present invention. Therefore, the appended claims of the present invention are intended to include these processes, mechanisms, manufacture, material compositions, means, methods or steps within their protection scope.

Claims (17)

1. A semiconductor device, comprising: a semiconductor substrate having an NMOS region and a PMOS region; A source region and a drain region respectively belonging to an NMOS region and a PMOS region are formed in the semiconductor substrate; a first gate stack formed on the NMOS region substrate and a second gate stack formed on the PMOS region substrate; Wherein, the first gate stack includes: a first interface layer; a first high-k gate dielectric layer formed on the first interface layer; a first work function layer formed on the first high-k gate dielectric layer adjusting dielectric layer; a first metal gate electrode formed on the first work function adjusting dielectric layer; The second gate stack includes: a second interface layer; a second high-k gate dielectric layer formed on the second interface layer; a second work function adjustment medium formed on the second high-k gate dielectric layer layer; a second metal gate electrode formed on the second work function adjusting dielectric layer; Wherein the first and second work function adjusting dielectric layers are formed of different materials to adjust the work functions of the NMOS device and the PMOS device respectively. 2. The device according to claim 1, wherein the metal atoms in the material of the first and second high-k gate dielectric layers will not migrate to the channel carriers of the device due to diffusion problems at a certain annealing temperature rate has a noticeable degradation effect. 3. The device according to claim 2, wherein the first and second high-k gate dielectric layers can be formed by selecting elements from the group comprising: HfO ₂ , HfSiO _x , HfON _x , HfZrO _x , HfSiON _x , _HfLaOx , _LaAlOx , or combinations thereof. 4. The device according to claim 1, wherein a negative dipole or a large number of positive charges are formed between the first work function adjusting dielectric layer and the layer below, so as to adjust the effective work function. 5 . The device according to claim 4 , wherein the first work function adjusting medium layer comprises: MgO _x , oxides of rare earth or rare earth-like metal elements or their silicides, nitrides, or combinations thereof. 6 . The device according to claim 1 , wherein a positive dipole or a large amount of negatively charged charges are formed between the second work function adjusting dielectric layer and the layer below, so as to adjust the effective work function. 7. The device according to claim 6, wherein the second work function adjusting medium layer comprises: oxides or silicides and nitrides of active metal elements other than rare earth and rare earth-like metal elements, the second The second work function adjustment medium layer is formed by selecting elements from the group consisting of the following elements: Al ₂ O ₃ , TiO ₂ , ZrO ₂ , HfAlO _x , HfTiO _x , TaO _x , HfTaO _x , or their silicides, nitrides, or its combination. 8. The device of claim 1, wherein the first and second metal gate electrodes are a one-layer or multi-layer structure. 9. A method of manufacturing a semiconductor device, the method comprising: providing a semiconductor substrate having an NMOS region and a PMOS region; On the semiconductor substrate, a first interface layer, a dummy gate and its sidewalls belonging to the NMOS region are formed, a second interface layer, a dummy gate and its sidewalls belonging to the PMOS region are formed, and in the semiconductor substrate Forming a source region and a drain region belonging to the NMOS region and the PMOS region respectively, and covering the source region and the drain region of the NMOS and PMOS regions to form an interlayer dielectric layer; removing the dummy gates of the NMOS region and the PMOS region to form a first opening and a second opening; forming a first high-k gate dielectric layer covering the first interface layer in the first opening, and forming a second high-k gate dielectric layer covering the second interface layer in the second opening; forming a first work function adjusting dielectric layer on the first high-k gate dielectric layer, and forming a second work function adjusting dielectric layer on the second high-k gate dielectric layer; Forming a first metal gate electrode filling the first opening on the first work function adjusting medium layer, forming a second metal gate electrode filling the second opening on the second work function adjusting medium layer electrode; processing the device to respectively form a first gate stack belonging to the NMOS region and a second gate stack belonging to the PMOS region; Wherein the first and second work function adjusting dielectric layers are formed of different materials to adjust the work functions of the NMOS device and the PMOS device respectively. 10. The method according to claim 9, further comprising further removing the first and second interface layers to form the first opening and the second opening, and re-forming the first interface layer, the second opening in the first opening A second interfacial layer is formed inside. 11. The method according to claim 9, wherein the metal atoms in the materials of the first and second high-k gate dielectric layers will not migrate to the channel carriers of the device due to diffusion problems at a certain annealing temperature rate has a noticeable degradation effect. 12. The method according to claim 11, wherein the first and second high-k gate dielectric layers can be formed by selecting elements from the group consisting of: HfO ₂ , HfSiO _x , HfON _x , HfZrO _x , HfSiON _x , _HfLaOx , _LaAlOx , or combinations thereof. 13. The method according to claim 9, wherein a negative dipole or a large number of positive charges are formed between the first work function adjusting dielectric layer and the layer below, so as to adjust the effective work function. 14. The method according to claim 13, wherein the first work function adjusting medium layer comprises: MgO _x , oxides of rare earth or rare earth-like metal elements or their silicides, nitrides, or combinations thereof. 15 . The method according to claim 9 , wherein a positive dipole or a large amount of negatively charged charges are formed between the second work function adjusting dielectric layer and the underlying layer, so as to adjust the effective work function. 16. The method according to claim 15, wherein the second work function adjusting medium layer comprises: oxides or silicides and nitrides of active metal elements other than rare earth and rare earth metal elements, the second The second work function adjustment medium layer is formed by selecting elements from the group consisting of the following elements: Al ₂ O ₃ , TiO ₂ , ZrO ₂ , HfAlO _x , HfTiO _x , TaO _x , HfTaO _x , or their silicides, nitrides, or its combination. 17. The method of claim 9, wherein the first and second metal gate electrodes are a one-layer or multi-layer structure.

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