CN104409488A - Breakdown-preventing SOI folding gate insulated tunneling bipolar transistor and making method thereof - Google Patents

Abstract

The invention relates to an anti-breakdown SOI folded gate insulated tunneling bipolar transistor. Compared with MOSFETs or tunneling field effect transistors of the same size, the breakdown protection region with low impurity concentration is introduced into the collector junction and the emitter junction to significantly improve the The forward and reverse anti-breakdown ability of the device at the deep nanometer scale; there are insulating tunneling structures on both sides and the upper surface of the base region, and the insulating tunneling effect occurs simultaneously on both sides of the base region and on the upper surface under the control of the gate electrode. The upper surface, thus increasing the generation rate of tunneling current; using the extremely sensitive relationship between the resistance of the tunneling insulating layer and its internal field strength to achieve excellent switching characteristics; enhancing the tunneling signal through the emitter to achieve excellent forward conduction characteristics; in addition, the present invention also proposes a specific manufacturing method of an anti-breakdown SOI folded gate insulated tunneling bipolar transistor unit and its array. The transistor significantly improves the working characteristics of the nanoscale integrated circuit unit and is suitable for popularization and application.

Description

Anti-breakdown SOI folded gate insulated tunneling bipolar transistor and manufacturing method thereof

Technical field:

The invention relates to the field of ultra-large-scale integrated circuit manufacturing, and relates to a structure of an anti-breakdown SOI folded-gate insulated tunneling bipolar transistor suitable for the manufacture of high-performance ultra-high-integrated integrated circuits. The specific manufacturing method of the pole transistor array.

Background technique:

At present, with the continuous improvement of the integration level, the source electrode and the channel or between the drain electrode and the channel of the integrated circuit unit Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) devices form a steep mutation PN within a few nanometers. Junction, when the drain-source voltage is large, this steep abrupt PN junction will have a breakdown effect, which will cause the device to fail. As the size of the device continues to shrink, this breakdown effect becomes more and more obvious. In addition, the continuous shortening of the channel length leads to the increase of the sub-threshold swing of MOSFETs, which leads to the serious degradation of switching characteristics and the obvious increase of static power consumption. Although the degradation of device performance can be alleviated by improving the gate electrode structure, when the device size is further reduced to below 20 nanometers, even with the optimized gate electrode structure, the subthreshold swing of the device will also decrease. increases with further reductions in the device channel length, resulting in another deterioration in device performance.

Tunneling Field Effect Transistors (TFETs), compared with MOSFETs, although its average subthreshold swing has been improved, but its forward conduction current is too small. The narrow material used to form the tunneling part of the tunneling field effect transistor can increase the tunneling probability to improve the transfer characteristics, but increases the difficulty of the process. In addition, the use of high dielectric constant insulating material as the insulating dielectric layer between the gate and the substrate can improve the control ability of the gate to the electric field distribution of the channel, but it cannot substantially increase the tunneling probability of the silicon material, so There is a limited improvement in transfer characteristics for tunneling field effect transistors.

Invention content:

purpose of invention

In order to significantly improve the ability of sub-20nm-scale devices to prevent breakdown under the premise of being compatible with existing silicon-based process technologies; significantly improve the switching characteristics of nanoscale integrated circuit basic unit devices; For current conduction characteristics, the present invention provides a structure of an anti-breakdown SOI folded gate insulated tunneling bipolar transistor suitable for high-performance and high-integration integrated circuit manufacturing, and a manufacturing method for its unit and array.

Technical solutions

The present invention is achieved through the following technical solutions:

The anti-breakdown SOI folded gate insulated tunneling bipolar transistor is characterized in that: an SOI wafer including a single crystal silicon substrate 1 and a wafer insulating layer 2 is used as the substrate for generating the device; the emitter region 3, the base region 4, The collector region 5 and the breakdown protection region 12 are located above the wafer insulating layer 2 of the SOI wafer, the base region 4 and the breakdown protection region 12 are located between the emitter region 3 and the collector region 5, and the breakdown protection region 12 is located Both sides of the base region 4; the emitter 9 is located above the emitter region 3; the collector 10 is located above the collector region 5; the folded conductive layer 6 forms three sides surrounding the upper surface and both sides of the base region 4; the folded tunnel insulation The layer 7 surrounds the upper surface and both sides of the folded conductive layer 6 on three sides; the folded gate electrode 8 surrounds the upper surface and both sides of the folded tunnel insulating layer 7 on three sides; the blocking insulating layer 11 is an insulating medium.

In order to achieve the device function described in the present invention, the present invention proposes an anti-breakdown SOI folded gate insulated tunneling bipolar transistor, whose core structural features are:

The impurity concentration of the breakdown protection region 12 is lower than 10 ¹⁶ per cubic centimeter.

The impurity concentration of the base region 4 is not lower than 10 ¹⁷ per cubic centimeter, and the two sides and the upper surface of the base region 4 are in contact with the folded conductive layer 6 to form an ohmic contact.

There are opposite impurity types between the emitter region 3 and the base region 4, between the collector region 5 and the base region 4, and an ohmic contact is formed between the emitter region 3 and the emitter electrode 9, and an ohmic contact is formed between the collector region 3 and the collector electrode 10. ohmic contact.

The folded conductive layer 6 is a metal material or a semiconductor material having the same impurity type as the base region 4 and a doping concentration greater than 10 ¹⁹ per cubic centimeter.

The folded tunneling insulating layer 7 is an insulating material layer for generating tunneling current.

The folded conductive layer 6, the folded tunnel insulating layer 7 and the folded gate electrode 8 are all isolated from the emitter region 3, the emitter electrode 9, the collector region 5 and the collector electrode 10 by the blocking insulating layer 11; the adjacent emitter region 3 and the collector electrode The electrical regions 5 are isolated by blocking insulating layers 11 , and adjacent emitters 9 and collectors 10 are isolated by blocking insulating layers 11 .

The folded conductive layer 6, the folded tunnel insulating layer 7 and the folded gate electrode 8 together constitute the tunneling base of the anti-breakdown SOI folded gate insulated tunneling bipolar transistor. When tunneling occurs under control, current flows from the folded gate electrode 8 through the folded tunnel insulating layer 7 to the folded conductive layer 6 and supplies power to the base region 4 .

The anti-breakdown SOI folded gate insulated tunneling bipolar transistor, taking the N-type as an example, the emitter region 3, the base region 4 and the collector region 5 are respectively the N region, the P region and the N region, and its specific working principle is as follows: when When the collector electrode 10 is forward biased and the folded gate electrode 8 is at a low potential, there is not enough potential difference formed between the folded gate electrode 8 and the folded conductive layer 6. At this time, the folded tunnel insulating layer 7 is in a high-resistance state. The polar insulating layer is similar, and there is no obvious tunneling current to pass through, so it is impossible to form a large enough base current between the base region 4 and the emitter region 3 to drive the anti-breakdown SOI folded gate insulation tunneling bipolar transistor, that is, the device is in the off state. off state; as the voltage of the folded gate electrode 8 gradually increases, the potential difference between the folded gate electrode 8 and the folded conductive layer 6 gradually increases, so that the folded tunnel insulation between the folded gate electrode 8 and the folded conductive layer 6 The electric field intensity in the layer 7 gradually increases accordingly. When the electric field intensity in the folded tunneling insulating layer 7 is below the critical value, the folded tunneling insulating layer 7 always maintains a good high resistance state, and the folded gate electrode 8 and the emission The potential difference between the poles 9 is almost completely dropped between the inner wall and the outer wall of the folded tunnel insulating layer 7, which makes the potential difference between the base region 4 and the emitter region 3 extremely small, so there is almost no current flowing in the base region , the device also maintains a good off state, and when the electric field strength in the folded tunneling insulating layer 7 reaches and exceeds a critical value, the folded gate electrode 8 and the folded conductive layer 6 will occur through the folded tunneling insulating layer 7 The tunneling of carriers, the folded tunneling insulating layer 7 will produce obvious tunneling current due to the tunneling effect, and the tunneling current will rise steeply at an extremely fast speed with the increase of the potential of the folded gate electrode 8, which This makes the folded tunneling insulating layer 7 rapidly switch from a high-resistance state to a low-resistance state within the extremely short potential change interval of the folded gate electrode 8; when the folded tunneling insulating layer 7 is in a low-resistance state, the folded tunneling insulating layer 7 The resistance formed between the folded gate electrode 8 and the folded conductive layer 6 is much smaller than the resistance formed between the folded conductive layer 6 and the emitter 3, which makes the potential difference between the folded gate electrode 8 and the emitter 9 It lands almost completely between the base region 4 and the emitter region 3, forming a sufficiently large forward bias voltage, and under the action of the tunneling effect, a large amount of electron movement is generated between the inner wall and the outer wall of the folded tunneling insulating layer 7, That is, a current source is provided for the base region 4, so that a sufficiently large base region current is formed between the base region 4 and the emitter region 3 to drive the anti-breakdown SOI folded-gate-insulated tunneling bipolar transistor, that is, the device is in an on state.

The anti-breakdown SOI folded gate insulated tunneling bipolar transistor prevents forward and reverse breakdown of the device through the breakdown protection region 12 . Taking an N-type device as an example, when the collector 10 is forward-biased relative to the emitter 9, the collector junction composed of the folded conductive layer 6, the base region 4, the breakdown protection region 12 and the collector region 5 is in a reverse-biased state , the breakdown protection zone 12 located between the base region 4 and the collector region 5 has an anti-breakdown protection effect on the reverse-biased collector junction, so it can significantly improve the forward withstand voltage capability of the device; when the collector electrode 10 is relative to the emitter When the pole 9 is reverse-biased, the emitter junction composed of the folded conductive layer 6, the base region 4, the breakdown protection region 12 and the emission region 3 is in a reverse-biased state, and the breakdown protection region between the base region 4 and the emission region 3 12 It has anti-breakdown protection for the reverse-biased emitter junction, so it can significantly improve the reverse withstand voltage capability of the device;

The anti-breakdown SOI folded gate insulated tunneling bipolar transistor has an insulating tunneling structure on both sides and the upper surface of the base region 4. Under the control of the folded gate electrode 8, the insulating tunneling effect occurs simultaneously on both sides of the base region. side and upper surface, thus greatly increasing the generation rate of tunneling current.

The anti-breakdown SOI folded gate insulation tunneling bipolar transistor uses the extremely sensitive relationship between the impedance of the folded tunneling insulating layer 7 and the electric field strength in the tunneling insulating layer, and selects an appropriate tunnel insulating layer 7 for the folded tunneling insulating layer 7. material, and by properly adjusting the sidewall height, sidewall thickness, and top thickness of the folded tunneling insulating layer 7, the folded tunneling insulating layer 7 can realize a high resistance state and a low The conversion between resistance states greatly improves the switching characteristics of the device.

Anti-breakdown SOI folded gate insulation tunneling bipolar transistor, the gate insulation tunneling current flows through the folded conductive layer 6 to the base region 4, and passes through the emitter region 3 for signal enhancement, and ordinary TFETs only use a small amount of tunneling current between semiconductor bands Compared with the conduction current of the device, it has better forward current conduction characteristics. Based on the above reasons, compared with ordinary TFETs devices, the anti-breakdown SOI folded gate insulation tunneling bipolar transistor can achieve higher forward conduction Pass current.

Advantages and effects

The present invention has following advantage and beneficial effect:

1. Put the breakdown function

The anti-breakdown SOI folded gate insulated tunneling bipolar transistor prevents forward and reverse breakdown of the device through the breakdown protection region 12 . Taking an N-type device as an example, when the collector 10 is forward-biased relative to the emitter 9, the collector junction composed of the folded conductive layer 6, the base region 4, the breakdown protection region 12 and the collector region 5 is in a reverse-biased state , the breakdown protection zone 12 located between the base region 4 and the collector region 5 has an anti-breakdown protection effect on the reverse-biased collector junction, so it can significantly improve the forward withstand voltage capability of the device; when the collector electrode 10 is relative to the emitter When the pole 9 is reverse-biased, the emitter junction composed of the folded conductive layer 6, the base region 4, the breakdown protection region 12 and the emission region 3 is in a reverse-biased state, and the breakdown protection region between the base region 4 and the emission region 3 12 It has anti-breakdown protection for the reverse-biased emitter junction, so it can significantly improve the reverse withstand voltage capability of the device;

2. High tunneling current generation rate

The anti-breakdown SOI folded gate insulated tunneling bipolar transistor has an insulating tunneling structure on both sides and the upper surface of the base region 4. Under the control of the folded gate electrode 8, the insulating tunneling effect occurs simultaneously on both sides of the base region. side and upper surface, thus greatly increasing the generation rate of tunneling current.

2. Significantly improved switching characteristics

The anti-breakdown SOI folded gate insulation tunneling bipolar transistor uses the extremely sensitive relationship between the impedance of the folded tunneling insulating layer 7 and the electric field strength in the tunneling insulating layer, and selects an appropriate tunnel insulating layer 7 for the folded tunneling insulating layer 7. material, and by properly adjusting the sidewall height, sidewall thickness, and top thickness of the folded tunneling insulating layer 7, the folded tunneling insulating layer 7 can realize a high resistance state and a low The conversion between resistance states greatly improves the switching characteristics of the device.

3. Improvement of positive communication ability

Anti-breakdown SOI folded gate insulation tunneling bipolar transistor, the gate insulation tunneling current flows through the folded conductive layer 6 to the base region 4, and passes through the emitter region 3 for signal enhancement, and ordinary TFETs only use a small amount of tunneling current between semiconductor bands Compared with the conduction current of the device, it has better forward current conduction characteristics. Based on the above reasons, compared with ordinary TFETs devices, the anti-breakdown SOI folded gate insulation tunneling bipolar transistor can achieve higher forward conduction Pass current.

Description of drawings

Fig. 1 is a three-dimensional structural schematic diagram of the anti-breakdown SOI folded gate insulated tunneling bipolar transistor formed on the SOI substrate of the present invention;

FIG. 2 is a schematic diagram of a three-dimensional structure of the anti-breakdown SOI folded gate insulated tunneling bipolar transistor of the present invention after stripping off the blocking insulating layer 11;

3 is a three-dimensional schematic diagram of the anti-breakdown SOI folded gate insulated tunneling bipolar transistor of the present invention after stripping the emitter 9, the collector 10 and the blocking insulating layer 11;

4 is a three-dimensional schematic diagram of the anti-breakdown SOI folded gate insulated tunneling bipolar transistor of the present invention after stripping the emitter 9, the collector 10, the blocking insulating layer 11 and the folded gate electrode 8;

5 is a three-dimensional schematic diagram of the anti-breakdown SOI folded gate insulating tunneling bipolar transistor of the present invention after stripping the emitter 9, the collector 10, the blocking insulating layer 11, the folded gate electrode 8 and the folded tunneling insulating layer 7;

Fig. 6 is the anti-breakdown SOI folded gate insulation tunneling bipolar transistor of the present invention after the emitter 9, the collector 10, the blocking insulating layer 11, the folded gate electrode 8, the folded tunneling insulating layer 7 and the folded conductive layer 6 are stripped off. 3D structure diagram;

Fig. 7 is a two-dimensional cross-sectional view of the anti-breakdown SOI folded gate insulated tunneling bipolar transistor of the present invention cut along the plane A in Fig. 1;

Fig. 8 is a two-dimensional cross-sectional view of the anti-breakdown SOI folded gate insulated tunneling bipolar transistor of the present invention cut along the B plane in Fig. 1;

Figure 9 is a schematic top view of Step 1,

Fig. 10 is a schematic cross-sectional view obtained by cutting along the tangent line A in Fig. 9,

Figure 11 is a schematic top view of step 2,

Fig. 12 is a schematic cross-sectional view of step 2 obtained by cutting along tangent line A in Fig. 11,

Figure 13 is a schematic top view of Step 3,

Fig. 14 is a schematic cross-sectional view of step 3 obtained by cutting along tangent line A in Fig. 13,

Figure 15 is a schematic top view of Step 4,

Fig. 16 is a schematic cross-sectional view of step 4 obtained by cutting along tangent line A in Fig. 15,

Figure 17 is a schematic top view of Step 5,

Fig. 18 is a schematic cross-sectional view of step 5 obtained by cutting along the tangent line B in Fig. 17,

Figure 19 is a schematic top view of step six,

Fig. 20 is a schematic cross-sectional view of step 6 obtained by cutting along the tangent line B in Fig. 19,

Figure 21 is a schematic top view of Step 7,

Fig. 22 is a schematic cross-sectional view of step 7 obtained by cutting along the tangent line B in Fig. 21,

Figure 23 is a schematic top view of Step 8,

Fig. 24 is a schematic cross-sectional view of step 8 obtained by cutting along tangent line A in Fig. 23,

Fig. 25 is a schematic cross-sectional view of step 8 obtained by cutting along the tangent line B in Fig. 23,

Figure 26 is a schematic top view of step nine,

Fig. 27 is a schematic cross-sectional view of step nine obtained by cutting along tangent line A in Fig. 26,

Fig. 28 is a schematic cross-sectional view of step nine obtained by cutting along the tangent line B in Fig. 26,

Figure 29 is a schematic top view of step ten,

Fig. 30 is a schematic cross-sectional view of step 10 obtained by cutting along tangent line A in Fig. 29,

Fig. 31 is a schematic cross-sectional view of step ten obtained by cutting along the tangent line B in Fig. 29,

Figure 32 is a schematic top view of step eleven,

Fig. 33 is a schematic cross-sectional view of step 11 obtained by cutting along tangent line A in Fig. 32,

Fig. 34 is a schematic cross-sectional view of step eleven obtained by cutting along the tangent line B in Fig. 32,

Fig. 35 is a schematic top view of step 12,

Fig. 36 is a schematic cross-sectional view of step 12 obtained by cutting along tangent line A in Fig. 35,

Fig. 37 is a schematic cross-sectional view of step 12 obtained by cutting along the tangent line B in Fig. 35,

Fig. 38 is a schematic top view of step 13,

Fig. 39 is a schematic cross-sectional view of step 13 obtained by cutting along tangent line A in Fig. 38,

Fig. 40 is a schematic cross-sectional view of step 13 obtained by cutting along tangent line B in Fig. 38,

Figure 41 is a schematic top view of step fourteen,

Fig. 42 is a schematic cross-sectional view of step 14 obtained by cutting along tangent line A in Fig. 41,

Fig. 43 is a schematic cross-sectional view of step 14 obtained by cutting along tangent line B in Fig. 41,

Figure 44 is a schematic top view of step fifteen,

Fig. 45 is a schematic cross-sectional view of step 15 obtained by cutting along tangent line A in Fig. 44,

Fig. 46 is a schematic cross-sectional view of step 15 obtained by cutting along tangent line B in Fig. 44,

Figure 47 is a schematic top view of step sixteen,

Fig. 48 is a schematic cross-sectional view of step 16 obtained by cutting along tangent line A in Fig. 47,

Figure 49 is a schematic top view of step seventeen,

FIG. 50 is a schematic cross-sectional view of step seventeen obtained by cutting along the tangent line A in FIG. 49 .

Explanation of reference signs:

1. Single crystal silicon substrate; 2. Wafer insulating layer; 3. Emitter region; 4. Base region; 5. Collector region; 6. Folded conductive layer; 7. Folded tunneling insulating layer; 8. Folded gate electrode ; 9, emitter; 10, collector; 11, blocking insulating layer; 12, breakdown protection zone.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings: Fig. 1 is the three-dimensional structure schematic diagram that the anti-breakdown SOI folded gate insulated tunneling bipolar transistor of the present invention is formed on the SOI substrate; Fig. 2 is the anti-breakdown SOI folded gate of the present invention Schematic diagram of the three-dimensional structure of the insulated tunneling bipolar transistor after stripping the blocking insulating layer 11; FIG. Figure 4 is a three-dimensional structural schematic diagram of the anti-breakdown SOI folded gate insulated tunneling bipolar transistor of the present invention after stripping the emitter 9, collector 10, blocking insulating layer 11 and folded gate electrode 8; Figure 5 is The anti-breakdown SOI folded gate insulated tunneling bipolar transistor of the present invention is a three-dimensional structural schematic diagram after stripping the emitter 9, the collector 10, the blocking insulating layer 11, the folded gate electrode 8 and the folded tunneling insulating layer 7; FIG. 6 is the present invention. The three-dimensional structural diagram of the anti-breakdown SOI folded gate insulated tunneling bipolar transistor after stripping off the emitter 9, the collector 10, the blocking insulating layer 11, the folded gate electrode 8, the folded tunneling insulating layer 7 and the folded conductive layer 6; Fig. 7 is a two-dimensional cross-sectional view of the anti-breakdown SOI folded gate insulated tunneling bipolar transistor of the present invention obtained after cutting along the plane A in Fig. 1; The two-dimensional cross-sectional view obtained after cutting the B plane in Fig. 1;

It specifically includes a single crystal silicon substrate 1; a wafer insulating layer 2; an emitter region 3; a base region 4; a collector region 5; a folded conductive layer 6; a folded tunnel insulating layer 7; a folded gate electrode 8; an emitter 9; electrode 10; blocking insulating layer 11; breakdown protection region 12.

The anti-breakdown SOI folded gate insulated tunneling bipolar transistor is characterized in that: an SOI wafer including a single crystal silicon substrate 1 and a wafer insulating layer 2 is used as the substrate for generating the device; the emitter region 3, the base region 4, The collector region 5 and the breakdown protection region 12 are located above the wafer insulating layer 2 of the SOI wafer, the base region 4 and the breakdown protection region 12 are located between the emitter region 3 and the collector region 5, and the breakdown protection region 12 is located Both sides of the base region 4; the emitter 9 is located above the emitter region 3; the collector 10 is located above the collector region 5; the folded conductive layer 6 forms three sides surrounding the upper surface and both sides of the base region 4; the folded tunnel insulation The layer 7 surrounds the upper surface and both sides of the folded conductive layer 6 on three sides; the folded gate electrode 8 surrounds the upper surface and both sides of the folded tunnel insulating layer 7 on three sides; the blocking insulating layer 11 is an insulating medium.

In order to achieve the device function described in the present invention, the present invention proposes an anti-breakdown SOI folded gate insulated tunneling bipolar transistor, whose core structural features are:

The impurity concentration of the breakdown protection region 12 is lower than 10 ¹⁶ per cubic centimeter.

The impurity concentration of the base region 4 is not lower than 10 ¹⁷ per cubic centimeter, and the two sides and the upper surface of the base region 4 are in contact with the folded conductive layer 6 to form an ohmic contact.

There are opposite impurity types between the emitter region 3 and the base region 4, between the collector region 5 and the base region 4, and an ohmic contact is formed between the emitter region 3 and the emitter electrode 9, and an ohmic contact is formed between the collector region 3 and the collector electrode 10. ohmic contact.

The folded conductive layer 6 is a metal material or a semiconductor material having the same impurity type as the base region 4 and a doping concentration greater than 10 ¹⁹ per cubic centimeter.

The folded tunneling insulating layer 7 is an insulating material layer for generating tunneling current;

The folded conductive layer 6 , the folded tunnel insulating layer 7 and the folded gate electrode 8 are all isolated from the emitter region 3 , the emitter 9 , the collector region 5 and the collector 10 by the blocking insulating layer 11 .

The folded conductive layer 6, the folded tunnel insulating layer 7 and the folded gate electrode 8 together constitute the tunneling base of the anti-breakdown SOI folded gate insulated tunneling bipolar transistor. When tunneling occurs under control, current flows from the folded gate electrode 8 through the folded tunnel insulating layer 7 to the folded conductive layer 6 and supplies power to the base region 4 .

The anti-breakdown SOI folded gate insulated tunneling bipolar transistor, taking the N-type as an example, the emitter region 3, the base region 4 and the collector region 5 are respectively the N region, the P region and the N region, and its specific working principle is as follows: when When the collector electrode 10 is forward biased and the folded gate electrode 8 is at a low potential, there is not enough potential difference formed between the folded gate electrode 8 and the folded conductive layer 6. At this time, the folded tunnel insulating layer 7 is in a high-resistance state. The polar insulating layer is similar, and there is no obvious tunneling current to pass through, so it is impossible to form a large enough base current between the base region 4 and the emitter region 3 to drive the anti-breakdown SOI folded gate insulation tunneling bipolar transistor, that is, the device is in the off state. off state; as the voltage of the folded gate electrode 8 gradually increases, the potential difference between the folded gate electrode 8 and the folded conductive layer 6 gradually increases, so that the folded tunnel insulation between the folded gate electrode 8 and the folded conductive layer 6 The electric field intensity in the layer 7 gradually increases accordingly. When the electric field intensity in the folded tunneling insulating layer 7 is below the critical value, the folded tunneling insulating layer 7 always maintains a good high resistance state, and the folded gate electrode 8 and the emission The potential difference between the poles 9 is almost completely dropped between the inner wall and the outer wall of the folded tunnel insulating layer 7, which makes the potential difference between the base region 4 and the emitter region 3 extremely small, so there is almost no current flowing in the base region , the device also maintains a good off state, and when the electric field strength in the folded tunneling insulating layer 7 reaches and exceeds a critical value, the folded gate electrode 8 and the folded conductive layer 6 will occur through the folded tunneling insulating layer 7 The tunneling of carriers, the folded tunneling insulating layer 7 will produce obvious tunneling current due to the tunneling effect, and the tunneling current will rise steeply at an extremely fast speed with the increase of the potential of the folded gate electrode 8, which This makes the folded tunneling insulating layer 7 rapidly switch from a high-resistance state to a low-resistance state within the extremely short potential change interval of the folded gate electrode 8; when the folded tunneling insulating layer 7 is in a low-resistance state, the folded tunneling insulating layer 7 The resistance formed between the folded gate electrode 8 and the folded conductive layer 6 is much smaller than the resistance formed between the folded conductive layer 6 and the emitter 3, which makes the potential difference between the folded gate electrode 8 and the emitter 9 It lands almost completely between the base region 4 and the emitter region 3, forming a sufficiently large forward bias voltage, and under the action of the tunneling effect, a large amount of electron movement is generated between the inner wall and the outer wall of the folded tunneling insulating layer 7, That is, a current source is provided for the base region 4, so that a sufficiently large base region current is formed between the base region 4 and the emitter region 3 to drive the anti-breakdown SOI folded gate-insulated tunneling bipolar transistor, that is, the device is in an on state.

The anti-breakdown SOI folded gate insulated tunneling bipolar transistor prevents forward and reverse breakdown of the device through the breakdown protection region 12 . Taking an N-type device as an example, when the collector 10 is forward-biased relative to the emitter 9, the collector junction composed of the folded conductive layer 6, the base region 4, the breakdown protection region 12 and the collector region 5 is in a reverse-biased state , the breakdown protection zone 12 located between the base region 4 and the collector region 5 has an anti-breakdown protection effect on the reverse-biased collector junction, so it can significantly improve the forward withstand voltage capability of the device; when the collector electrode 10 is relative to the emitter When the pole 9 is reverse-biased, the emitter junction composed of the folded conductive layer 6, the base region 4, the breakdown protection region 12 and the emission region 3 is in a reverse-biased state, and the breakdown protection region between the base region 4 and the emission region 3 12 It has anti-breakdown protection for the reverse-biased emitter junction, so it can significantly improve the reverse withstand voltage capability of the device;

The anti-breakdown SOI folded gate insulated tunneling bipolar transistor has an insulating tunneling structure on both sides and the upper surface of the base region 4. Under the control of the folded gate electrode 8, the insulating tunneling effect occurs simultaneously on both sides of the base region. side and upper surface, thus greatly increasing the generation rate of tunneling current.

The anti-breakdown SOI folded gate insulation tunneling bipolar transistor uses the extremely sensitive relationship between the impedance of the folded tunneling insulating layer 7 and the electric field strength in the tunneling insulating layer, and selects an appropriate tunnel insulating layer 7 for the folded tunneling insulating layer 7. material, and by properly adjusting the sidewall height, sidewall thickness, and top thickness of the folded tunneling insulating layer 7, the folded tunneling insulating layer 7 can realize a high resistance state and a low The conversion between resistance states greatly improves the switching characteristics of the device.

Anti-breakdown SOI folded gate insulation tunneling bipolar transistor, the gate insulation tunneling current flows through the folded conductive layer 6 to the base region 4, and passes through the emitter region 3 for signal enhancement, and ordinary TFETs only use a small amount of tunneling current between semiconductor bands Compared with the conduction current of the device, it has better forward current conduction characteristics. Based on the above reasons, compared with ordinary TFETs devices, the anti-breakdown SOI folded gate insulation tunneling bipolar transistor can achieve higher forward conduction Pass current.

The specific manufacturing process steps of the anti-breakdown SOI folded gate insulated tunneling bipolar transistor array on the SOI wafer proposed by the present invention are as follows:

Step 1, as shown in Figure 9 to Figure 10, provide an SOI wafer, the bottom of the SOI wafer is the single crystal silicon substrate 1 of the SOI wafer, and the middle of the SOI wafer is the wafer insulating layer 2, through ion implantation Or diffusion process, doping the single crystal silicon thin film above the SOI wafer to preliminarily form the base region 4 .

Step 2, as shown in Fig. 11 to Fig. 12, doping the single crystal silicon thin film above the SOI wafer again by ion implantation or diffusion process, and forming the same step 1 on both sides of the base region 4 formed in step 1. A heavily doped region with the opposite impurity type and a concentration not lower than 10 ¹⁹ per cubic centimeter, the heavily doped region is used to further form the emitter region 3 and the collector region 5, and the gap between the heavily doped region and the base region An undoped region remains, which serves to form the breakdown protection region 12 .

Step 3, as shown in Figure 13 to Figure 14, form a cuboid-shaped single crystal silicon island array on the provided SOI wafer through photolithography and etching processes, so that each unit is sequentially arranged with emission regions 3, breakdown The protection area 12 , the base area 4 , the breakdown protection area 12 and the collector area 5 .

Step 4, as shown in Figures 15 to 16, after depositing an insulating medium on the wafer, planarize the surface to expose the emitter region 3, the base region 4, the collector region 5 and the breakdown protection region 12, and initially form a blocking insulating layer 11.

Step five, as shown in Figure 17 to Figure 18, further form a cuboid-shaped single crystal silicon island array on the provided SOI wafer through photolithography and etching processes, so that each single crystal silicon island formed in step three Divided into multiple independent units.

Step 6. As shown in FIG. 19 to FIG. 20 , deposit an insulating medium on the wafer, so that the part etched in step 5 is fully filled, and planarize the surface to expose the emitter region 3, the base region 4, and the collector region. The electrical region 5 and the breakdown protection region 12 further form a blocking insulating layer 11 .

Step 7. As shown in FIG. 21 to FIG. 22 , the blocking insulating layer 11 on both sides of the base region 4 of each unit on the wafer surface is etched to expose the wafer insulating layer 2 through an etching process.

Step 8. As shown in FIGS. 23 to 25 , deposit metal or heavily doped polysilicon with the same impurity type as the base region 4 on the wafer, so that the blocking insulating layer 11 etched in step 7 is completely covered. Filling, planarizing the surface and then etching away the part other than the folded conductive layer 6 through an etching process, exposing the emitter region 3, the collector region 5, the blocking insulating layer 11 and the base region 4 adjacent to the emitter region 3 and the collector At both ends of the region 5, folded conductive layers 6 are formed.

Step 9, as shown in Figure 26 to Figure 28, deposit an insulating medium on the wafer, then planarize the surface to expose the upper surface of the folded conductive layer 6, and then perform tunneling on both sides of the base region through an etching process The side of the insulating layer 7 away from the base region is etched to the blocking insulating layer 11 to expose the wafer insulating layer 2 .

Step 10. As shown in FIG. 29 to FIG. 31 , deposit a tunneling insulating layer dielectric on the wafer, so that the blocking insulating layer 11 etched in step 9 is completely filled, and then pass the etching process after planarizing the surface Parts other than the folded tunneling insulating layer 7 are etched away to expose the blocking insulating layer 11 to form the folded tunneling insulating layer 7 .

Step eleven, as shown in FIG. 32 to FIG. 34 , respectively etch the blocking insulating layer 11 on the side of the folded tunneling insulating layer 7 on both sides of the base region away from the base region to expose the wafer insulating layer 2 .

Step 12, as shown in Figure 35 to Figure 37, deposit metal or heavily doped polysilicon on the wafer, so that the blocking insulating layer 11 etched in step 11 is completely filled; after planarizing the surface The portion other than the folded gate electrode 8 is etched away by an etching process to expose the blocking insulating layer 11 , and the folded gate electrode 8 is preliminarily formed.

Step 13, as shown in FIG. 38 to FIG. 40 , deposit an insulating medium on the wafer, and planarize the surface until the upper surface of the folded gate electrode 8 formed in step 12 is exposed.

Step 14, as shown in Figure 41 to Figure 43, deposit metal or heavily doped polysilicon on the wafer, and etch away the part other than the part used to form the wiring between the device units, and further form the folded gate electrode 8.

Step fifteen, as shown in FIG. 44 to FIG. 46 , deposit an insulating medium on the wafer to planarize the surface.

Step 16. As shown in FIG. 47 to FIG. 48 , the blocking insulating layer 11 above the emitter region 3 and the collector region 5 is etched away by an etching process to form through holes for the emitter 9 and the collector 10 .

Step seventeen, as shown in Figure 49 to Figure 50, deposit metal on the wafer, so that the through holes of the emitter 9 and the collector 10 formed in step sixteen are completely filled, and form the emitter through the etching process pole 9 and collector 10.

Claims (9)

1. anti-breakdown SOI folds gate insulation tunnelling bipolar transistor, it is characterized in that: adopt the SOI wafer comprising monocrystalline substrate (1) and wafer insulating barrier (2) as the substrate of generating device; Emitter region (3), base (4), collector region (5) and breakdown protection district (12) are positioned at the top of the wafer insulating barrier (2) of SOI wafer, base (4) and breakdown protection district (12) are positioned between emitter region (3) and collector region (5), and breakdown protection district (12) are positioned at the both sides of base (4); Emitter (9) is positioned at the top of emitter region (3); Collector electrode (10) is positioned at the top of collector region (5); Folding conductive layer (6) forms three bread to the upper surface of base (4) and both sides and encloses; Folding tunneling insulation layer (7) forms three bread to the upper surface of folding conductive layer (6) and both sides and encloses; Folding gate electrode (8) forms three bread to the upper surface of folding tunneling insulation layer (7) and both sides and encloses; Barrier insulating layer (11) is dielectric.

2. anti-breakdown SOI according to claim 1 folds gate insulation tunnelling bipolar transistor, it is characterized in that: the impurity concentration of breakdown protection district (12) is lower than 10 ¹⁶every cubic centimetre.

3. anti-breakdown SOI according to claim 1 folds gate insulation tunnelling bipolar transistor, it is characterized in that: the impurity concentration of base (4) is not less than 10 ¹⁷every cubic centimetre, (4) both sides, base and upper surface contact with folding conductive layer (6) and form ohmic contact.

4. anti-breakdown SOI according to claim 1 folds gate insulation tunnelling bipolar transistor, it is characterized in that: between emitter region (3) and base (4), between collector region (5) and base (4), there is opposite impurity type, and form ohmic contact between emitter region (3) and emitter (9), form ohmic contact between collector region (3) and collector electrode (10).

5. anti-breakdown SOI according to claim 1 folds gate insulation tunnelling bipolar transistor, it is characterized in that: folding conductive layer (6) is metal material or same base (4) have identical dopant type and doping content is greater than 10 ¹⁹the semi-conducting material of every cubic centimetre.

6. anti-breakdown SOI according to claim 1 folds gate insulation tunnelling bipolar transistor, it is characterized in that: folding tunneling insulation layer (7) is the insulation material layer for generation of tunnelling current.

7. anti-breakdown SOI according to claim 1 folds gate insulation tunnelling bipolar transistor, it is characterized in that: folding conductive layer (6), folding tunneling insulation layer (7) and folding gate electrode (8) are all mutually isolated with emitter region (3), emitter (9), collector region (5) and collector electrode (10) by barrier insulating layer (11); Isolated by barrier insulating layer (11) between adjacent emitter region (3) and collector region (5), isolated by barrier insulating layer (11) between adjacent emitter (9) and collector electrode (10).

8. anti-breakdown SOI according to claim 1 folds gate insulation tunnelling bipolar transistor, it is characterized in that: folding conductive layer (6), folding tunneling insulation layer (7) and folding gate electrode (8) constitute the tunnelling base stage that anti-breakdown SOI folds gate insulation tunnelling bipolar transistor jointly, when there is tunnelling in folding tunneling insulation layer (7) under the control of folding gate electrode (8), electric current flow to folding conductive layer (6) from folding gate electrode (8) through folding tunneling insulation layer (7), and is base (4) power supply.

9. anti-breakdown SOI as claimed in claim 1 folds the unit of gate insulation tunnelling bipolar transistor and a manufacture method for array thereof, it is characterized in that: this processing step is as follows:

Step one, provide a SOI wafer, the below of SOI wafer is the monocrystalline substrate (1) of SOI wafer, the centre of SOI wafer is wafer insulating barrier (2), by ion implantation or diffusion technology, monocrystalline silicon thin film above SOI wafer is adulterated, begins to take shape base (4);

Step 2, again by ion implantation or diffusion technology, the monocrystalline silicon thin film above SOI wafer to be adulterated, form contrary with the dopant type in step one, concentration in the both sides of the base that step one is formed (4) and be not less than 10 ¹⁹the heavily doped region of every cubic centimetre, this heavily doped region is used for forming emitter region (3) and collector region (5) further, leave the region of undoped between this heavily doped region and base, the region of this undoped is for the formation of breakdown protection district (12);

Step 3, in provided SOI wafer, form the queue of rectangular-shaped monocrystalline silicon isolated island by photoetching, etching technics, make in each unit, to be arranged in sequence with emitter region (3), breakdown protection district (12), base (4), breakdown protection district (12) and collector region (5);

Step 4, above wafer, after deposit dielectric, planarized surface, to exposing emitter region (3), base (4), collector region (5) and breakdown protection district (12), begins to take shape barrier insulating layer (11);

Step 5, in provided SOI wafer, form rectangular-shaped monocrystalline silicon isolated island array further by photoetching, etching technics, each monocrystalline silicon isolated island queue that step 3 is formed is divided into multiple unit independent of each other;

Step 6, above wafer deposit dielectric, the part be etched away in step 5 is fully filled, and planarized surface is to exposing emitter region (3), base (4), collector region (5) and breakdown protection district (12), forms barrier insulating layer (11) further;

Step 7, by etching technics, the barrier insulating layer (11) of base (4) both sides of each unit of crystal column surface is etched to and exposes wafer insulating barrier (2);

Step 8, above wafer depositing metal or there is the heavily doped polysilicon with base (4) identical dopant type, the barrier insulating layer (11) be etched away in step 7 is filled completely, the part for generating beyond folding conductive layer (6) is etched away by etching technics again after planarized surface, expose the two ends of emitter region (3), collector region (5), the contiguous emitter region (3) in barrier insulating layer (11) and base (4), collector region (5), form folding conductive layer (6);

Step 9, above wafer deposit dielectric, again by surface planarisation to the upper surface exposing folding conductive layer (6), then in the side away from base of the tunneling insulation layer of both sides, base (7), barrier insulating layer (11) is etched to respectively by etching technics and exposes wafer insulating barrier (2);

Step 10, above wafer deposit tunneling insulation layer medium, the barrier insulating layer (11) be etched away in step 9 is filled completely, etched away by etching technics again after planarized surface and to exposing barrier insulating layer (11), form folding tunneling insulation layer (7) for generating part beyond folding tunneling insulation layer (7);

The side away from base of step 11, folding tunneling insulation layer (7) respectively in both sides, base is etched to barrier insulating layer (11) exposes wafer insulating barrier (2);

Step 12, above wafer depositing metal or heavily doped polysilicon, the barrier insulating layer (11) be etched away in step 11 is completely filled; Etched away by etching technics again after planarized surface and to exposing barrier insulating layer (11), begin to take shape folding gate electrode (8) for part beyond generating folding stacked gate electrode (8);

Step 13, above wafer deposit dielectric, then by surface planarisation to the upper surface exposing the folding gate electrode (8) formed in the middle of step 12;

Step 14, above wafer depositing metal or heavily doped polysilicon, and etch away the part beyond for the formation of trace portions between device cell, form folding gate electrode (8) further;

Step 15, above wafer deposit dielectric, by surface planarisation;

Step 10 six, etched away the barrier insulating layer (11) of the top being positioned at emitter region (3) and collector region (5) by etching technics, form the through hole of emitter (9) and collector electrode (10);

Step 10 seven, above wafer depositing metal, the through hole of emitter (9) and the collector electrode (10) formed in step 10 six is completely filled, and forms emitter (9) and collector electrode (10) by etching technics.