CN104380274B - Apparatus and method for optimized link training and management - Google Patents

Abstract

In one embodiment, an aggregate protocol stack can be used to unify communications from a first communication protocol to a second communication protocol to provide data transfer across a physical interconnect. This stack can be incorporated into an apparatus including a protocol stack for a first communication protocol including a transaction and link layer and a physical (PHY) unit coupled to the protocol stack to provide communication between the apparatus and a device coupled to the apparatus via a physical link. This PHY unit may include physical unit circuitry according to a second communication protocol. Other embodiments are described and claimed.

Description

Apparatus and method for optimized link training and management

technical field

Embodiments relate to interconnect technologies.

background

In order to provide communication between different devices within a system, some type of interconnection mechanism is used. A wide variety of such interconnections are possible, depending on the system implementation. Often times in order for two devices to communicate with each other, they share a common communication protocol

A typical communication protocol for inter-device communication within a computer system is Peripheral Component Express Interconnect based on a link based on the PCI Express™ Specification Base Specification Version 3.0 (published November 18, 2010) (hereinafter referred to as the ^PCIeTM Specification). PCI Express ^TM (PCIe ^TM ) communication protocol. This communication protocol is an instance of a load/store input/output (IO) interconnect system. The communication between the devices is usually performed serially at very high speed according to this protocol. When the PCIe ^™ communication protocol was developed in the context of desktop computers, various parameters regarding this protocol were developed for the purpose of achieving maximum performance without regard to power efficiency. As a result, many of its features cannot be reduced to lower power solutions that can be incorporated into mobile systems.

In addition to these power issues with conventional load/store communication protocols, existing link management schemes are usually very complex and involve a large number of states, resulting in lengthy procedures for performing transitions between states. This is due in part to existing link management mechanisms, which were developed to accommodate a variety of different form factor requirements such as connectors, merging of different systems, and the like. One such example is link management according to the PCIe ^™ communication protocol.

Brief description of the drawings

FIG. 1 is a high-level block diagram of a protocol stack for a communication protocol according to an embodiment of the present invention.

FIG. 2 is a block diagram of a system on chip (SoC) according to an embodiment of the present invention.

Fig. 3 is a block diagram of a physical unit according to another embodiment of the present invention.

Figure 4 is a block diagram showing further details of a protocol stack according to an embodiment of the present invention.

Figure 5 is a state diagram for a link training state machine, which can be part of a link manager according to an embodiment of the invention.

FIG. 6 is a flowchart of various states for a sideband mechanism according to an embodiment of the present invention.

Fig. 7 is a flowchart of a method according to an embodiment of the present invention.

FIG. 8 is a block diagram of components present in a computer system according to an embodiment of the present invention.

9 is a block diagram of an example system with which an embodiment can be used.

detailed description

Embodiments may provide input/output (IO) interconnect technology that has a low power, load/store architecture and is particularly suitable for use in mobile devices including cellular phones such as smartphones, tablet computers, e-readers, Ultrabooks™, etc. used in the device.

In various embodiments, a protocol stack for a given communication protocol can be used with physical units of a different communication protocol or at least one physical (PHY) unit different from the physical unit used for the given communication protocol. A physical unit includes both a logical layer and a physical or electrical layer that provides the actual, physical communication of information signals over an interconnect, such as a link linking two separate semiconductor dies. There may be two semiconductor dies within a single integrated circuit (IC) package or separate packages coupled eg via circuit board routing, traces, or the like. Additionally, the physical unit is capable of performing framing/deframing of packets, performing link training and initialization, and processing packets for reception from or delivery onto the physical interconnect.

Although different implementations are possible, in one embodiment the protocol stack may have a conventional personal computer (PC) based communication protocol (such as the PCI Express™ Specification Base Specification Version 3.0 (Nov. 18, 2010) Published) (hereinafter referred to as the PCIe ^TM Specification) Peripheral Component Interconnect Express (PCI) Express ^TM (PCIe ^TM ) Communication Protocol), a further version of the Application Protocol Extensions, or another such protocol, while the physical unit does not According to the PCIe ^TM communication protocol. For the purpose of achieving low power operation, this physical unit can be specially designed to allow a substantially unchanged protocol stack on PCIe ^™ to be merged with this low power physical circuit. In this way, the broad legacy base of the PCIe ^™ communications protocol can be leveraged for ease of incorporation into portable and other non-PC based form factors that operate at low power. While the scope of the invention is not limited thereto, in one embodiment, this physical unit may be defined by a mobile platform, such as according to the Mobile Industry Processor Interface (MIPI) Alliance (which is a group that sets standards for mobile computing devices). M-PHY Specification Version 1.00.00 - physical unit of so-called M-PHY) adaptation on February 8, 2011 (MIPI Board approved on April 28, 2011) (hereinafter MIPI Specification). However, other low power physical units (such as according to other low power specifications such as for coupling together individual dies within a multi-chip package), or custom low power solutions can be used. As used herein, the term "low power" means at a lower power consumption level than conventional PC systems, and it can be applied to a wide variety of mobile and portable devices. As an example, "low power" may be a physical unit that consumes less power than a conventional PCIe ^™ physical unit.

In this way, by aggregating legacy PCIe ^™ protocol stacks with different types of physical units, a large number of reused legacy components developed for PCIe ^™ can be used to incorporate into mobile or other portable or low power platforms.

Embodiments may also take advantage of the recognition that existing load/store IO technologies, especially PCIe ^™ , are designed to achieve maximum performance where power efficiency is not a major concern, and thus not scaled down to low power applications. By combining portions of a conventional load/store protocol stack with low power designed physical units, embodiments can preserve the performance advantages of PCIe ^™ while optimizing in terms of power at the device and platform level.

As such, embodiments may be software compatible with the ubiquitous PCIe ^™ architecture with a large legacy base. Furthermore, embodiments may also enable direct PHY reuse of mobile design PHYs, such as M-PHY. In this way, low active and idle power can be achieved with efficient power/bits delivered and what is friendly as Electromagnetic Interface/Radio Frequency Interface (EMI/RFI) since the PHY can do so without interfering with the associated radio (because of the clock rate used for the PHY A typical radio solution operates at the clock rate of the conventional radio frequency (eg, 1.8, 1.9, 2.4 gigahertz (GHz)) or other such radio frequency on which it operates.

Embodiments may further provide architectural improvements enabling optimized link training and management mechanisms (LTSSM); optimized flow control and retry buffering and management mechanisms; architectural protocols for changing link operating modes; fast hardware support for device state preservation and recovery; and a unified sideband mechanism for link management with optional in-band support.

In various embodiments, the PCIe ^™ transaction and data link layer can be implemented as part of the protocol stack with limited modifications to account for different link speeds and asymmetric links. In addition, modified link training and management may be provided to include support for multi-lane communication, asymmetric link configuration, sideband unification, and dynamic bandwidth scalability. Embodiments may further provide support for bridging between existing PCIe ^™ -based and non-PCIe ^™ -based logic and circuits such as M-PHY logic and circuits.

This layered approach enables existing software stacks (eg, operating system (OS), hypervisor, and drivers) to run seamlessly on different physical layers. Impact on the data link and transaction layers is minimized and may include updating related timers to update acknowledgment frequency, replay timers, etc.

Accordingly, embodiments can limit some of the flexibility provided in PCIe ^™ systems, as this flexibility can in some cases create certain complexities both within PCIe ^™ systems and others. This is true because both protocols offer great flexibility in enabling plug-and-play capabilities. Rather, embodiments enable custom solutions that minimize the amount of design flexibility because, when incorporated into a given system, such as a system-on-chip (SoC) interconnected with another integrated circuit (IC), existing Known and fixed configuration. As is known in achieving precise configurations that exist, when both the SoC and the connected devices are attached within the platform, for example soldered to the circuit board of the system, these devices do not require plug and play capability and thus may The greater flexibility inherent in PCIe ^™ or other PC-based communication protocols to enable seamless incorporation of different devices into a plug-and-play capable system is not required.

As an example, the SoC can act as a root complex implemented in a first IC and is coupled to a second IC, which can be a radio solution, which can include one or more of a plurality of wireless communication devices devices. Such devices can range from low-power short-range communication systems such as according to the Bluetooth ^™ specification, local area wireless communication such as the so-called WiFi ^™ system according to the given Institute of Electrical and Electronics Engineering (IEEE) 802.11 standard, to such as the given High-power wireless systems with cellular communication protocols such as 3G or 4G communication protocols.

Referring now to FIG. 1 , shown is a high level block diagram of a protocol stack for a communication protocol in accordance with an embodiment of the present invention. As shown in FIG. 1 , stack 100 may be a combination of software, firmware, and hardware within a semiconductor component, such as an IC, for providing processing of data communications between the semiconductor device and another device coupled thereto. In the embodiment of FIG. 1, a high-level view is shown beginning with high-level software 110, which may be various types of software executing on a given platform. Such high-level software may include operating system (OS) software, firmware, application software, and the like. Data to be communicated via interconnect 140 , which may be a given physical interconnect coupling the semiconductor device with another component, can be passed through layers of a protocol stack, generally shown within FIG. 1 . As seen, portions of this protocol stack may be part of a conventional PCIe ^™ stack 120 and may include a transaction layer 125 and a data link layer 128 . Typically, the transaction layer 125 is used to generate transaction layer packets (TLPs), which can be request or response based packets separated by time, allowing the link to carry other traffic while the target device collects data for the response . The transaction layer further handles credit-based flow control. Thus, the transaction layer 125 provides the interface between the device's processing circuitry and the interconnection fabric, such as the data link layer and the physical layer. In this regard, the main responsibilities of the transaction layer are the assembly and disassembly of data packets (ie, Transaction Layer Packets (TLPs)) and handling credit-based flow control.

In turn, the data link layer 128 can sequence the TLPs generated by the transaction layer and ensure reliable delivery of TLPs between two endpoints (including handling error checking) and reply processing. Thus, the link layer 128 acts as an intermediate stage between the transaction layer and the physical layer and provides a reliable mechanism for exchanging TLPs between the two components over the link. One side of the link layer receives the TLP assembled by the transaction layer, applies an identifier, calculates and applies an error detection code (such as a cycle recovery code (CRC)), and submits the modified TLP to the physical layer for use in Transmitted across physical links to external devices.

After processing in the data link layer 128 , the data packet can be passed to the PHY unit 130 . In general, PHY unit 130 may include a low power PHY 134, which may include both logical layers and physical (including electrical) sublayers. In one embodiment, the physical layer, represented by PHY unit 130, physically transmits data packets to external devices. The physical layer includes a transmit section that prepares outgoing information for transmission and a receiver section that identifies and prepares received information before passing it on to the link layer. Symbols to be serialized and transmitted to an external device are supplied to the transmitter. The receiver is supplied with serialized symbols from an external device, and the receiver transforms the received signal into a bit stream. The bitstream is deserialized and supplied to logical sub-blocks.

In one embodiment, low power PHY 134 (which can be a given low power PHY specially developed or adapted by another PHY such as M-PHY) may provide processing of packed data for use along interconnect 140 send. As further seen in FIG. 1 , a link training and management layer 132 (also referred to herein as a link manager) may also reside within the PHY unit 130 . In various embodiments, Link Manager 132 may include specific logic that may be implemented in accordance with another communications protocol, such as the PCIe ^™ protocol, and proprietary processing of interfaces between conventional and physical PHYs 134 with different protocols, such as the PCIe ^™ protocol stack described above. logic.

In the embodiment of FIG. 1 , interconnect 140 can be implemented as a differential wire pair, which can be two pairs of unidirectional wires. In some implementations, multiple sets of differential pairs can be used to increase bandwidth. It should be noted that according to the PCIe ^TM communication protocol, the number of differential pairs in each direction is required to be the same. However, according to various embodiments, different numbers of pairs can be provided in each direction, which allows for more efficient and lower power operation. This entire aggregated stack and link 140 may be referred to as a Mobile Express PCIe ^™ interconnect or link. While shown at this high level in the embodiment of FIG. 1 , it is to be understood that the scope of the present invention is not so limited. That is, it is to be understood that the view shown in FIG. 1 is only about the protocol stack from the transaction layer through the physical layer and high-level software, and does not show various other circuits of the SoC or other semiconductor devices including this stack.

Referring now to FIG. 2 , a block diagram of a SoC according to an embodiment of the present invention is shown. As shown in FIG. 2, SoC 200 can be any type of platform for implementation in various types of SoCs ranging from devices such as smart phones, personal digital assistants (PDAs), tablet computers, notebooks, ^UltrabooksTM , etc. Relatively small low-power portable devices to more advanced SoCs capable of being implemented in high-level systems.

As seen in FIG. 2 , SoC 200 may include one or more cores 210 ₀ - 210 _n . Thus in various embodiments, there may be a multi-core SoC, the cores may all be homogeneous cores of a given architecture, such as in-order or out-of-order processors. Or there can be heterogeneous cores, eg some relatively small low power cores eg with an in-order architecture; there can be additional cores that can have larger and more complex architectures eg an out-of-order architecture. The protocol stack enables data communication between one or more of these cores and other components of the system. As seen, this stack can include software 215, which may be higher level software (such as OS, firmware) and application level software executing on one or more cores. In addition, the protocol stack includes a transaction layer 220 and a data link layer 230 . In various embodiments, these transaction and data link layers may have a given communication protocol such as the PCIe ^™ protocol. Of course, layers of a different protocol stack, such as according to the Universal Serial Bus (USB) protocol stack, may be present in other embodiments. Also, in some embodiments, the low power PHY circuits described herein can be multiplexed with existing replacement protocol stacks.

Still referring to FIG. 2, this protocol stack can then be coupled to a physical unit 240, which can include multiple physical units capable of providing communication via multiple interconnects. In one embodiment, the first physical unit 250 may be a low power PHY unit, which in one embodiment may correspond to an M-PHY according to the MIPI specification, for providing communication via the main interconnect 280 . Additionally, a sideband (SB) PHY unit 244 may be present. In the illustrated embodiment, this sideband PHY unit may provide communications via sideband interconnect 270, which may be configured for, for example, at a slower data rate than main interconnect 280 coupled to first PHY 250. Uniform sidebands that provide some sideband information. In some embodiments, layers of the protocol stack can have separate sidebands coupled to this SB PHY 244 for communication along this sideband interconnect.

Additionally, PHY unit 240 may further include an SB link manager 242 operable to control SB PHY 244 . In addition, a link training and state manager 245 may be present and can be used to adapt the protocol stack with the first communication protocol to the first PHY 250 with the second communication protocol, as well as provide support for the first PHY 250 and the interconnect 280 overall control.

As further seen, various components may be present in the first PHY 250 . More specifically, there may be transmitter and receiver circuits (ie TX253 and RX254). In general, such circuitry may be used to perform serialization operations, deserialization operations, and transmit and receive data via the main interconnect 280 . A save state manager 251 may be present and may be used to save configuration and other state information about the first PHY 250 when it is in a low power state. Furthermore, there can be an encoder 252 for performing line encoding eg according to the 8b/10b protocol.

As further seen in FIG. 2 , there may be a mechanical interface 258 . This mechanical interface 258 may be a given interconnect for providing communication from the root complex 200 , and more specifically to/from the first PHY 250 via the primary interconnect 280 . In various embodiments, this mechanical connection can utilize pins of a semiconductor device such as a ball grid array (BGA) or other surface mount, or via via connection plating.

In addition to these primary communication mechanisms, additional communication interfaces may utilize Low Power Serial (LPS) PHY unit 255 via The split stack is coupled between the core 210 and one or more off-chip devices 260a-c, which can be, for example, sensors, accelerometers, temperature sensors, global positioning system (GPS) circuits, compass circuits, touch screen circuits, Various low data rate peripherals such as keyboard circuits, mouse circuits, etc.

Note that in various embodiments, either sideband interconnect 270 or main interconnect 280 can be coupled between SoC 200 and another semiconductor component (eg another IC such as a multi-band radio solution).

Again, while the illustration of Figure 2 is at a relatively high level, variations are possible. For example, multiple low power PHYs may be provided to enable higher rate data communication, eg, via multiple channels, where each channel is associated with a separate PHY. Referring now to FIG. 3 , a block diagram of a physical unit according to another embodiment of the present invention is shown. As shown in FIG. 3 , the physical unit 300 includes a link training and state manager 310 . This state manager can be as described above and can be a logical set for enabling a protocol stack with a first communication protocol to interface with a physical unit with a second (eg different) communication protocol.

As further seen in FIG. 3, link training and state manager 310 may communicate with a plurality of M- _{PHYs 3200-320n} . By providing more than one such PHY, higher rate data communication is enabled. Note that while each of the M-PHYs shown in FIG. 3 may include some amount of logic for enabling their individual independent communications to occur, the overall control over the communications of these different M-PHYs may be via link training and state Manager 310. Also, it is to be understood that while multiple M-PHY units are shown in FIG. 3, in other embodiments there can be another type of multiple PHY units and that additional heterogeneous multiple PHY units can be provided. Note that each M-PHY unit can be used as part of a unique logical link, or in a group where a group is associated with a single logical link. Each device may typically consume a single logical link, but in some embodiments a single physical device may consume multiple logical links, for example to provide dedicated link resources for different functions of a multi-function component.

Referring now to FIG. 4 , shown is a block diagram showing further details of a protocol stack in accordance with an embodiment of the present invention. As shown in FIG. 4 , stack 400 includes various layers including: transaction layer 410 , data link layer 420 , and physical layer 430 . As noted above, these different layers can be configured using the conventional transaction and data link portions of the PCIe ^™ protocol stack, or modified versions of such stacks, to accommodate the integration of the layers with the first communication protocol with the physical layer with another communication protocol. Interaction between layers, the physical layer in the embodiment of FIG. 4 may be M-PHY according to the MIPI specification.

As seen in FIG. 4 , with regard to the direction of transmission of information transmitted from the protocol stack 400 , in the transport packet assembler 412 that typically combines the control and data paths at the transaction layer to form a TLP it receives data from, for example, other circuits of the SoC such as the core or other processing logic) to the incoming information of the protocol stack. After being assembled into a transport packet (a transport packet can be a packet with, for example, 1 to 4096 bytes (or a smaller maximum allowed size, such as 128 or 256) in various embodiments), the assembled The packet is provided to flow controller 414, which determines whether sufficient flow control credits are available based on the required number of next TLP(s) queued for transmission, and controls injection of the packet into the data link Road layer 420. As seen more specifically, these injected packets are provided to an error detector and sequencer 422, which in one embodiment may generate a TLP sequence number and LCRC. As further seen, the data link layer 420 further includes a transport message mechanism 426 which in turn generates a DLLP for link management functions and is coupled to a data link transport controller 425 which is used for flow control and data link integrity (ACK/NAK) mechanisms; note that this can be subdivided such that different logic blocks are used to implement these functions.

As further seen, the processed packets are provided to a retry buffer 424 which holds a copy of each TLP until acknowledged by a component on the other side of the link, noting that in practice this may Utilization buffering is implemented further up the stack (inside or above the assembler 412 ) and they can be stored in corresponding entries until selected for transmission to the physical layer 430 via the data/message selector 428 . In general, the transaction and data link layers described above may operate according to conventional PCIe ^™ protocol stack circuitry, with some modifications described further below.

Conversely with respect to the physical layer 430, much more modification of certain logical components of this layer (as modified for example according to the PCIe ^™ protocol stack) can take place and serve to provide access to the actual physical part of the physical unit with another communication protocol Interface. As can be seen, incoming data packets can be applied to a frame generator 432, which adds physical layer frame symbols and generates frames for the data packets, and provides them to a bandwidth/location mapper 434, which shifts the data path bytes in to generate the required alignment for external transmissions to adjust the data path width if necessary, and is then coupled to a trainer and hop sequencer 436 which can be used to perform link training and hop sequencing. As seen, frame generator 432, trainer/sequencer 436, and data/sequence selector 438 may all be coupled to physical layer transmit controller 435, which is the transceiver portion of the LTSSM and associated logic . Block 436 is logic for generating physical layer transmissions such as training sets (TS) and hop ordered sets. In this way, framed packets can be selected and provided to physical circuitry to perform encoding, serialization, and drive serialized signals corresponding to the processed packets onto the physical interconnect. In one embodiment, the mapping of symbol differences between different communication protocols may be performed in the frame generator 432 .

As can be seen, this physical interconnect can be provided with multiple individual channels or lanes. In the illustrated embodiment, each physical channel or channel can include its own independent PHY unit transmission circuitry 445 ₀ - 445 _j , each of which may be part of an M-PHY unit according to the MIPI specification in one embodiment . As described herein, unlike PCIe ^™ where the number of transmitters and receivers is matched, there may be a different number of transmitters and receivers. Thus as seen, each transmit circuit 445 can include an encoder to encode symbols according to 8b/10b encoding, a serializer to serialize the encoded symbols, and a driver to drive the signal onto the physical interconnect. driver. As further seen, each lane or channel may be associated with a logic unit 440 ₀ - 440 _j , which may be a logic circuit according to the MIPI specification for M-PHY, for managing physical communication via the corresponding lane accordingly.

Note that these multiple channels can be configured to operate at different rates, and embodiments may include different numbers of such channels. In addition, it is possible to have different numbers of lanes and lane speeds in the transmit and receive directions. Thus, while a given logic unit 440 controls the operation of a corresponding lane of the PHY 445, it is understood that a physical layer transport controller 435 may be used to control the overall information transport via the physical interconnect. Note that in some cases some very basic functions are performed by different logic associated with each channel; for situations where channels can be assigned to more than a single link, multiple LTSSM instances can be provided; for training Link, there is a single LTSSM in each component controlling both the transceiver and receiver sides. Such overall control can include power control, link speed control, link width control, initialization, and the like.

Still referring to FIG. 4 , incoming information received via the physical interconnect may similarly pass through the physical layer 430 , the data link layer 420 , and the transaction layer 410 via the reception mechanisms of these layers. In the embodiment shown in FIG. 4 , each PHY unit may further include receive circuits, namely receive circuits 455 _{0 -455 k} , which in the illustrated embodiment _are capable of addressing physical link of each channel exists. Note that in this embodiment, the numbers of receiver circuits 455 and transmitter circuits 445 are different. As can be seen, this physical circuit can include an input buffer to receive incoming information, a deserializer to deserialize this information, and a decoder that can be used to decode symbols transmitted in 8b/10b encoding. As further seen, each lane or channel may be associated with a logic unit _4500-450k , _which may be a logic circuit according to a given specification (e.g. MIPI specification for _M -PHY ₎ , for thus managing the physical communication via the corresponding channel.

The decoded symbols may then be provided to the logical portion of the physical layer 430, which as seen may include an elastic buffer 460 that accommodates clock differences between this component and another component on the link; Note that in various embodiments its location may be shifted eg below the 8b/10b decoder, or combined with the lane deskew buffer, and store incoming decoded symbols. This information can in turn be provided to a width/position mapper 462, from there to a lane deskew buffer 464 which performs deskew across multiple lanes, and for multi-lane cases the buffer 464 is able to handle inter-lane signal skew difference to realign the bytes. In turn, the de-skewed information may be provided to frame processor 466, which may eliminate the frames present in the incoming information. As seen, physical layer receive controller 465 may couple to and control elastic buffer 460 , mapper 462 , deskew buffer 464 and frame processor 466 .

Still referring to FIG. 4 , the recovered data packets may be provided to a receive message mechanism 478 and error detector, sequence checker and link level retry (LLR) requester 475 . This circuitry can perform error correction checks on incoming packets, such as by performing CRC checksum operations, performing ordering checks, and requesting link-level retries for erroneously received packets. Both receive message mechanism 478 and error detector/requester 475 may be under the control of data link receive controller 480 .

Still referring to FIG. 4, packets processed in unit 475 may thus be provided to transaction layer 410, and more specifically to flow controller 485, which performs flow control on these packets to provide them to packet interpreter 495. . Packet interpreter 495 performs interpretation of the packets and forwards them to a selected destination, such as a given core or other logic of the receiver. While shown at this high level in the embodiment of FIG. 4, it is to be understood that the scope of the present invention is not so limited.

Note that the PHY 440 can use the same 8b/10b encoding supported by PCIe ^™ for transport. The 8b/10b encoding scheme provides special symbols other than the data symbols used to represent characters. These special symbols can be used for various link management mechanisms described in the physical layer chapter of the PCIe ^TM specification. The use of additional special symbols by M-PHY is described in the MIPI M-PHY specification. Embodiments may provide mapping between PCIe ^TM and MIPI M-PHY symbols.

Referring now to Table 1, an exemplary mapping of PCIe ^TM symbols to M-PHY symbols is shown, according to one embodiment of the present invention. Thus, this table shows the mapping of special symbols for the aggregated protocol stack according to one embodiment of the invention.

Table 1

The 8b/10b decoding rules are the same as defined for the PCIe ^™ specification. The only exception to the 8b/10b rule is when TAIL OF BURST is detected, which is a specific sequence that violates the 8b/10b rule. According to various embodiments, physical layer 430 is capable of providing notification to data link layer 420 of any errors encountered during TAIL OF BURST.

In one embodiment, the framing of symbols and application to lanes can be as defined in the PCIe ^™ specification, while data scrambling can be the same as defined in the PCIe ^™ specification. However, care is taken not to disturb the data symbols transmitted in the PREPARE phase of communication according to the MIPI specification.

With regard to link initialization and training, the link manager can provide configuration and initialization of links for channels that can include one or more lanes, support for normal data transfers, support for state transitions when recovering from link errors, as discussed above. Support and port restart from low power state.

To enable such operations, the following physical and link-related characteristics may be known in advance (e.g., prior to initialization): PHY parameters (including, for example, initial link speed and supported speeds; and initial link width and supported link speeds; road width).

In one embodiment, training may include various operations. Such operations may include initializing the link at the configured link speed and width, per-lane bit lock, per-lane symbol lock, lane polarity, and lane-to-lane deskew for multi-lane links. This way, training is able to discover channel polarity and perform adjustments accordingly. However, it should be noted that link training according to embodiments of the present invention may not include link data rate and width negotiation, link speed and width degradation. Instead, as described above, once the link is initialized, both entities know the initial link width and speed ahead of time, and thus can avoid the time and computational costs associated with negotiation.

PCIe ^TM ordered sets can be used for the following modifications: TS1 and TS2 ordered sets are used to facilitate IP reuse, but many fields of the training ordered sets are ignored. Also, fast training sequences are not used. Electrical Idle Ordered Sets (EIOS) may be reserved to facilitate IP reuse, as in Jump OS, but the frequency of Jump OS may be at a different speed than according to the PCIe ^TM specification. Note also that the dataflow ordered set and symbols can be the same as according to the PCIe ^™ specification.

The following events are transmitted to facilitate link training and management: (1) present, which can be used to indicate that there is an active PHY on the remote end of the link; and (2) configuration ready, which is triggered to indicate completion of PHY parameter configuration and The PHY is ready to operate with the configured profile. In one embodiment, the family information can be transmitted via a unified sideband signal according to an embodiment of the present invention.

For the purpose of controlling electrical idle conditions, the PHY has a TAIL OF BURST sequence to indicate that the transmitter is entering an electrical idle state. In one embodiment, the sideband channel may be used for signaling exit from electrical idle. Note that this instruction can be coupled with the PHY inhibition break mechanism. An OPENS sequence of symbols may be transmitted as EIOS to indicate entry into the electrical idle state.

In some embodiments, no fast training sequence (FTS) is defined. Instead, the PHY can use a specific physical layer sequence for exiting from a shutdown/sleep state to a burst state that can be used to address bit lock, symbol lock, and lane-to-lane deskew. A small number of FTSs can be defined as sequences of symbols for robustness. The start of an ordered set of data streams can be according to the PCIe ^™ specification, as in link error recovery.

Regarding the link data rate, in various embodiments, the initial data rate of the link initialization may be a predetermined data rate. A data rate change from this initial link speed can occur by going through a recovery state. Embodiments may support asymmetric link data rates, where a different data rate in the opposite direction is allowed.

In one embodiment, the supported link widths may be according to those in the PCIe ^™ specification. Additionally, as described above, because the link width is predetermined, embodiments may not support a protocol for negotiating link width, and thus link training may be simplified. Of course, embodiments may provide support for asymmetric link widths in the opposite direction. Meanwhile, the initial link width and initial data rate configured for each direction of the link may be known in advance before training starts.

Regarding the physical ports of the PHY unit, there is no requirement for xN ports to form xN (where N can be 32, 16, 12, 8, 4, 2, and 1) links as well as x1 link capabilities, and xN ports form N with 1 The ability to have arbitrary link widths between is optional. Examples of this behavior include x16 ports, which can only be configured as a unique link, but the width of the link can be configured as x12, x8, x4, x2 and the required width of x16 and x1. In this way, a designer seeking to implement a device using a protocol stack according to an embodiment of the present invention can connect ports between two different components in a manner that allows these components to meet the requirements described above. If ports between components are connected in a way that does not conform to their intended use as defined by the component's port description/datasheet, the behavior is undefined.

Also, the ability to split a port into two or more links is not disabled. The ports can be configured to support specific widths during training, if such support is appropriate for a given design. An example of this behavior would be a x16 port that could be configured with two x8 links, 4 x4 links, or 16 x1 links.

When using 8b/10b encoding, the unambiguous lane-to-lane anti-skew mechanism as in the PCIe ^TM specification is the COM symbol of the ordered set received during the training sequence or SKP ordered set, since all Sorted sets are transmitted concurrently on the channel. The MK0 symbols transmitted during the synchronization sequence of the HS-BURST can be used for lane-to-lane deskew.

As briefly described above with reference to FIG. 4, the link training and state manager can be configured to perform various operations, including adapting the upper layers of the PCIe ^™ protocol stack to lower layer PHY units of different protocols. In addition, this link manager is capable of configuring and managing single or multiple lanes and may include support for: symmetric link bandwidth, compatibility with state machines at the PCIe ^TM transaction and data link layers, link link training, optional symmetric link shutdown state, and control of sideband signals for robust communications. Accordingly, embodiments provide for implementing the PCIe ^™ transaction and data link layers with limited modifications to account for different link speeds and asymmetric links. In addition, using the link manager according to the embodiment of the present invention can support multi-channel, asymmetric link configuration, sideband unification and dynamic bandwidth scaling, and further realize bridging between different communication protocol layers.

Referring now to FIG. 5 , there is shown a state diagram 500 for a link training state machine, which can be part of a link manager according to an embodiment of the present invention. As shown in FIG. 5 , link training can begin in a detection state 510 . This state occurs at power-on reset and applies to both upstream and downstream ports. After the reset is complete, all configured lanes can transition to a given state, the HIBERN8 state, where each end of the link can signal using a sideband channel, eg via the PRESENCE signal. Note that in this detection state, a high-impedance signal, the DIF-Z signal, can be driven on all channels.

Therefore, when a PRESENCE event is signaled and received, control passes from the Detect state 510 to the Configure state 520 and drives this high impedance on all configured channels. In configuration state 520, PHY parameters can be configured and once done on all configuration lanes at each end of the link, a configuration ready signal (CFG-RDY) can be indicated, for example using a sideband interconnect, simultaneously on all lanes maintain high impedance.

So once this configuration readiness indication is sent and received via the sideband interconnect, control passes to the shutdown state 530 . That is, in this L0.STALL state, the PHY transitions to the STALL state and continues to drive high impedance on all configured channels. As can be seen, depending on whether data is available for transmission or reception, control can pass to the active state L1 (state 530 ), the low power state (L1 state 540 ), the deep low power state (L1.OFF state 545 ) or return to configuration Status 520.

Thus, in the STALL state, the negative drive signal DIF-N can be transmitted on all configured channels. Then, when booted by the initiator, the BURST sequence can begin. Therefore, control passes to active state 530 after the MARKER0 (MK0 ) symbol is transmitted.

In one embodiment, the receiver can detect exit from STALL state on all configured lanes and perform bit lock and symbol lock according to eg MIPI specification. In embodiments with multi-lane links, this MK0 symbol can be used to establish lane-to-lane deskew.

Conversely, all configured lanes may transition to the SLEEP state when directed to a low power state (ie, L1 state 540 ). All configured lanes may then transition to the HIBERN8 state when directed to a deeper low power state (ie L1.OFF state 545). Finally, when directed back to the configured state, all configured channels are similarly transitioned to the HIBERN8 state.

Still referring to FIG. 5 , for active data transfers, control therefore passes to the active state 550 . Specifically, this is the state at which the Link and Transaction layers start exchanging information using Data Link Layer Packets (DLLPs) and TLPs. In this way, payload transfers can take place, and at the end of such transfers, TAIL OF BURST symbols can be transferred.

As can be seen, control can be passed from this active state back to the STALL state 530, to the recovery state 560 (e.g. in response to a receiver error, or when otherwise directed), or to a deeper low power (e.g., L2) State 570.

To return to the halted state, the transmitter may send an EIOS sequence on all configured channels followed by a TAIL of BURST indication.

Control can also pass to recovery state 560 if an error occurs or is otherwise directed. Here, a transition to recovery causes all configured channels to enter the STALL state in both directions. To achieve this, a GO TO STALL signal can be sent on the sideband interconnect, and the transmitter of this signal can wait for a response. When this stall signal has been sent and received, control passes back to the STALL state 530 as indicated by the GO TO STALL indication received on the sideband interconnect. Note that this recovery state therefore uses sidebands to establish the protocol to coordinate simultaneous entry into the STALL state.

Operation is according to states 540 and 545 with respect to low power states L1 and L1.OFF. In particular, control passes from the STALL state to the L1 low power state 540 to enable the PHY to be placed in the SLEEP state. In this state, a negative drive signal, the DIF-N signal, can be driven on all configured channels. When directed to exit the state, control passes back to the STALL state, such as signaling a PRESENCE signal on the sideband interconnect.

As also seen, the deeper low state L1.OFF can be entered when all L1.OFF conditions are met. In one embodiment, these conditions may include full power gating or turning off power to the PHY unit. In this deeper low power state, the PHY can be placed in the HIBERN8 state and drive high impedance signals on all configured channels. To exit this state, control is passed back to the STALL state by driving DIF-N on all configured channels.

As further seen in FIG. 5, there may be an additional state, a still further deeper low power state (L2) 570, which can be entered from the active state when power is to be turned off 570. In one embodiment, this state may be the same as that of the PCIe ^™ specification.

Referring now to Table 2, there is shown a mapping between LTSSM states according to the PCIe ^™ specification and corresponding M-PHY states according to an embodiment of the present invention.

Table 2

LTSSM status M-PHY state details detection, polling SAVE State transitions through the SAVE substate configuration BURST BURST (PREP, SYNC) sub-state recover BURST/SLEEP/STALL Can be in BURST state, but will transition to BURST via SLEEP/STALL L0 BURST (payload) BURST mode and swap transactions L0s STALL STALL state L1 SLEEP SLEEP state L1.OFF HIBERN8 HIBERN8 L2 UNPOWERED UNPOWERED state disabled DISABLED DISABLED state loopback no action Link speed can change when entering loopback from configuration hot reset INLINE RESET INLINE RESET state

As described above with reference to FIG. 2, embodiments provide a unified sideband mechanism that can be used for link management as well as optional in-band support. In this way, using sideband circuitry and interconnects, link management and control can occur independently of the higher speed (and more power consuming) circuitry of the physical layer for the main interconnect. Further in this way, when the portion of the PHY unit associated with the main interconnect is powered down, this sideband channel can be used, achieving a reduction in power consumption. Also, this unified sideband mechanism can be used before training the main interconnect and also when there is a failure on the main interconnect.

Still further, via this unified sideband mechanism, there can be a single interconnect in each direction, such as a differential pair, reducing pin count and enabling the addition of new capabilities. Embodiments can also enable faster, more robust clock/power gating and can use this link to disambiguate in conventional protocols such as the PCIe ^™ sideband mechanism.

While the scope of the invention is not limited thereto, in various embodiments, a sideband interconnect (eg, sideband interconnect 270 of FIG. 2 ) can be implemented as a single-wire bidirectional sideband signal, a dual-wire bidirectional In-band signaling mechanisms, such as are available using M-PHY in low-power pulse width modulation (PWM) mode, or implemented as in-band high-speed signaling mechanisms, such as Physical Layer Ordered Set or DLLP.

By way of example and not limitation, various physical layer methods may be supported. When using sideband interconnects, the first approach can be to provide a single-wire bidirectional sideband signal with minimal pin count. In some embodiments, this signal can be multiplexed on existing sidebands, such as PERST#, WAKE# or CLKREQ signals. A second approach could be a two-wire bidirectional unidirectional signal set, which can be simpler and somewhat more efficient than the single-wire approach, at the cost of additional pins. This implementation can be multiplexed on existing sidebands, such as PERST# for the host device and CLKREQ# for the device host (in this instance, maintaining the existing signal directionality, simplifying the dual-mode implementation). A third approach could be a low-speed in-band signaling mechanism, such as M-PHY LS PWM mode, which reduces pin count relative to sideband mechanisms and can still support similarly low power levels. Because this mode of operation is mutually exclusive with high-speed operation, it can be combined with high-speed in-band mechanisms such as Physical Layer Ordered Sets or DLLP. Although this approach is not low-power, it maximizes commonality with existing high-speed IO. When combined with low-speed in-band signaling, this approach can provide a good low-power solution.

To implement one or more of these configurations in a given system, a semantic layer can be provided which can be used to determine the meaning of information exchanged above the physical layer as well as the policy layer which can be used to comprehend device/platform level action/reaction. In one embodiment, these layers may exist in the SB PHY unit.

By providing a layered approach, embodiments allow for sideband capabilities (which may be preferred in some implementations due to simplicity and/or low power operation) and in-band capabilities (which may be preferred for other implementations) , such as avoiding the need for additional pin counts) different physical layer implementations for both.

In one embodiment, multiple sideband signals can be configured, eg, via a semantic layer, into a single data packet for communication via a unified sideband mechanism (or in-band mechanism). In one embodiment, Table 3 below shows the various signals that may be present in one embodiment. In the table shown, the logical direction of the signals is shown by arrows, where the up arrow is defined as the direction to the host (e.g., the root complex) and the down arrow is defined as the direction to the device (e.g., a peripheral such as a radio solution) direction.

table 3

Device exists ↑

Good power ↓

power off↓

Good reference clock ↓

Base reset↓

Configuration preparation ↑↓

Ready to train ↑↓

Start training ↑↓

L1pg Request ↑↓

L1pg rejects ↑↓

L1pg authorization↑↓

OBFF CPU active↓

OBFF DMA↓

OBFF free↓

wake up ↑

The response to the handshake is received ↑↓.

Referring now to FIG. 6 , there is shown a flowchart for various states of a sideband mechanism according to an embodiment of the present invention. As shown in FIG. 6, these various states may relate to the root complex (eg, host control operations). State diagram 600 may provide control of various states via the host. As can be seen, operation begins in a pre-boot state 610 in which a presence signal can be transmitted. Note that this presence signal can be as described above with respect to link management operations. Control then passes to the boot state 620 where various signals can be transmitted, namely a power good signal, a reset signal, a reference clock status signal, and a ready to train signal. Note that all of these signals can be conveyed via a single data packet, where each of these signals may correspond to an indicator or field of the data packet (eg, a 1-bit indicator of the data packet).

Still referring to FIG. 6, control next passes to the active state 630, where the system may be in the active state (e.g., S0), the corresponding device (e.g., the downstream device may be in the active device state (e.g., D0) and the link may be in the active state , shutdown or low-power state (for example, L0, L0s, or L1). As you can see, in this state, various signals can be transmitted, including OBFF signal, clock request signal, reference clock status, request L0 signal, and prepare for training Signal.

Next, control can pass to a low power state 640, eg, after performing the signaling described above. As can be seen, in this low power state 640, the system can be active while the device can be in a relatively low latency low power state (eg, D3 hot). Additionally, the link may be in a given low power state (eg, L2 or L3). As seen in these states, the signals conveyed via the unified sideband packets may include wakeup signals, reset signals, and power good signals.

A second low power state 650 can be entered when the system enters a deeper low power state (e.g., when the system is in state S0 and the device is in D3 cold state and the link is similarly in L2 or L3 state When. As can be seen, the same wakeup, reset, and power good signals can be conveyed. Also seen in FIG. , D3 cold) and the same signal can occur in the same link low power states L2 and L3. While this particular set of sideband information conveyed is shown, it is to be understood that the scope of the invention is not limited thereto.

Embodiments thus provide a layered structure with extensibility that balances simplicity and low latency against flexibility. In this way, it is possible to replace existing sideband signals and additional sideband signals with a smaller number of signals, and to enable future expansion of the sideband mechanism without adding more pins.

Referring now to FIG. 7 , a flowchart of a method according to an embodiment of the present invention is shown. As shown in FIG. 7 , method 700 may be used to transmit data via a converged protocol stack comprising upper layers of one communication protocol and lower layers of a different communication protocol, such as a physical layer. In the example shown, a converged protocol stack as described above is assumed, ie with the upper transaction and data link layers of the PCIe ^™ protocol and the physical layer of a different specification (eg MIPI specification). Of course, there may also be additional logic that enables the aggregation of these two communication protocols into a single protocol stack, such as the logic and circuitry discussed above with respect to FIG. 4 .

As seen in FIG. 7 , method 700 can begin by receiving a first transaction in a protocol stack of a first communication protocol (block 710 ). For example, various logic such as the root complex of the kernel, other execution engines, etc. seek to send information to another device. Therefore, this information can be passed to the transaction layer. As seen, control passes to block 720 where the transaction can be processed and provided to the logic of the PHY of the second communication protocol. Such processing may include the various operations discussed above with respect to the flow of FIG. 4, where various operations such as receiving data, performing flow control, linking operations, packing operations, etc., can occur. In addition, various operations can occur to provide data link layer packets to the PHY. Next, control passes to block 730, where this first transaction can be translated into a second format transaction in the logical portion of the PHY. For example, arbitrary transformations of symbols can be performed (when required). Additionally, various conversion operations can occur that are performed to thereby convert the transaction into a format for transmission over the link. Accordingly, control can pass to block 740, where this second format transaction can be communicated from the PHY to the device via the link. As an example, the second format transaction can be serialized data after wire encoding, serialization, or the like. While shown at this high level in the embodiment of FIG. 7, it is to be understood that the scope of the present invention is not so limited.

Referring now to FIG. 8 , there is shown a block diagram of components found in a computer system in accordance with an embodiment of the present invention. As shown in Figure 8, system 800 can include many different components. These components can be implemented as ICs, portions thereof, discrete electronic devices, or other modules that fit into a circuit board, such as a computer system's motherboard or plug-in card, or as an IC that is otherwise incorporated within a computer system's chassis. components. Note also that the block diagram of Figure 8 is intended to show a high-level view of the many components of a computer system. It is to be understood, however, that in certain embodiments additional components may be present, and that additionally, in other embodiments different arrangements of the components shown may occur.

As seen in FIG. 8, processor 810 (which may be a low power multi-core processor socket such as an ultra-low voltage processor) may serve as the main processing unit and central hub for communicating with the various components of the system . Such a processor can be implemented as a SoC. In one embodiment, processor 810 may be an ^Intel® Architecture Core ^™ based processor (such as an i3, i5, i7, or another such processor available from Intel Corporation of Santa Clara, California). However, it is to be understood that other low power processors such as those available from Advanced Micro Devices (AMD) of Sunnyvale, CA, ARM based ARM from ARM Corporation Holdings, Inc. may alternatively exist in other embodiments such as the Apple A5 processor. or MIPS-based designs from MIPS Technologies, Inc., Sunnyvale, California, or their licensors or adopters.

Processor 810 may be in communication with system memory 815, which in embodiments can be implemented with multiple memory devices to provide a given amount of system memory. As an example, the memory can be based on a Low Power Double Data Rate (LPDDR) based design of the Joint Electron Device Engineering Conference (JEDEC), such as the current LPDDR2 standard according to JEDEC JESD 209-2E (published April 2009), or called LPDDR3 is the next-generation LPDDR standard that will provide extensions to LPDDR2 to increase bandwidth. As an example, 2/4/8 gigabytes (GB) of system memory can be present and can be coupled to the processor 810 via one or more memory interconnects. In various implementations, individual memory devices can have different package types, such as single die package (SDP), dual die package (DDP), or quad die package (QDP). These devices can in some embodiments be soldered directly to the motherboard to provide a low profile solution, while in other embodiments the devices can be configured as one or more memory modules which in turn can be connected by a given tor coupled to the motherboard.

Mass storage 820 may also be coupled to processor 810 in order to provide persistent storage of information, such as data, applications, one or more operating systems, and the like. In various embodiments, to enable thinner and lighter system designs, and to improve system responsiveness, such mass storage may be implemented via SSDs. However, in other embodiments, mass storage may be implemented primarily using hard disk drives (HDDs), with a lesser amount of SSD storage acting as SSD cache to enable non-volatile storage of background status and other such information during shutdown events , so that fast power-up can occur when restarting system activity. Also shown in FIG. 8, flash memory device 822 may be coupled to processor 810, eg, via a serial peripheral interface (SPI). This flash memory device may provide non-volatile storage of system software including basic input/output software (BIOS) and other firmware for the system.

Various input/output (IO) devices may exist within system 800 . Specifically shown in the embodiment of FIG. 8 is a display 824, which may be a high resolution LCD or LED panel disposed within the lid of the chassis. This display panel may also provide a touch screen 825, e.g. externally fitted on said display panel such that via user interaction with this touch screen, user input can be provided to the system to achieve desired operations, e.g. regarding information display, information access Wait. In one embodiment, display 824 may be coupled to processor 810 via a display interconnect, which can be implemented as a high-performance graphics interconnect. ^The touch screen 825 may be coupled to the processor 810 via another interconnect, which in one embodiment can be an I2C interconnect. As further shown in FIG. 8, in addition to the touch screen 825, user input by touch can also occur via a touch pad 830, which can be disposed within the chassis and can also be coupled to the same ^I2 as the touch screen 825. C interconnect.

Various sensors may be present within the system and may be coupled to processor 810 in different ways for perceptual computing and other purposes. Certain inertial and environmental sensors may be coupled to processor 810 through sensor hub 840 (eg, via an I ² C interconnect). In the embodiment shown in FIG. 8 , these sensors may include an accelerometer 841 , an ambient light sensor (ALS) 842 , a compass 843 and a gyroscope 844 . In one embodiment, other environmental sensors may include one or more thermal sensors 846, which may be coupled to processor 810 via a system management bus (SMBus) bus. It is also to be understood that one or more of the described sensors may be coupled to the processor 810 via an LPS link in accordance with an embodiment of the present invention.

Also seen in FIG. 8, various peripheral devices may also be coupled to processor 810 via low pin count (LPC) interconnects. In the illustrated embodiment, various components can be coupled through an embedded controller 835 . These components can include a keyboard 836 (eg, coupled via a PS2 interface), a fan 837 and a thermal sensor 839 . In some embodiments, touchpad 830 may also be coupled to EC 835 via a PS2 interface. Additionally, a secure processor (such as a Trusted Platform Module (TPM) 838 according to the Trusted Computing Group (TCG) TPM Specification Version 1.2 (October 2, 2003)) may also be coupled to the processor via this LPC interconnect. device 810.

System 800 can communicate with peripheral devices in a variety of ways, including wirelessly. In the embodiment shown in Figure 8, there are various wireless modules, each of which can correspond to a radio configured for a particular wireless communication protocol. One means for wireless communication within a short range, such as the near field, may be via a Near Field Communication (NFC) unit 845 , which in one embodiment may communicate with the processor 810 via the SMBus. It is to be noted that via this NFC unit 845, devices in close proximity to each other can communicate. For example, a user can enable system 800 to communicate with another (for example) portable device (such as user's smartphone) communication. Wireless power transfer can also be performed using the NFC system.

As seen further in FIG. 8 , additional wireless units can include other short-range wireless engines, including WLAN unit 850 and Bluetooth unit 852 . Using the WLAN unit 850 , Wi-Fi™ communication according to a given Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard can be realized, while via the Bluetooth unit 852 short-range communication via the Bluetooth protocol can take place. These units may communicate with processor 810 via, for example, a USB link or a Universal Asynchronous Receiver Transmitter (UART) link. Or these units may be coupled to processor 810 via an interconnect via a low power interconnect such as the converged PCIe/MIPI interconnect described herein or another such protocol such as the Serial Data Input/Output (SDIO) standard. Of course, the actual physical connections between these peripherals, which may be configured on one or more add-in cards, can be by means of NGFF connectors that fit into the motherboard.

Additionally, wireless wide area communications (eg, according to cellular or other wireless wide area protocols) can occur via a WWAN unit 856 which may in turn be coupled to a Subscriber Identity Module (SIM) 857 . In addition, in order to realize the reception and use of location information, there may also be a GPS module 855 . It is to be noted that in the embodiment shown in FIG. 8, the WWAN unit 856 and the integrated capture device such as the camera module 854 may communicate via a given USB protocol (such as a USB2.0 or 3.0 link ⁾ , or a UART or I2C protocol communication. The actual physical connection of these units can again be via fitting NGFF plug-in cards to NGFF connectors configured on the motherboard.

To provide audio input and output, an audio processor can be implemented via a digital signal processor (DSP) 860, which may be coupled to processor 810 via a high-resolution audio (HAD) link. Similarly, DSP 860 may communicate with an integrated coder/decoder (CODEC) and amplifier 862, which in turn may be coupled to an output speaker 863, which may be implemented within the chassis. Similarly, the amplifier and CODEC 862 can be coupled to receive audio input from a microphone 865, which in an embodiment can be implemented via a dual array microphone to provide high quality audio input for voice activated control of various operations within the system. Note also that audio output can be provided from amplifier/COEDC 862 to headphone jack 864 .

Embodiments can thus be used in many different environments. Referring now to FIG. 9 , an example system 900 that can be used with embodiments is shown. As seen, system 900 may be a smartphone or other wireless communicator. As shown in the block diagram of FIG. 9, system 900 may include a baseband processor 910, which may be a multi-core processor capable of handling baseband processing tasks as well as application processing. Accordingly, the baseband processor 910 is capable of performing various signal processing related to communication, as well as performing calculation operations for the device. In turn, the baseband processor 910 can be coupled to a user interface/display 920, which in some embodiments can be implemented by a touch screen display. Additionally, baseband processor 910 may be coupled to a memory system, which in the embodiment of FIG. 9 includes non-volatile memory (ie, flash memory 930 ) and system memory (ie, dynamic random access memory (DRAM) 935 ). As further seen, the baseband processor 910 can be further coupled to a capture device 940, such as an image capture device capable of recording video and/or still images.

In order to implement communication transmission and reception, various circuits may be coupled between the baseband processor 910 and the antenna 980 . In particular, a Radio Frequency (RF) transceiver 970 and a Wireless Local Area Network (WLAN) transceiver 975 may be present. In general, the RF transceiver 970 can be used in a given wireless communication protocol such as 3G or 4G based on Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Long Term Evolution (LTE), or other protocols. The communication protocol receives and transmits wireless data and makes calls. Other wireless communications such as reception or transmission of radio signals, such as AM/FM, or Global Positioning Satellite (GPS) signals may also be provided. In addition, via the WLAN transceiver 975 local area wireless signals can also be implemented, such as according to the Bluetooth™ standard or the IEEE802.11 standard (such as IEEE802.11a/b/g/n). Note that the link between the baseband processor 910 and one or both of the transceivers 970 and 975 may be via a low-power aggregated interconnect that combines and maps the functions of a PCIe™ interconnect and a low-power interconnect such as a MIPI interconnect. even. While shown at this high level in the embodiment of FIG. 9, it is to be understood that the scope of the present invention is not limited in this regard.

Embodiments may be used in many different types of systems. For example, in one embodiment, a communications device can be arranged to perform the various methods and techniques described herein. Of course, the scope of the present invention is not limited to communication devices, and rather, other embodiments can involve other types of means for processing instructions, or one or more machine-readable media, including instructions that respond to being executed on a computing device such that The device performs instructions for one or more of the methods and techniques described herein.

Embodiments may be implemented in code and may be stored on a non-transitory storage medium having stored thereon instructions that can be used to program a system to carry out the instructions. The storage media may include, but is not limited to: any type of magnetic disk, including floppy disks, compact disks, solid state drives (SSD), compact disk read only memory (CD-ROM), rewritable compact disk (CD-RW), and Magneto-optical disks; semiconductor devices such as read-only memory (ROM), random-access memory (RAM) (such as dynamic random-access memory (DRAM), static random-access memory (SRAM)), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM); magnetic or optical cards, or any other type of media suitable for storing electronic instructions.

While the invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. The appended claims are intended to cover all such modifications and changes as fall within the true spirit and scope of the invention.

Claims (29)

1. A device for link training and management, comprising: a protocol stack for the Peripheral Component Interconnect Express ^™ (PCIe ^™ ) communication protocol, the protocol stack including a transaction layer and a link layer; and a physical (PHY) unit coupled to the protocol stack to provide communication between the apparatus and a device coupled to the apparatus via a physical link, the physical unit having a low power communication protocol and including a a physical unit circuit of a low power communication protocol and a logical layer interfacing said protocol stack with said physical unit circuit, said logical layer including a link training state machine performing link training of said physical link and including Mapping logic for mapping a first special symbol of the PCIe ^TM communication protocol to a second special symbol of the low power communication protocol. 2. The apparatus of claim 1 , wherein the physical link has an asymmetric width from the apparatus to the device than from the device to the apparatus, and the physical link is configurable as Operating at an asymmetric frequency from the device to the device as from the device to the device. 3. The apparatus of claim 1, wherein the link training state machine initializes a physical link from reset of the apparatus to an initial link width and frequency in advance without negotiation with the device. 4. The apparatus of claim 3, wherein the link training state machine causes a change in a link width of the physical link without negotiation with the device. 5. The apparatus of claim 1, further comprising a sideband channel coupled between the apparatus and the device, separate from the physical link, the sideband channel comprising a and wherein the second physical unit transmits a first presence signal to the device and receives a second presence signal from the device, the link training state machine responds to Receiving a second presence signal in a second physical unit configures the physical link. 6. A method for link training and management, comprising: In a first integrated circuit coupled to a second integrated circuit via a physical link, executing a physical (PHY) unit comprising a physical unit circuit having a low power communication protocol in response to powering up of the first integrated circuit detection state of a link training state machine coupled to a protocol stack for a Peripheral Component Interconnect Express ^™ (PCIe ^™ ) communication protocol including a transaction layer and a link layer; After execution of the detection state, in the first integrated circuit, the configuration state of the link training state machine is executed, including placing the sending a configuration ready signal to the second integrated circuit; and In said first integrated circuit, in response to receiving a second configuration ready signal from said second integrated circuit via said sideband link, a halt state of a link training state machine is executed, wherein during said halt state , the physical unit drives a differential N signal on the physical link. 7. The method of claim 6, further comprising initiating a burst sequence in the shutdown state to transition into the active state of the link training state machine. 8. The method of claim 7, further comprising: in the active state, transferring a payload from the first integrated circuit to the second integrated circuit, and thereafter transferring a tail of a burst signal to convert to the shutdown state. 9. The method of claim 6, further comprising: transitioning from the shutdown state into a first low power state, and driving the differential N over the physical link in the first low power state Signal. 10. The method of claim 9, further comprising transitioning from the first low power state to the shutdown state in response to receiving a presence signal from the second integrated circuit via the sideband link. 11. The method of claim 9, further comprising: transitioning from the shutdown state to a second low power state lower than the first low power state when a set of predetermined conditions is met state, and driving a differential high impedance signal on the physical link in the second low power state. 12. The method of claim 7, further comprising transitioning from the active state to a resumed state in response to a receiver error. 13. The method of claim 6, further comprising: sending a shutdown enable signal to the second integrated circuit via the sideband channel; and Transitioning to the shutdown state is responsive to receiving a shutdown indication signal from the second integrated circuit via the sideband link. 14. The method of claim 7, further comprising transitioning from the active state to a powered-down state in response to a communication received in a physical unit from the protocol stack. 15. A system for link training and management, comprising: A multi-core processor, including a plurality of cores and a protocol stack for realizing communication between the multi-core processor and peripheral devices via a physical link, the protocol stack includes: Transaction layer according to the Peripheral Component Interconnect Express ^™ (PCIe ^™ ) communication protocol; A data link layer according to the PCIe ^TM communication protocol; and A physical layer according to a low power communication protocol comprising a physical layer transport controller and a physical (PHY) unit transport circuit, wherein the physical layer transport controller adapts the physical unit transport circuit to a transaction with the PCIe ^™ communication protocol layer and a data link layer, the physical layer further includes a link training state machine that performs link training of the physical link, and includes mapping the first special symbol of the PCIe ^TM communication protocol to the low power mapping logic for the second special symbol of the communication protocol; and A peripheral device coupled to the multi-core processor. 16. The system of claim 15 , wherein the link training state machine: in response to powering up of the multi-core processor, executes a configuration state of the link training state machine after executing a detection state, including via a sideband link coupled between the multi-core processor and the peripheral device sends a configuration ready signal to the peripheral device; and in response to receiving a second configuration ready signal from the peripheral device via the sideband link signal to execute a shutdown state of the link training state machine, wherein during the shutdown state the physical unit transmission circuit drives a differential N signal on the physical link. 17. The system of claim 16 , wherein the link training state machine initiates a burst sequence in the shutdown state to transition into the active state of the link training state machine, and in the active state transferring a payload from the multi-core processor to the peripheral, and then transferring a tail of a burst to transition to the halt state. 18. The system of claim 17 , wherein the link training state machine sends a shutdown start signal to the peripheral via the sideband link and responds to The peripheral equipment is converted to the shutdown state upon receiving the shutdown indication signal. 19. The system of claim 15, wherein the peripheral device comprises a multiradio integrated circuit. 20. A device for link training and management, comprising: For executing, in a first integrated circuit coupled to a second integrated circuit via a physical link, a physical (PHY) having a low power communication protocol including a physical unit circuit in response to powering up of the first integrated circuit means for detecting state of a link training state machine of a unit coupled to a protocol stack for a Peripheral Component Interconnect Express ^™ (PCIe ^™ ) communication protocol including a transaction layer and a link layer; configuration state means for executing said link training state machine in said first integrated circuit after said detection state is executed, comprising means for via coupling between said first and second integrated circuits means for sending a configuration ready signal to said second integrated circuit via a sideband link; and means for, in said first integrated circuit, in response to receiving a second configuration ready signal from said second integrated circuit via said sideband link, for executing a halt state of a link training state machine, wherein in said During the shutdown state, the physical unit drives a differential N signal on the physical link. 21. The apparatus of claim 20, further comprising means for initiating a burst sequence in the shutdown state to transition into the active state of the link training state machine. 22. The apparatus of claim 21 , further comprising means for, in said active state, transferring a payload from said first integrated circuit to said second integrated circuit, and thereafter transferring a tail of a burst signal to transition the device into the shutdown state. 23. The apparatus of claim 20, further comprising: for transitioning from the shutdown state into a first low power state, and driving the differential N signaling device. 24. The apparatus of claim 23, further comprising means for transitioning from the first low power state to the shutdown state in response to receiving a presence signal from the second integrated circuit via the sideband link. state of the device. 25. The apparatus of claim 23, further comprising: for transitioning from the shutdown state to a second low power state when a set of predetermined conditions are met, and in the second low power state in the means for driving a differential high impedance signal on a physical link, said second low power state being lower than said first low power state. 26. The apparatus of claim 21, further comprising means for transitioning from the active state to a resumed state in response to a receiver error. 27. The device of claim 20, further comprising: means for sending a shutdown activation signal to the second integrated circuit via the sideband channel; and means for transitioning to the shutdown state in response to receiving a shutdown indication signal from the second integrated circuit via the sideband link. 28. The apparatus of claim 21, further comprising means for transitioning from the active state to the powered-down state in response to a communication received in a physical unit from the protocol stack. 29. A machine-readable medium having stored thereon instructions which, when executed, cause a computing device to perform the method of any one of claims 6-14.