CN118093490B

CN118093490B - Bus protocol conversion method and device

Info

Publication number: CN118093490B
Application number: CN202410455405.8A
Authority: CN
Inventors: 曹泽文; 彭卓; 赵华龙; 唐丹; 包云岗
Original assignee: Beijing Open Source Chip Research Institute
Current assignee: Beijing Open Source Chip Research Institute
Priority date: 2024-04-16
Filing date: 2024-04-16
Publication date: 2024-07-26
Anticipated expiration: 2044-04-16
Also published as: CN118093490A

Abstract

The application provides a bus protocol conversion method and a device, which relate to the technical field of system-on-chip and comprise the following steps: the method comprises the steps of obtaining a first request and a second request which are generated by a processor core and use an intra-core bus protocol inside the processor core, combining the first request and the second request into a third request which uses an extra-core bus protocol outside the processor core when the first request and the second request meet a first preset condition, and sending the third request to an external device corresponding to the third request, so that the same effect that the first request and the second request are respectively sent to the external device after protocol conversion is achieved, the request sending efficiency is improved, the bus protocol conversion efficiency is further improved, and the problem that the bus protocol conversion efficiency is low in the prior art is solved.

Description

Bus protocol conversion method and device

Technical Field

The present application relates to the field of system-in-chip technologies, and in particular, to a bus protocol conversion method and apparatus.

Background

A System on Chip (SoC) includes a processor including a plurality of processor cores connected to an input/output port using an AHB-Lite protocol (a bus protocol), a memory, an input/output port for connection to an external device, and the like. Since the intra-core bus protocol inside the processor core is different from the AHB-Lite protocol, a bus protocol conversion method is required in order for the processor core to access external devices.

In the prior art, the processor core accesses the external device by converting each request using the internal bus protocol of the processor core into a request of the AHB-Lite protocol and transmitting the request to the external device, respectively.

In carrying out the present application, the inventors have found that at least the following problems exist in the prior art: since each request using the internal bus protocol of the processor core is converted into a request of the AHB-Lite protocol and transmitted to the external device, respectively, the bus protocol conversion efficiency is low.

Disclosure of Invention

The embodiment of the application provides a bus protocol conversion method and a bus protocol conversion device, which are used for solving the problem that in the prior art, the efficiency of bus protocol conversion is low because each request using the internal bus protocol of a processor core is respectively converted into a request of an AHB-Lite protocol and sent to external equipment.

In a first aspect, an embodiment of the present application provides a bus protocol conversion method, applied to a processor core in a system-in-a-chip, where the method includes:

Acquiring a first request and a second request generated by the processor core, wherein the first request and the second request are signal sets using an intra-core bus protocol inside the processor core;

Combining the first request and the second request into a third request, wherein the third request is a signal set using an out-of-core bus protocol outside the processor core, under the condition that the first request and the second request meet a first preset condition;

Transmitting the third request to an external device corresponding to the third request so as to read and write data in the external device;

Wherein the number of bits of the third data signal in the third request is the sum of the number of bits of the first data signal in the first request and the number of bits of the second data signal in the second request.

In a second aspect, an embodiment of the present application further provides a bus protocol conversion device, applied to a processor core in a system-in-chip, where the device includes:

the first acquisition module is used for acquiring a first request and a second request generated by the processor core, wherein the first request and the second request are signal sets using an intra-core bus protocol inside the processor core;

A merging module, configured to merge the first request and the second request into a third request, where the third request is a signal set using an out-of-core bus protocol outside the processor core, if the first request and the second request meet a first preset condition;

A sending module, configured to send the third request to an external device corresponding to the third request, so that data reading and writing are performed in the external device;

In the embodiment of the application, under the condition that the first request and the second request which use the in-core bus protocol inside the processor core meet the first preset condition, the first request and the second request are combined into the third request which uses the out-of-core bus protocol outside the processor core, and the third request is sent to the external device corresponding to the third request, wherein the bit number of the third data signal in the third request is the sum of the bit number of the first data signal in the first request and the bit number of the second data signal in the second request, and the same effect that the first request and the second request are sent to the external device after being respectively subjected to protocol conversion is realized by sending the third request to the external device, the efficiency of request sending is improved, and the efficiency of bus protocol conversion is improved, and the problem that in the prior art, the efficiency of bus protocol conversion is low due to the fact that each request which uses the in-core bus protocol of the processor core is respectively converted into the request of AHB-Lite protocol and sent to the external device is solved.

The foregoing description is only an overview of the present application, and is intended to be implemented in accordance with the teachings of the present application in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present application more readily apparent.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort to a person skilled in the art.

FIG. 1 is a flowchart of a method for converting a bus protocol according to an embodiment of the present invention;

FIG. 2 is a flowchart illustrating steps of another method for converting a bus protocol according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a bus protocol conversion system according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a specific structure of a bus protocol conversion system according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a clock signal provided by an embodiment of the present application;

FIG. 6 is a schematic diagram of a processor core according to an embodiment of the present application;

FIG. 7 is a state transition diagram of a first state machine according to an embodiment of the present application;

FIG. 8 is a state transition diagram of a second state machine according to an embodiment of the present application;

FIG. 9 is a schematic diagram illustrating a signal state of a bus protocol conversion system according to an embodiment of the present application;

FIG. 10 is a schematic diagram of another signal state of a bus protocol conversion system according to an embodiment of the present application;

Fig. 11 is a block diagram of a bus protocol conversion device according to an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more. Furthermore, the term "and/or" as used in the specification and claims to describe an association of associated objects means that there may be three relationships, e.g., a and/or B, may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. The term "plurality" in embodiments of the present application means two or more, and other adjectives are similar.

The bus protocol conversion method provided by the embodiment of the application is described in detail below through specific embodiments and application scenarios thereof with reference to the accompanying drawings.

Fig. 1 is a flowchart of a bus protocol conversion method according to an embodiment of the present application, where the bus protocol conversion method is applied to a processor core in a system-in-chip, and as shown in fig. 1, the method may include:

step 101, acquiring a first request and a second request generated by the processor core, wherein the first request and the second request are signal sets using an intra-core bus protocol inside the processor core.

In the embodiment of the application, the first request and the second request generated by the processor core are acquired, and then the first request and the second request are combined into the third request under the condition that the first request and the second request meet the first preset condition.

It should be noted that the processor in the system-on-chip may include a microcontroller, a microprocessor, a digital signal processor (DSPs, digital Signal Processors), an Application specific instruction set processor (ASIPs, application-Specific Instruction-set Processors), etc., and the processor may include a plurality of processor cores.

The in-core bus protocol inside the processor core is a custom protocol, i.e., a protocol formed by custom settings.

The first request and the second request are both requests using the intra-core bus protocol, i.e. the set of signals for the request using the intra-core bus protocol, including a plurality of signals, e.g. the request using the intra-core bus protocol includes a read-write request signal, an indication signal of a read or write operation, a byte enable signal of a read or write, a read-write address signal, a write data signal, etc.

Step 102, merging the first request and the second request into a third request, where the third request is a signal set using an out-of-core bus protocol outside the processor core, if the first request and the second request meet a first preset condition.

In the embodiment of the application, when the first request and the second request meet the first preset condition, the first request and the second request are combined into the third request, and then the third request is sent to the external equipment corresponding to the third request.

It should be noted that, the first preset condition is used for characterizing a condition that the first request and the second request can be combined into a third request; the out-of-core bus protocol may be the AHB-Lite bus protocol.

The third request is a request using an out-of-core bus protocol, i.e. a set of signals for the request using an out-of-core bus protocol, comprising a plurality of signals, e.g. the request using an out-of-core bus protocol comprises a signal indicating whether the current transmission request belongs to a lock sequence, a signal indicating the transmission type of the current transmission request, a signal indicating the amount of transmission, a signal indicating the burst type, a protection control signal, a 32-bit system address bus signal, a write data bus signal, etc.

The types of requests may include a read request, a write request, etc., and in the case where the first request and the second request are both read requests, the third request is a read request; in the case where both the first request and the second request are write requests, the third request is a write request.

Step 103, the third request is sent to an external device corresponding to the third request, so that data reading and writing can be performed in the external device.

In the embodiment of the application, the processor core accesses the external device by sending the third request to the external device corresponding to the third request.

It should be noted that, the third request is sent to the external device through the input/output port of the system-on-chip.

The external devices may include flash memory, dynamic random access memory, static random access memory, solid state disk, and the like.

The first data signal and the second data signal are both write data signals in a request using an in-core bus protocol, and the third data signal is a write data bus signal in a request using an out-of-core bus protocol.

The number of bits of the first data signal is equal to that of the second data signal, the bits of the third data signal comprise high bits and low bits, the number of bits of the high bits of the third data signal is equal to that of the low bits of the third data signal, the bits in the high bits of the third data signal are in one-to-one correspondence with the bits of the first data signal, and the bits in the low bits of the third data signal are in one-to-one correspondence with the bits of the second data signal; or the lower bits of the third data signal are in one-to-one correspondence with the first data signal bits, and the upper bits of the third data signal are in one-to-one correspondence with the second data signal bits.

In some embodiments, the first request and the second request are respectively converted into a request using the AHB-Lite bus protocol and sent to the external device, in case the first request and the second request do not meet a first preset condition.

In summary, in the embodiment of the present application, when the first request and the second request using the intra-core bus protocol inside the processor core satisfy the first preset condition, the first request and the second request are combined into the third request using the extra-core bus protocol outside the processor core, and the third request is sent to the external device corresponding to the third request, where the number of bits of the third data signal in the third request is the sum of the number of bits of the first data signal in the first request and the number of bits of the second data signal in the second request, and by sending the third request to the external device, the same effect that the first request and the second request are sent to the external device after protocol conversion is performed respectively is achieved, and the efficiency of sending the request is improved, so that the efficiency of bus protocol conversion is improved, and the problem that in the prior art, the efficiency of bus protocol conversion is low due to the fact that each request using the intra-core bus protocol of the processor core is converted into a request of the AHB-Lite protocol and sent to the external device respectively is solved.

Fig. 2 is a flowchart of specific steps of a bus protocol conversion method according to an embodiment of the present application, where, as shown in fig. 2, the method may include:

step 201, acquiring a first request and a second request generated by the processor core, where the first request and the second request are both signal sets using an intra-core bus protocol inside the processor core.

The implementation of this step is similar to the implementation of the above-mentioned sub-step 101, and will not be repeated here.

Optionally, in some embodiments, the first clock cycle in which the first request is generated and the second clock cycle in which the second request is generated are adjacent.

In the embodiment of the application, the efficiency of request transmission is improved by combining two requests using the in-core bus protocol in adjacent periods into one request using the out-of-core bus protocol.

Step 202, determining that the first request and the second request meet the first preset condition and merging the first request and the second request into a third request, wherein the third request is a signal set using an out-of-core bus protocol outside the processor core, when the first data signal and the second data signal meet a second preset condition and the first access address of the first request and the second access address of the second request meet a third preset condition, and the request types of the first request and the second request are the same, and the first request and the second request are both valid requests.

In the embodiment of the application, when the first data signal and the second data signal meet the second preset condition, the first access address of the first request and the second access address of the second request meet the third preset condition, the request type of the first request and the request type of the second request are the same, and the first request and the second request are valid requests, the first request and the second request are determined to meet the first preset condition, the first request and the second request are combined into the third request, and then the third request is sent to the external device corresponding to the third request.

In the case where the first request and the second request satisfy the first preset condition, the implementation manner of merging the first request and the second request into the third request is similar to the implementation process of the above sub-step 103, and will not be repeated here.

It should be noted that, the second preset condition is used to characterize the condition of the data signal in the request that the first request and the second request can be combined into the third request; the third preset condition is used to characterize a condition that the first request and the second request can be combined into a third request with respect to an access address in the request.

Step 203, sending the third request to an external device corresponding to the third request, so as to read and write data in the external device.

The implementation of this step is similar to the implementation of the above-mentioned sub-step 103, and will not be repeated here.

Optionally, in some embodiments, the number of bits of the first data signal and the number of bits of the second data signal are each 32 bits, and the number of bits of the third data signal is 64 bits.

In the embodiment of the application, since the number of bits of the first data signal and the number of bits of the second data signal are both 32 bits and the number of bits of the third data signal is 64 bits, the number of bits of the third data signal in the third request is the sum of the number of bits of the first data signal in the first request and the number of bits of the second data signal in the second request, so that the same effect that the first request and the second request are respectively subjected to protocol conversion and then are sent to the external device is achieved by sending the third request to the external device.

In some embodiments, the number of bits (32 bits) of the first data signal is equal to the number of bits (32 bits) of the second data signal, the bits of the third data signal including one high bit (the high 32 bits of the 64 bits of the third data signal) and one low bit (the low 32 bits of the 64 bits of the third data signal), the bits of the high bit of the third data signal being in one-to-one correspondence with the bits of the first data signal, the bits of the low bit of the third data signal being in one-to-one correspondence with the bits of the second data signal; or the lower bits of the third data signal are in one-to-one correspondence with the first data signal bits, and the upper bits of the third data signal are in one-to-one correspondence with the second data signal bits.

Optionally, in some embodiments, the method further comprises the step of (step 204):

Step 204, determining that the first data signal and the second data signal meet the second preset condition when each bit of the first data signal is a valid bit and each bit of the second data signal is a valid bit.

In the embodiment of the application, by determining that the first data signal and the second data signal meet the second preset condition under the condition that each bit of the first data signal is a valid bit and each bit of the second data signal is a valid bit, whether the first request and the second request meet the first preset condition is further determined.

When the request type of the first request is a write request, each bit of the first data signal is a valid bit, which indicates that each bit of the first data signal stores valid data, and the number of bits of data in the first data signal is equal to the number of bits of the first data signal; in the case where the request type of the second request is a write request, each bit of the second data signal is a valid bit, indicating that each bit of the second data signal stores valid data, and the number of bits of data in the second data signal is equal to the number of bits of the second data signal.

Optionally, in some embodiments, the first access address and the second access address are both 32 bits, and the method further includes the following step (step 205):

step 205, determining that the first access address and the second access address meet a third preset condition when the 0 th bit and the 1 st bit of the first access address are binary 0, the 0 th bit and the 1 st bit of the second access address are binary 0, the address value of the 2 nd bit of the first access address is different from the address value of the 2 nd bit of the second access address, and the address values of the 3 rd bit to the 31 rd bit of the first access address and the 3 rd bit to the 31 rd bit of the second access address are the same.

In the embodiment of the application, when the 0 th bit and the 1 st bit of the first access address are binary 0, the 0 th bit and the 1 st bit of the second access address are binary 0, the address value of the 2 nd bit of the first access address is different from the address value of the 2 nd bit of the second access address, and the address values of the 3 rd bit to the 31 rd bit of the first access address and the address values of the 3 rd bit to the 31 rd bit of the second access address are the same, the first access address and the second access address are determined to meet the third preset condition, namely, the 0 th bit and the 1 st bit of the first access address, the 0 th bit and the 1 st bit of the second access address are invalid bits in the in-core bus protocol, the first access address and the second access address are adjacent, and the first access address and the second access address are within 64 bits of the third access address of the third request.

It should be noted that, the address value of the 2 nd bit of the first access address is different from the address value of the 2 nd bit of the second access address, that is, when the address value of the 2 nd bit of the first access address is binary 1, the address value of the 2 nd bit of the second access address is binary 0; in the case where the address value of the 2 nd bit of the first access address is binary 0, the address value of the 2 nd bit of the second access address is binary 1.

The address values of the 3 rd bit to the 31 rd bit of the first access address and the address values of the 3 rd bit to the 31 st bit of the second access address are the same, i.e., the address value of the i th bit of the first access address is the same as the address value of the i th bit of the second access address, i is a positive integer of 3 or more and 31 or less, for example, in the case that the address value of the i th bit of the first access address is binary 1, the address value of the i th bit of the second access address is binary 1; in the case where the address value of the i-th bit of the first access address is binary 0, the address value of the i-th bit of the second access address is binary 0.

Optionally, in some embodiments, the merging the first request and the second request into a third request includes the following sub-steps (sub-step 2021, sub-step 2022):

substep 2021, combining the first data signal and the second data signal into the third data signal.

In an embodiment of the present application, the first data signal and the second data signal are combined into the third data signal, such that the data in the third data signal includes the data in the first data signal and the data in the second data signal.

Substep 2022, determining the access address of the request generated earlier in the first request and the second request as the access address of the third request.

In the embodiment of the application, since the number of bits of the access address of the request using the out-of-core bus protocol is equal to the number of bits of the access address of the request using the in-core bus protocol, the access address of the request generated earlier in the first request and the second request is determined as the access address of the third request so as to meet the requirement of the out-of-core bus protocol.

It should be noted that, in addition to the sub-steps 2021 and 2022, other signals in the third request need to be generated according to the out-of-core bus protocol, for example, a signal indicating whether the current transmission request belongs to the lock sequence, a signal indicating the transmission type of the current transmission request, a signal indicating the transmission amount, a signal indicating the burst type, a protection control signal, and the like.

By performing sub-steps 2021 to 2022, it is possible to achieve the same effect that the first request and the second request are respectively protocol-converted and then transmitted to the external device by transmitting the third request to the external device.

Optionally, in some embodiments, the merging the first request and the second request into a third request includes the following substeps (substep 2023, substep 2024, substep 2025, substep 2026, substep 2027):

Substep 2023 merges the first request and the second request into a fourth request, the fourth request being a set of signals using the intra-core bus protocol, the number of bits of a fourth data signal in the fourth request being a sum of the number of bits of the first data signal and the number of bits of the second data signal.

In the embodiment of the application, the first request and the second request are combined into the fourth request, so that the data of the fourth request is stored in the first-in first-out memory.

It should be noted that, the number of bits of the first data signal is equal to the number of bits of the second data signal, the bits of the fourth data signal include a high bit and a low bit, the number of bits of the high bit of the fourth data signal is equal to the number of bits of the low bit of the fourth data signal, the bits in the high bit of the fourth data signal are in one-to-one correspondence with the bits of the first data signal, and the bits in the low bit of the fourth data signal are in one-to-one correspondence with the bits of the second data signal; or the lower bits of the fourth data signal are in one-to-one correspondence with the first data signal bits, and the upper bits of the fourth data signal are in one-to-one correspondence with the second data signal bits.

In some embodiments, the number of bits (32 bits) of the first data signal is equal to the number of bits (32 bits) of the second data signal, the bits of the fourth data signal include one high bit (the high 32 bits of the 64 bits of the fourth data signal) and one low bit (the low 32 bits of the 64 bits of the fourth data signal), the bits of the high bit of the fourth data signal are in one-to-one correspondence with the bits of the first data signal, and the bits of the low bit of the fourth data signal are in one-to-one correspondence with the bits of the second data signal; or the lower bits of the fourth data signal are in one-to-one correspondence with the first data signal bits, and the upper bits of the fourth data signal are in one-to-one correspondence with the second data signal bits.

The fourth request includes a read-write request signal, an indication signal of a read or write operation, a byte enable signal of a read or write, a read-write address signal, a write data signal, a signal indicating whether the current request is a merge request, and the like, wherein the merge request is a request using the in-core bus protocol after merging the first request and the second request.

Substep 2024, storing the fourth requested data in a first-in-first-out memory.

In the embodiment of the application, the data of the fourth request is stored in the first-in first-out memory, and then after the second clock signal corresponding to the out-of-core bus protocol is generated according to the preset control signal and the first clock signal corresponding to the in-core bus protocol, the data of the fourth request in the first-in first-out memory is sampled and output according to the second clock signal, so as to generate the third request.

The data of the fourth request includes data of an instruction signal of a read or write operation, data of a byte enable signal of read or write, data of a read/write address signal, data of a write data signal, and data of a signal indicating whether the current request is a merge request, etc.

Sub-step 2025, generating a second clock signal corresponding to the out-of-core bus protocol according to a preset control signal and a first clock signal corresponding to the in-core bus protocol; the clock frequency of the second clock signal is less than the clock frequency of the first clock signal.

In the embodiment of the application, the second clock signal corresponding to the out-of-core bus protocol is generated according to the preset control signal and the first clock signal corresponding to the in-core bus protocol, and then the data of the fourth request in the first-in first-out memory is sampled and output according to the second clock signal to generate the third request.

The ratio of the clock frequency of the first clock signal to the clock frequency of the second clock signal is N:1, wherein N is a positive integer greater than or equal to 1.

Optionally, in some embodiments, sub-step 2025 may include the following molecular step (molecular step 2025 a):

in step 2025a, if the preset control signal is at a high level and the first clock signal is at a rising edge, the second clock signal is determined to be at a rising edge.

In the embodiment of the application, the second clock signal is determined to be at the rising edge under the condition that the preset control signal is at the high level and the first clock signal is at the rising edge, so that the data of the fourth request in the first-in first-out memory is sampled and output under the condition that the second clock signal is at the rising edge, and the fifth request is generated.

By means of the control signal, a conversion of the clock frequency of the first clock signal into the clock frequency of the second clock signal can be achieved.

For example, referring to fig. 5, in the case where the control signal HCLKEN is at the high level and the first clock signal HCLK1 is at the rising edge, the second clock signal HCLK2 is at the rising edge, the clock period of the second clock signal HCLK1 is 3 times that of the first clock signal HCLK1, and the ratio of the clock frequency of the first clock signal to the clock frequency of the second clock signal is 3:1.

Sub-step 2026, sampling and outputting the data of the fourth request in the fifo according to the second clock signal, to generate a fifth request; the fifth request is a set of signals using the in-core bus protocol, and the number of bits of a fifth data signal in the fifth request is equal to the number of bits of the fourth data signal.

In the embodiment of the application, the fourth request data in the first-in first-out memory is sampled and output according to the second clock signal to generate the fifth request, namely, the fourth request data in the first-in first-out memory is sampled and output under the condition that the second clock signal is at the rising edge to generate the fifth request, and then the third request is generated according to the fifth request.

The data in the fourth request is the same as the data in the fifth request, the clock signal corresponding to the fourth request is the first clock signal, and the clock signal corresponding to the fifth request is the second clock signal.

Sub-step 2027, generating said third request from said fifth request.

In the embodiment of the application, the third request is generated according to the fifth request, and then the third request is sent to the external device, so that the same effect that the first request and the second request are respectively sent to the external device after protocol conversion is realized.

Note that, the clock signal corresponding to the third request is the second clock signal.

By performing sub-steps 2023 to 2027, it is possible to generate a second clock signal corresponding to the out-of-core bus protocol, and further generate a third request conforming to the second clock signal.

Optionally, in some embodiments, the method further comprises the following steps (step 206, step 207, step 208):

Step 206, obtaining a third feedback corresponding to the third request; the third feedback is a set of signals using the out-of-core bus protocol.

In the embodiment of the application, the third feedback is split into the first feedback corresponding to the first request and the second feedback corresponding to the second request by acquiring the third feedback corresponding to the third request.

The third feedback is feedback sent to the processor core by the external device corresponding to the third request, the third feedback is feedback using an extranuclear bus protocol, the feedback using the extranuclear bus protocol is a signal set for feedback using the extranuclear bus protocol, and the feedback using the extranuclear bus protocol includes a plurality of signals, for example, a signal indicating whether the previous transmission request is completed, a signal indicating a transmission state, a signal for reading a data bus, and the like.

Step 207, splitting the third feedback into a first feedback corresponding to the first request and a second feedback corresponding to the second request; the first feedback and the second feedback are both signal sets using the intra-core bus protocol.

In the embodiment of the application, the third feedback is split into the first feedback corresponding to the first request and the second feedback corresponding to the second request, so that the first feedback and the second feedback are sent to the processor core.

It should be noted that, the first feedback and the second feedback are both feedback using the intra-core bus protocol, that is, the set of signals for feedback using the intra-core bus protocol, including a plurality of signals, for example, the feedback using the intra-core bus protocol includes a read-write feedback request signal, a signal of data of the read feedback, a signal of an error flag of the read or write feedback, and the like.

Step 208, sending the first feedback and the second feedback to the processor core.

The number of bits of the sixth data signal in the third feedback is the sum of the number of bits of the seventh data signal in the first feedback and the number of bits of the eighth data signal in the second feedback.

In the embodiment of the application, the information interaction between the processor core and the external equipment is realized by sending the first feedback and the second feedback to the processor core.

In some embodiments, the sixth data signal may be a signal of a read data bus in feedback using an out-of-core bus protocol, and the seventh data signal, the eighth data signal may be a signal of data of a read feedback in feedback using an in-core bus protocol.

The number of bits of the seventh data signal is equal to the number of bits of the eighth data signal, the bits of the sixth data signal comprise high bits and low bits, the number of bits of the high bits of the sixth data signal is equal to the number of bits of the low bits of the sixth data signal, the bits in the high bits of the sixth data signal are in one-to-one correspondence with the bits of the seventh data signal, and the bits in the low bits of the sixth data signal are in one-to-one correspondence with the bits of the eighth data signal; or the lower bits of the sixth data signal are in one-to-one correspondence with the seventh data signal, and the upper bits of the sixth data signal are in one-to-one correspondence with the eighth data signal.

Optionally, in some embodiments, the number of bits of the seventh data signal and the number of bits of the eighth data signal are each 32 bits, and the number of bits of the sixth data signal is 64 bits.

In the embodiment of the application, since the bit number of the seventh data signal and the bit number of the eighth data signal are both 32 bits, and the bit number of the sixth data signal is 64 bits, the bit number of the sixth data signal in the third feedback is the sum of the bit number of the seventh data signal in the first feedback and the bit number of the eighth data signal in the second feedback, so that the same effect that the first feedback and the second feedback are respectively sent to the processor core after protocol conversion is realized by splitting the third feedback into the first feedback and the second feedback and sending the first feedback and the second feedback to the processor core is realized.

In some embodiments, the number of bits (32 bits) of the seventh data signal is equal to the number of bits (32 bits) of the eighth data signal, the bits of the sixth data signal including one high bit (the high 32 bits of the 64 bits of the sixth data signal) and one low bit (the low 32 bits of the 64 bits of the sixth data signal), the bits of the high bit of the sixth data signal being in one-to-one correspondence with the bits of the seventh data signal, the bits of the low bit of the sixth data signal being in one-to-one correspondence with the bits of the eighth data signal; or the lower bits of the sixth data signal are in one-to-one correspondence with the seventh data signal, and the upper bits of the sixth data signal are in one-to-one correspondence with the eighth data signal.

Optionally, in some embodiments, step 207 includes the following sub-steps (sub-step 2071, sub-step 2072):

substep 2071, converting the third feedback into a fourth feedback, the fourth feedback being a set of signals using the in-core bus protocol.

In the embodiment of the application, the third feedback is converted into the fourth feedback, so that the fourth feedback is split into the first feedback and the second feedback.

The fourth feedback is feedback using the intra-core bus protocol, that is, a set of signals for feedback using the intra-core bus protocol, including a plurality of signals, for example, a signal for reading and writing feedback request, a signal for reading and writing data of the feedback, a signal for reading or writing an error flag of the feedback, and the like.

A substep 2072 of splitting the fourth feedback into the first feedback and the second feedback; the number of bits of the ninth data signal in the fourth feedback is the sum of the number of bits of the seventh data signal and the number of bits of the eighth data signal.

In the embodiment of the application, the fourth feedback is split into the first feedback and the second feedback, so that the first feedback and the second feedback are sent to the processor core.

In some embodiments, the ninth data signal may be a signal of data using a read feedback of 64 bits in the feedback of the intra-core bus protocol, and the seventh data signal, the eighth data signal may be a signal of data using a read feedback of 32 bits in the feedback of the intra-core bus protocol.

The number of bits of the seventh data signal is equal to the number of bits of the eighth data signal, the bits of the ninth data signal include a high bit and a low bit, the number of bits of the high bit of the ninth data signal is equal to the number of bits of the low bit of the ninth data signal, the bits in the high bit of the ninth data signal are in one-to-one correspondence with the bits of the seventh data signal, and the bits in the low bit of the ninth data signal are in one-to-one correspondence with the bits of the eighth data signal; or the bits in the lower bits of the ninth data signal are in one-to-one correspondence with the bits of the seventh data signal, and the bits in the upper bits of the ninth data signal are in one-to-one correspondence with the bits of the eighth data signal.

For example, the number of bits (32 bits) of the seventh data signal is equal to the number of bits (32 bits) of the eighth data signal, the bits of the ninth data signal include one high bit (high 32 bits of 64 bits of the ninth data signal) and one low bit (low 32 bits of 64 bits of the ninth data signal), the high bits of the ninth data signal correspond one-to-one to the bits of the seventh data signal, and the low bits of the ninth data signal correspond one-to-one to the bits of the eighth data signal; or the bits in the lower bits of the ninth data signal are in one-to-one correspondence with the bits of the seventh data signal, and the bits in the upper bits of the ninth data signal are in one-to-one correspondence with the bits of the eighth data signal.

The implementation of sub-steps 2071 through 2072 may be performed by first converting the third feedback to a fourth feedback, splitting the fourth feedback into a first feedback and a second feedback, and then sending the first feedback and the second feedback to the processor core.

Optionally, in some embodiments, step 207 includes the following sub-steps (sub-step 2073):

Substep 2073 splits the sixth data signal into the seventh data signal and the eighth data signal.

In the embodiment of the application, the sixth data signal is split into the seventh data signal and the eighth data signal, so that the same effect that the first feedback and the second feedback are respectively sent to the processor core after protocol conversion is realized by splitting the third feedback into the first feedback and the second feedback and sending the first feedback and the second feedback to the processor core.

Optionally, in some embodiments, the method further comprises the step of (step 209):

step 209, determining that the request type of the first request and the request type of the second request are the same in the case that the first request and the second request are both a read request or a write request.

In the embodiment of the application, by determining that the request type of the first request is the same as the request type of the second request when the first request and the second request are both read requests or write requests, whether the first request and the second request meet the first preset condition or not can be further determined.

The read request of the processor core is used for accessing the external device and reading the data corresponding to the read request in the external device, and the write request of the processor core is used for accessing the external device and writing the data corresponding to the write request in the external device.

Referring to fig. 3, a bus protocol conversion system provided in an embodiment of the present application includes a first processing module and a second processing module, where the first processing module includes a first register and a processing sub-module.

Referring to fig. 4, the processing sub-module includes a second register, a first processing unit, a first storage unit, a second storage unit, a third storage unit, a fifth processing unit, a sixth processing unit, a first state machine, etc., and the second processing module includes a third register, a second processing unit, a fourth register, a third processing unit, a fourth processing unit, a second state machine, etc.

The bus protocol conversion system can realize the conversion between the nuclear bus protocol and the extranuclear bus protocol (AHB-Lite bus protocol), htrans of the AHB-Lite bus protocol only supports DILE and NONSEQ values, hburst only supports SINGLE mode.

Referring to fig. 6, a processor core provided in an embodiment of the present application includes a plurality of bus protocol conversion systems, where the processor core includes a plurality of ports, each port has a corresponding bus protocol conversion system, each bus protocol conversion system implements conversion between an in-core bus protocol and an out-of-core bus protocol (AHB-Lite bus protocol) of a port corresponding to the bus protocol conversion system, specifically, for a port corresponding to the bus protocol conversion system, the bus protocol conversion system converts a request with a 32-bit data bit width of the in-core bus protocol into a request with a 64-bit data bit width of the out-of-core bus protocol, and the bus protocol conversion system converts feedback with a 64-bit data bit width of the out-of-core bus protocol into feedback with a 32-bit data bit width of the in-core bus protocol.

The interfaces of the bus protocol conversion system also include clk_i, rst_ni, clk2en, exclusionary_o, etc., and the above interfaces are described in the following table (table 1):

TABLE 1

Referring to fig. 7, the states of the first state machine include a first state and a second state, and an initial state of the first state machine is the first state. The first state is used for indicating the first processing unit to select a signal from the second processing unit as feedback of the processing sub-module. If the effective feedback exists in the current third storage unit, and the request corresponding to the feedback is indicated to be a merging request in the second storage unit, the state of the first state machine jumps to a second state; the second state is used for indicating the first processing unit to select high-order data from feedback split by the sixth processing unit as feedback of the processing sub-module. At the next moment, the state of the first state machine unconditionally jumps to the second state.

Referring to fig. 8, the second state machine includes five states of a first state, a second state, a third state, a fourth state, and a fifth state.

First state: waiting for receiving a write operation request or a read operation request sent by the processor core side. If condition 1 is met (the request sent by the processor core does not need to be split, and the previously transmitted request is normally completed), the state machine jumps to the second state; if condition 2 is met (the processor core sent the request and the previously transmitted request completed normally), the second state will jump to the third state; if condition 5 is met (the previously transmitted request was in error, which is the 1 st cycle of the error signal), the second state machine jumps to the fifth state.

Second state: wait to receive the transmission completion signal hready of the previously undeployed request and wait to receive the write operation request or the read operation request sent from the processor core side at the same time. If the condition 1 is met, the second state machine jumps to the second state; if the condition 2 is met, the second state machine jumps to a third state; if the condition 5 is met, the second state machine jumps to a fifth state; if condition 4 is met (no request is issued by the processor core and the request for the previous transfer is normally completed), the second state machine jumps to the first state.

Third state: wait for the split request 1 st transmission complete signal hready before receiving. If condition 3 is met (the 1 st request transmission of the split request is normally completed, and a new request can be received), the second state machine jumps to a fourth state; if condition 5 is met, the second state machine jumps to the fifth state.

Fourth state: wait to receive the split request 2 nd transmission completion signal hready before and wait to receive a write operation request or a read operation request from the processor core side at the same time. If the condition 1 is met, the second state machine jumps to the second state; if the condition 2 is met, the second state machine jumps to a third state; if the condition 5 is met, the second state machine jumps to a fifth state; if condition 4 is met, the second state will jump to the first state.

Fifth state: waiting for the 2 nd cycle of the feedback error signal to be received. If condition 6 is met (the previous transmission request was in error, which is the 2 nd cycle of the error signal), the second state machine jumps to the first state.

The interfaces of the first processing module corresponding to the first request, the first feedback, the second request and the second feedback are described in the following table (table 2):

TABLE 2

The interfaces of the first processing module corresponding to the fifth request and the fourth feedback are described in the following table (table 3):

TABLE 3 Table 3

Where [ m: n ] represents the bit range of the signal from the nth bit to the mth bit, e.g., m_ wdata _o [63:0] represents the bit range of the signal from the 0 th bit to the 63 rd bit of the m_ wdata _o [63:0] interface.

The first memory cell, the second memory cell and the third memory cell are all first-in first-out memories (FIFOs, first Input First Output), the second memory cell and the third memory cell are common FIFOs (marked as FIFOs_A), and the first memory cell is a FIFO (marked as FIFOs_B) for introducing control signals.

Fifo_a carries a valid/ready handshake and does not support forward logic for enqueue to dequeue. Fifo_b introduces control signals on the basis of fifo_a. Since fifo_ A, FIFO _b internally is logically consistent with a common synchronous FIFO, only a valid/ready handshake signal of a layer of read-write FIFO is set outside fifo_ A, FIFO _b, the port of fifo_ A, FIFO _b is described in the following table (table 4):

TABLE 4 Table 4

In the first storage unit, when valid data exists in the second register, the signal value of the wvalid_i is binary 1; the signal of the rready _i interface can receive the request at the second processing module, and when the signal is in the external clock sampling enabling period, the signal value is binary 1; the first memory cell stores signals of m_we_o, m_be_o [3:0], m_addr_o [31:0], m_ wdata _o [63:0] and m_mr_o [0] therein.

In the second memory cell, when rready _i of the first memory cell and rvalid _o of the first memory cell are both binary 1, the signal value of wvalid_i is binary 1; the rready _i signal is consistent with rready _i transformation in the third storage unit, and if the signal corresponds to a merging request, rready _i is made to be binary 1 when the first state machine is RESP 2; if the non-merge request is corresponding, rready _i is made to be binary 1 when the first state machine is RESP1 and rvalid _o is 1 in the third memory unit; the second memory cell stores m_mr_o and m_addr [2] signals therein. The m_mr_o controls a second processing module, which is used for judging whether the request corresponding to feedback is a merging request or not; m_addr [2] controls the first processing module to select, as feedback data, whether the upper 32 bits of the 64 bits of the ninth data signal fed back or the lower 32 bits of the 64 bits of the ninth data signal fed back if the request corresponding to the feedback is a non-merging request.

When the signal value of the signal of the m_mr_o interface is binary 1, the fourth feedback output by the third storage unit is required to be split into first feedback and second feedback, and the first state machine has two states of RESP1 and RESP 2; when m_addr_o2 (the signal value of the 2 nd bit in the signal of the m_addr_o interface) is binary 0, then the lower 32 bits of the 64 bits of the ninth data signal are returned when the first state machine is RESP1, and the upper 32 bits of the 64 bits of the ninth data signal are returned when the first state machine is RESP 2; when m_addr_o2 is binary 1, the upper 32 bits of the 64 bits of the ninth data signal are returned when the first state machine is RESP1, and the lower 32 bits of the 64 bits of the ninth data signal are returned when the first state machine is RESP 2.

When the signal value of the signal of the m_mr_o interface is binary 0, the fourth feedback output by the third storage unit is not required to be split, and the first state machine has a state of RESP 1; when m_addr_o2 is binary 0, then returning the lower 32 bits of the 64 bits of the ninth data signal when the first state machine is RESP 1; when m_addr_o2 is binary 1, then the upper 32 bits of data in the 64 bits of the ninth data signal are returned when the first state machine is RESP 1.

In the third storage unit, the signal of wvalid_i has effective feedback in the fourth processing unit, and the signal value is binary 1 when the signal is in an external clock sampling enabling period; the signal rready _i is an input signal in the third storage unit, and if the signal corresponds to the merge request, rready _i is made to be binary 1 when the first state machine is RESP 2; if the non-merging request is corresponding, enabling rready _i to be binary 1 when the first state machine is RESP 1; the third memory cell has m_ rvalid _i and m_rdata_i [63:0] signals stored therein.

Referring to fig. 9, the first register is identified as s1, the second register is identified as s2, the first processing unit is identified as mr, in the 2 nd clock cycle in the clock signal clk, the access address of the first request is 0x3000_016c, the access address of the second request is 0x3000_0170, the first request and the second request do not satisfy the first preset condition, the signal value of mr_mr_o is binary 0, and the signal value of mr_mr_o of the binary 0 indicates that the first memory unit enqueues the request with the access address of 0x3000_016c; in the 3 rd clock cycle, the access address of the first request is 0x3000_0170, the access address of the second request is 0x3000_0174, the first request and the second request meet a first preset condition, at this time, the signal value of m_mr_o of mr is binary 1, the signal value of m_mr_o of mr of binary 1 characterizes that the first memory unit enqueues with a merged request of the first request with the access address of 0x3000_0170 and the second request with the access address of 0x3000_0174.

Referring to fig. 10, the processor core is identified as core, and valid feedback data exists in the third memory cell out_resp_fifo at 1 st clock cycle in the clock signal clk, and since the signal value of resp_addr2 in the second memory cell resp_fifo is binary 1 and the signal value of resp_mr is binary 0, the feedback data is the upper 32 bits (D2) of the 64 bits (D2D 1) of the feedback data. In the 2 nd clock cycle, there is valid feedback data in out_resp_fifo because the signal value of resp_mr in resp_fifo is binary 1 and the first state machine is in merge requesting the first feedback cycle, the feedback data is the data of the lower 32 bits (D3) of the 64 bits (D4D 3) of feedback. In the 3 rd clock cycle, there is valid feedback data in out_resp_fifo because the signal value of resp_mr in resp_fifo is binary 1 and the first state machine is in merge requesting the second feedback cycle, the feedback data is the data of the upper 32 bits (D4) of the 64 bits (D4D 3) of feedback.

The first register is used for registering the signals (the signal of m_we_i, the signal of m_be_i, the signal of m_addr_i and the signal of m_ wdata _i) in the request in the first register by one beat.

The second register is used for registering the signal in the request for one beat again, and then combining the first request and the second request into a third request.

The first processing unit is configured to combine the first request and the second request into a fourth request and send the fourth request to the first storage unit if the first request and the second request satisfy a first preset condition

The first storage unit is configured to cache consecutive fourth requests.

The second storage unit is used for sending a signal of whether the second bit addr [2] in the access address of the fourth request in the first storage unit, the first request and the second request are combined into m_mr_o of the fourth request to the second storage unit for storage and feeding back the sixth processing unit and the first state machine if the output of the first processing module and the input handshake of the second processing module in the request channel are successful.

The third memory unit is used to register a beat of the data phase related signal (the signal of HWDATA) to conform to the AHB-Lite protocol in order to cause the requested data phase to lag the address phase.

The second processing unit is configured to split a 64-bit request using an out-of-core bus protocol converted from a 32-bit request using an in-core bus protocol into two split requests using an out-of-core bus protocol according to an AHB-Lite protocol.

And summarizing and outputting all signals of the request of the out-of-core bus protocol according to the AHB-Lite bus protocol.

The fourth register is used for temporarily storing a feedback signal of the first split request in the split 2 times of split requests.

The third processing unit is used for selecting and splicing the split feedback corresponding to the two split requests, selecting the effective bits in the two split feedback, and splicing the effective bits into 1 feedback.

The fourth processing unit is configured to select a feedback signal, if the feedback signal is a feedback signal corresponding to an undetached request, select a feedback output sent by the bus of the AHB-Lite protocol, and if the feedback signal is a feedback signal corresponding to a detached request, select a combined feedback sent by the third processing unit to output.

The third storage unit is used for caching the feedback signals so that the fifth processing unit splits the fourth feedback into the first feedback and the second feedback.

The fifth processing unit is configured to split the fourth feedback into a first feedback and a second feedback.

The sixth processing unit is configured to select whether the data of the first feedback is the data of the high order of the fourth feedback or the data of the low order of the fourth feedback, and select whether the data of the feedback is the data of the feedback which is not combined with the data of the feedback corresponding to the request, or the data of the second feedback corresponding to the third request.

It should be noted that, the first data signal and the second data signal are both derived from the write data signal of the m_ wdata _i [31:0] interface (the write data signal input to the first processing module), for example, the write data signal input to the first processing module forms the first data signal and the second data signal through the first register and the second register respectively, the first register outputs the first data signal, and the second register outputs the second data signal; the fourth data signal is a write data signal input to the first memory unit by the first processing unit, the fifth data signal is a write data signal of an m_ wdata _o [63:0] interface (the write data signal output by the first processing module, namely, the write data signal output by the first memory unit), and the third data signal is a write data bus signal in the AHB-Lite protocol (the write data bus signal output by the second processing module);

the sixth data signal is a read data bus signal in the AHB-Lite protocol (namely, a read data bus signal input to the second processing module), the seventh data signal and the eighth data signal are both data signals of read feedback of the m_rdata_o [31:0] interface (data signals of read feedback output by the first processing module), and the ninth data signal is a data signal of read feedback input to the fifth processing unit by the third storage unit.

In the related art, a request using an in-core bus protocol under a first clock signal is converted into a request using an out-of-core bus protocol (AHB-Lite protocol) under the first clock signal, and then the request using the out-of-core bus protocol under the first clock signal is converted into a request using the out-of-core bus protocol under a second clock signal and sent to an external device, and under the condition of sending continuous requests, feedback corresponding to two adjacent requests needs to be separated by 2N (N is a positive integer) first clock cycles.

In the embodiment of the application, the fourth request is converted into the fifth request through the fifo_b, and then the fifth request is converted into the third request through the second processing module and sent to the external device, and under the condition of sending continuous requests, feedback corresponding to two adjacent requests needs to be separated by N first clock cycles.

Therefore, compared with the related art, the bus protocol conversion method provided by the embodiment of the application realizes faster clock frequency conversion, so that the feedback corresponding to the request is obtained faster.

Referring to fig. 11, a bus protocol conversion device provided by an embodiment of the present application is applied to a processor core in a system-in-chip, where the device includes:

A first obtaining module 301, configured to obtain a first request and a second request generated by the processor core, where the first request and the second request are both signal sets that use an intra-core bus protocol inside the processor core;

A merging module 302, configured to merge the first request and the second request into a third request, where the third request is a signal set using an out-of-core bus protocol outside the processor core, if the first request and the second request meet a first preset condition;

A sending module 303, configured to send the third request to an external device corresponding to the third request, so as to perform data reading and writing in the external device;

Optionally, the apparatus further includes:

The first determining module is configured to determine that the first request and the second request satisfy the first preset condition when the first data signal and the second data signal satisfy a second preset condition, the first access address of the first request and the second access address of the second request satisfy a third preset condition, the request type of the first request and the request type of the second request are the same, and the first request and the second request are both valid requests.

Optionally, the apparatus further includes:

And the second determining module is used for determining that the first data signal and the second data signal meet the second preset condition under the condition that each bit of the first data signal is a valid bit and each bit of the second data signal is a valid bit.

Optionally, the apparatus further includes:

A third determining module, configured to determine, when the 0 th bit and the 1 st bit of the first access address are binary 0, and the 0 th bit and the 1 st bit of the second access address are binary 0, and the address value of the 2 nd bit of the first access address and the address value of the 2 nd bit of the second access address are different, and the address values of the 3 rd bit to the 31 rd bit of the first access address and the address values of the 3 rd bit to the 31 rd bit of the second access address are the same, that the first access address and the second access address satisfy a third preset condition.

Optionally, the merging module 302 specifically includes:

a first combining sub-module for combining the first data signal and the second data signal into the third data signal;

and the determining submodule is used for determining the access address of the request generated earlier in the first request and the second request as the access address of the third request.

Optionally, the merging module 302 specifically includes:

a second merging sub-module, configured to merge the first request and the second request into a fourth request, where the fourth request is a signal set using the intra-core bus protocol, and a number of bits of a fourth data signal in the fourth request is a sum of a number of bits of the first data signal and a number of bits of the second data signal;

a storage sub-module for storing the data of the fourth request in a first-in first-out memory;

The first generation submodule is used for generating a second clock signal corresponding to the out-of-core bus protocol according to a preset control signal and the first clock signal corresponding to the in-core bus protocol; the clock frequency of the second clock signal is less than the clock frequency of the first clock signal;

the second generating submodule is used for sampling and outputting the data of the fourth request in the first-in first-out memory according to the second clock signal to generate a fifth request; the fifth request is a signal set using the in-core bus protocol, and the number of bits of a fifth data signal in the fifth request is equal to the number of bits of the fourth data signal;

and the third generation sub-module is used for generating the third request according to the fifth request.

Optionally, the first generating sub-module specifically includes:

and the generating unit is used for determining that the second clock signal is at the rising edge under the condition that the preset control signal is at the high level and the first clock signal is at the rising edge.

Optionally, the first clock cycle in which the first request is generated and the second clock cycle in which the second request is generated are adjacent.

Optionally, the number of bits of the first data signal and the number of bits of the second data signal are 32 bits, and the number of bits of the third data signal is 64 bits.

Optionally, the apparatus further includes:

the second acquisition module is used for acquiring third feedback corresponding to the third request; the third feedback is a signal set using the out-of-core bus protocol;

The splitting module is used for splitting the third feedback into a first feedback corresponding to the first request and a second feedback corresponding to the second request; the first feedback and the second feedback are both signal sets using the intra-core bus protocol;

a feedback module for sending the first feedback and the second feedback to the processor core;

Optionally, the splitting module specifically includes:

A conversion sub-module for converting the third feedback into a fourth feedback, the fourth feedback being a set of signals using the intra-core bus protocol;

the first splitting module is used for splitting the fourth feedback into the first feedback and the second feedback; the number of bits of the ninth data signal in the fourth feedback is the sum of the number of bits of the seventh data signal and the number of bits of the eighth data signal.

Optionally, the splitting module specifically includes:

and the second splitting module is used for splitting the sixth data signal into the seventh data signal and the eighth data signal.

In summary, in the embodiment of the present application, when the first request and the second request using the intra-core bus protocol inside the processor core satisfy the first preset condition, the first request and the second request are combined into the third request using the extra-core bus protocol outside the processor core, and the third request is sent to the external device corresponding to the third request, where the number of bits of the third data signal in the third request is the sum of the number of bits of the first data signal in the first request and the number of bits of the second data signal in the second request, and by sending the third request to the external device, the same effect that the first request and the second request are sent to the external device after protocol conversion is performed respectively is achieved, and the efficiency of sending the request is improved, so that the efficiency of bus protocol conversion is improved, and the problem that in the prior art, the efficiency of bus protocol conversion is low due to the fact that each request using the intra-core bus protocol of the processor core is converted into the request of the AHB-Lite protocol and sent to the external device is solved.

Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It is to be understood that the application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

The foregoing description of the preferred embodiments of the application is not intended to limit the application to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the application are intended to be included within the scope of the application.

The above description of the bus protocol conversion method, the device, the electronic equipment and the computer readable storage medium provided by the present application applies specific examples to illustrate the principles and the implementation of the present application, and the above examples are only used to help understand the method and the core idea of the present application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.

Claims

1. A bus protocol conversion method, for use with a processor core within a system-on-chip, the method comprising:

wherein the number of bits of the third data signal in the third request is the sum of the number of bits of the first data signal in the first request and the number of bits of the second data signal in the second request;

The first access address of the first request and the second access address of the second request are 32 bits, and the method further comprises:

and when each bit of the first data signal is a valid bit, each bit of the second data signal is a valid bit, the 0 th bit and the 1 st bit of the first access address are binary 0, the 0 th bit and the 1 st bit of the second access address are binary 0, the address value of the 2 nd bit of the first access address and the address value of the 2 nd bit of the second access address are different, the address values of the 3 rd bit to the 31 rd bit of the first access address and the address value of the 3 rd bit to the 31 st bit of the second access address are the same, and the request type of the first request and the request type of the second request are the same, and the first request and the second request are valid requests, the first request and the second request are determined to meet the first preset condition.

2. The method of claim 1, wherein the merging the first request and the second request into a third request comprises:

combining the first data signal and the second data signal into the third data signal;

and determining the access address of the request generated earlier in the first request and the second request as the access address of the third request.

3. The method of claim 1, wherein the merging the first request and the second request into a third request comprises:

Combining the first request and the second request into a fourth request, the fourth request being a set of signals using the intra-core bus protocol, a number of bits of a fourth data signal in the fourth request being a sum of a number of bits of the first data signal and a number of bits of the second data signal;

storing the fourth requested data in a first-in first-out memory;

generating a second clock signal corresponding to the out-of-core bus protocol according to a preset control signal and a first clock signal corresponding to the in-core bus protocol; the clock frequency of the second clock signal is less than the clock frequency of the first clock signal;

Sampling and outputting the data of the fourth request in the first-in first-out memory according to the second clock signal to generate a fifth request; the fifth request is a signal set using the in-core bus protocol, and the number of bits of a fifth data signal in the fifth request is equal to the number of bits of the fourth data signal;

and generating the third request according to the fifth request.

4. The method of claim 3, wherein generating the second clock signal corresponding to the out-of-core bus protocol based on the preset control signal and the first clock signal corresponding to the in-core bus protocol comprises:

and determining that the second clock signal is at the rising edge under the condition that the preset control signal is at the high level and the first clock signal is at the rising edge.

5. The method of claim 1, wherein a first clock cycle at which the first request is generated and a second clock cycle at which the second request is generated are adjacent.

6. The method of claim 1, wherein the number of bits of the first data signal and the number of bits of the second data signal are each 32 bits, and the number of bits of the third data signal is 64 bits.

7. The method according to claim 1, wherein the method further comprises:

Acquiring a third feedback corresponding to the third request; the third feedback is a signal set using the out-of-core bus protocol;

Splitting the third feedback into a first feedback corresponding to the first request and a second feedback corresponding to the second request; the first feedback and the second feedback are both signal sets using the intra-core bus protocol;

sending the first feedback and the second feedback to the processor core;

8. The method of claim 7, wherein splitting the third feedback into a first feedback corresponding to the first request and a second feedback corresponding to the second request comprises:

converting the third feedback to a fourth feedback, the fourth feedback being a set of signals using the intra-core bus protocol;

Splitting the fourth feedback into the first feedback and the second feedback; the number of bits of the ninth data signal in the fourth feedback is the sum of the number of bits of the seventh data signal and the number of bits of the eighth data signal.

9. The method of claim 7, wherein splitting the third feedback into a first feedback corresponding to the first request and a second feedback corresponding to the second request comprises:

splitting the sixth data signal into the seventh data signal and the eighth data signal.

10. A bus protocol conversion apparatus for use with a processor core within a system-on-chip, the apparatus comprising:

The first access address of the first request and the second access address of the second request are 32 bits, and the apparatus further comprises:

A first determining module, configured to determine that, when the first data signal and the second data signal satisfy a second preset condition, and a first access address of the first request and a second access address of the second request satisfy a third preset condition, and a request type of the first request and a request type of the second request are the same, and the first request and the second request are both valid requests, the first request and the second request satisfy the first preset condition;

a second determining module, configured to determine that the first data signal and the second data signal meet the second preset condition when each bit of the first data signal is a valid bit and each bit of the second data signal is a valid bit;