CN104380274A - Optimized link training and management mechanism - Google Patents

Abstract

In one embodiment, an aggregation protocol stack can be used to unify communications from a first communication protocol to a second communication protocol to provide data transfer across a physical interconnect. This stack can be incorporated into an apparatus comprising a protocol stack for a first communication protocol including a transaction and link layer and a Physical unit coupled to the protocol stack to provide communication between the apparatus and a device coupled to the apparatus via a physical link. This PHY unit may include physical unit circuitry according to the second communication protocol. Other embodiments are described and claimed.

Description

Optimized link training and management mechanism

Technical Field

Embodiments relate to interconnect technology.

background

In order to provide communication between different devices within a system, some type of interconnection mechanism is used. Depending on the system implementation, a wide variety of such interconnections are possible. Often in order for two devices to be able to communicate with each other, they share a common communication protocol.

A typical communication protocol for communication between devices within a computer system is the Peripheral Component Interconnect Express (PCI Express ^™ (PCIe™)) communication protocol based on a link based on the PCI Express ^™ Specification Base Specification Version 3.0 (published on November 18, 2010) (hereinafter referred to as the PCIe ^™ specification ⁾ . This communication protocol is an example of a load/store input/output (IO) interconnect system. Communication between the devices is typically performed serially at very high speeds according to this protocol. When the PCIe ^™ communication protocol was developed in the context of desktop computers, various parameters for this protocol were developed for the purpose of achieving maximum performance without regard to power efficiency. As a result, many of its features cannot be reduced to a lower power solution that can be incorporated into a mobile system.

In addition to these power issues with conventional load/store communication protocols, existing link management schemes are typically very complex and involve a large number of states, resulting in a lengthy process of performing transitions between states. This is due in part to existing link management mechanisms, which were developed to appreciate a variety of different form factor requirements such as connectors, different system incorporations, etc. One such example is link management according to the PCIe ^™ communication protocol.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a high-level block diagram of a protocol stack for a communication protocol according to an embodiment of the present invention.

FIG. 2 is a block diagram of a system on chip (SoC) according to an embodiment of the present invention.

FIG. 3 is a block diagram of a physical unit according to another embodiment of the present invention.

FIG. 4 is a block diagram showing further details of a protocol stack according to an embodiment of the present invention.

5 is a state diagram for a link training state machine, which can be part of a link manager according to an embodiment of the present invention.

FIG. 6 is a flow chart of various states for a sideband mechanism according to an embodiment of the present invention.

FIG. 7 is a flow chart of a method according to an embodiment of the present invention.

FIG. 8 is a block diagram of components present in a computer system according to an embodiment of the present invention.

9 is a block diagram of an example system with which embodiments can be used.

DETAILED DESCRIPTION

Embodiments may provide an input/output (IO) interconnect technology having a low power, load/store architecture and particularly suitable for use in mobile devices including cellular phones such as smartphones, tablet computers, e-readers, Ultrabooks ^™ , and the like.

In various embodiments, a protocol stack for a given communication protocol can be used with physical units for different communication protocols or at least one physical (PHY) unit that is different from the physical unit for a given communication protocol. The physical unit includes both a logical layer and a physical or electrical layer that provides the actual, physical communication of information signals over an interconnect, such as a link linking two independent semiconductor dies, which can be two semiconductor dies within a single integrated circuit (IC) package or separate packages coupled, for example, via circuit board routing, traces, etc. In addition, the physical unit can perform framing/deframing of data packets, perform link training and initialization, and process data packets for reception from or delivery to the physical interconnect.

Although different implementations are possible, in one embodiment, the protocol stack may have a conventional personal computer (PC) based communication protocol (such as the Peripheral Component Interconnect Express (PCI) Express ^TM (PCIe ^TM )) communication protocol according to the PCI Express ^TM Specification Base Specification Version 3.0 (published November 18, 2010) (hereinafter referred to as the PCIe ^TM specification), a further version of the application protocol extension, or another such protocol, while the physical unit is not based on the PCIe ^TM communication protocol. For the purpose of achieving low power operation, this physical unit can be specially designed to allow a substantially unchanged PCIe ^TM upper protocol stack to be incorporated with this low power physical circuit. In this way, the broad traditional basis of the PCIe ^TM communication protocol can be utilized for ease of incorporation into portable and other non-PC based form factors that operate at low power. While the scope of the present invention is not limited in this regard, in one embodiment, this physical unit may be a physical unit adapted by a mobile platform, such as the so-called M-PHY according to the M-PHY Specification Version 1.00.00 of the Mobile Industry Processor Interface (MIPI) Alliance (which is a group setting standards for mobile computing devices) - February 8, 2011 (MIPI Board approved on April 28, 2011) (hereinafter referred to as the MIPI Specification). However, other low-power physical units (such as according to other low-power specifications such as for coupling individual dies within a multi-chip package together), or customized low-power solutions can be used. As used herein, the term "low power" means being at a power consumption level lower than conventional PC systems, and it can be applied to a wide variety of mobile and portable devices. As an example, "low power" may be a physical unit that consumes less power than a conventional PCIe ^TM physical unit.

Thus, by aggregating the legacy PCIe ^™ protocol stack with different types of physical units, a large number of reused legacy components developed for PCIe ^™ can be used to incorporate into mobile or other portable or low-power platforms.

Embodiments may also take advantage of the recognition that existing load/store IO technologies, particularly PCIe ^™ , are designed with the goal of achieving maximum performance where power efficiency is not a primary concern and therefore will not scale down to low power applications. By combining portions of a conventional load/store protocol stack with a low power designed physical unit, embodiments may retain the performance advantages of PCIe ^™ while optimizing for power at the device and platform level.

As such, embodiments may be software compatible with the ubiquitous PCIe ^™ architecture, which has a large legacy base. In addition, embodiments may also enable direct PHY reuse of mobile design PHYs, such as M-PHY. In this way, low active and idle power can be achieved with efficient power/bit transmitted and an approach that is electromagnetic interface/radio frequency interface (EMI/RFI) friendly, because the PHY can operate at a clock rate that does not interfere with the associated radio (because the harmonics of the clock rate used for the PHY do not interfere with the conventional radio frequencies (e.g., 1.8, 1.9, 2.4 gigahertz (GHz)) or other such radio frequencies at which typical radio solutions operate).

Embodiments may further provide architectural improvements that implement an optimized link training and management mechanism (LTSSM); optimized flow control and retry buffering and management mechanisms; an architectural protocol for changing link operating modes; fast hardware support for device state preservation and recovery; and a unified sideband mechanism for link management with optional in-band support.

In various embodiments, the PCIe ^TM transaction and data link layers can be implemented as part of a protocol stack with limited modifications to account for different link speeds and asymmetric links. In addition, modified link training and management can be provided to include support for multi-channel communications, asymmetric link configurations, sideband unification, and dynamic bandwidth scalability. Embodiments may further provide support for bridging between existing PCIe ^TM- based and non-PCIe ^TM- based logic and circuits such as M-PHY logic and circuits.

This layered approach enables existing software stacks (e.g., operating systems (OS), virtual machine managers, and drivers) to run seamlessly on different physical layers. The impact on the data link and transaction layers is minimized and can include updating related timers to update response frequencies, replay timers, etc.

Therefore, each embodiment can limit some flexibility provided in PCIe ^TM system, because this flexibility can create some complexity in both PCIe ^TM system and other systems in some cases. Indeed, because both protocols provide great flexibility to realize plug-and-play capability. On the contrary, each embodiment can customize the solution of minimizing the amount of design flexibility, because when being incorporated into a given system (e.g., a system on a chip (SoC) interconnected with another integrated circuit (IC)), a known and fixed configuration occurs. Because it is known in terms of the precise configuration of the implementation, when both SoC and the connected devices are attached in the platform, such as soldered to the circuit board of the system, these devices do not need plug-and-play capability, and therefore may not need PCIe ^TM or other PC-based communication protocols inherent, so that different devices can be seamlessly incorporated into the system with plug-and-play capability. Greater flexibility.

As an example, the SoC can act as a root complex implemented in a first IC and coupled to a second IC which can be a radio solution, which can include one or more of a plurality of wireless communication devices. Such devices can range from low power short range communication systems such as those according to the Bluetooth ^™ specification, local area wireless communications such as so-called WiFi ^™ systems according to a given Institute of Electrical and Electronics Engineering (IEEE) 802.11 standard, to high power wireless systems such as given cellular communication protocols such as 3G or 4G communication protocols.

Referring now to FIG. 1 , a high-level block diagram of a protocol stack for a communication protocol according to an embodiment of the present invention is shown. As shown in FIG. 1 , the stack 100 may be a combination of software, firmware, and hardware within a semiconductor component (such as an IC) for providing processing for data communication between the semiconductor device and another device coupled thereto. In the embodiment of FIG. 1 , a high-level view starting with high-level software 110 is shown, which may be various types of software executed on a given platform. Such high-level software may include operating system (OS) software, firmware, application software, etc. Data to be transmitted via interconnect 140 can be passed through the layers of the protocol stack, generally shown in FIG. 1 , where interconnect 140 may be a given physical interconnect coupling the semiconductor device to another component. As seen, portions of this protocol stack may be portions of a conventional PCIe ^TM stack 120, and may include a transaction layer 125 and a data link layer 128. Typically, the transaction layer 125 is used to generate transaction layer packets (TLPs) that may be request or response-based packets separated by time, thereby allowing the link to carry other services while the target device collects data for the response. The transaction layer further handles credit-based flow control. Thus, the transaction layer 125 provides an interface between the processing circuitry of the device and the interconnect architecture, such as the data link layer and the physical layer. In this regard, the primary responsibilities of the transaction layer are the assembly and disassembly of data packets (i.e., transaction layer packets (TLPs)) and handling credit-based flow control.

The data link layer 128 can then order the TLPs generated by the transaction layer and ensure reliable delivery (including handling error checking) and acknowledgment processing of the TLPs between the two endpoints. Thus, the link layer 128 acts as an intermediate stage between the transaction layer and the physical layer and provides a reliable mechanism for exchanging TLPs between the two components over a link. One side of the link layer receives the TLPs assembled by the transaction layer, applies an identifier, calculates and applies an error detection code (e.g., a cyclic recovery code (CRC)), and submits the modified TLPs to the physical layer for transmission across the physical link to an external device.

After processing in the data link layer 128, the data packet can be transmitted to the PHY unit 130. Generally, the PHY unit 130 may include a low power PHY 134, which may include both a logical layer and a physical (including electrical) sublayer. In one embodiment, the physical layer represented by the PHY unit 130 physically transmits the data packet to the external device. The physical layer includes a transmission section that prepares outgoing information for transmission and a receiver section that identifies and prepares the received information before passing it to the link layer. The symbols that are serialized and transmitted to the external device are supplied to the transmitter. The serialized symbols from the external device are supplied to the receiver, and the receiver converts the received signal into a bit stream. The bit stream is deserialized and supplied to the logic sub-block.

In one embodiment, the low power PHY 134 (which may be a given low power PHY specifically developed or adapted from another PHY such as an M-PHY) may provide processing for packetized data for transmission along the interconnect 140. As further seen in FIG1 , a link training and management layer 132 (also referred to herein as a link manager) may also be present within the PHY unit 130. In various embodiments, the link manager 132 may include specific logic that may be implemented according to another communication protocol such as the PCIe ^™ protocol and proprietary logic that handles the interface between the conventional and different protocols of the PCIe ^™ protocol stack described above.

In the embodiment of Fig. 1, interconnect 140 can be implemented as differential line pairs, and differential line pairs can be two pairs of unidirectional lines. In some embodiments, multiple groups of differential pairs can be used to increase bandwidth. It should be noted that according to the PCIe ^TM communication protocol, the number of differential pairs in each direction is required to be the same. However, according to various embodiments, different numbers of pairs can be provided in each direction, which allows operation to be more efficient and lower power. The entire aggregated stack and link 140 can be referred to as mobile fast PCIe ^TM interconnect or link. Although shown at this high level in the embodiment of Fig. 1, it is to be understood that the scope of the present invention is not limited thereto. That is, it is to be understood that the view shown in Fig. 1 is only about the protocol stack from the transaction layer through the physical layer and the high-level software, and various other circuits of SoC or other semiconductor devices including this stack are not shown.

Referring now to FIG2 , a block diagram of a SoC according to an embodiment of the present invention is shown. As shown in FIG2 , SoC 200 can be any type of platform for implementation in various types of SoCs, ranging from relatively small low-power portable devices such as smart phones, personal digital assistants (PDAs), tablet computers, notebooks, Ultrabooks ^™ , etc. to more advanced SoCs that can be implemented in high-level systems.

As seen in FIG. 2 , SoC 200 may include one or more cores 210 ₀ -210 _n . Thus, in various embodiments, there may be a multi-core SoC, all of which may be homogeneous cores with a given architecture, such as in-order or out-of-order processors. Or there may be heterogeneous cores, such as some relatively small low-power cores, such as cores with an in-order architecture; with the presence of additional cores, which may have a larger and more complex architecture, such as an out-of-order architecture. The protocol stack enables data communication between one or more of these cores and other components of the system. As seen, this stack can include software 215, which may be higher-level software (such as an OS, firmware) and application-level software executed on one or more cores. In addition, the protocol stack includes a transaction layer 220 and a data link layer 230. In various embodiments, these transaction and data link layers may have a given communication protocol such as a PCIe ^TM protocol. Of course, in other embodiments, there may be layers of different protocol stacks such as according to a universal serial bus (USB) protocol stack. Moreover, in some embodiments, the low-power PHY circuit described herein can be multiplexed with an existing replacement protocol stack.

Still referring to Figure 2, this protocol stack can then be coupled to a physical unit 240, which can include multiple physical units capable of providing communication via multiple interconnects. In one embodiment, the first physical unit 250 can be a low-power PHY unit, which in one embodiment can correspond to an M-PHY according to the MIPI specification, for providing communication via a main interconnect 280. In addition, there can be a sideband (SB) PHY unit 244. In the embodiment shown, this sideband PHY unit can provide communication via a sideband interconnect 270, which can be a unified sideband for providing certain sideband information, for example, at a data rate slower than the main interconnect 280 coupled to the first PHY 250. In some embodiments, the various layers of the protocol stack can have separate sidebands coupled to this SB PHY 244 to enable communication along this sideband interconnect.

In addition, the PHY unit 240 may further include an SB link manager 242 that can be used to control the SB PHY 244. In addition, a link training and status manager 245 may be present and can be used to adapt a protocol stack having a first communication protocol to the first PHY 250 having a second communication protocol, and provide overall control of the first PHY 250 and the interconnect 280.

As further seen, various components may be present in the first PHY 250. More specifically, transmitter and receiver circuits (i.e., TX 253 and RX 254) may be present. In general, such circuits may be used to perform serialization operations, deserialization operations, and transmission and reception of data via the main interconnect 280. A save state manager 251 may be present and may be used to save configuration and other state information about the first PHY 250 when it is in a low power state. Also, an encoder 252 may be present for performing line encoding, for example, according to an 8b/10b protocol.

2 , there may be a mechanical interface 258. This mechanical interface 258 may be a given interconnect for providing communications from the root complex 200, and more specifically to/from the first PHY 250 via the primary interconnect 280. In various embodiments, this mechanical connection can utilize pins of a semiconductor device such as a ball grid array (BGA) or other surface mount, or through hole connection plating.

In addition to these primary communication mechanisms, additional communication interfaces may utilize a low power serial (LPS) PHY unit 255, which couples between the core 210 and one or more off-chip devices 260a-c via a separate stack including a software layer 216, a transaction layer 221, and a link layer 231. The off-chip devices may be various low data rate peripherals such as sensors, accelerometers, temperature sensors, global positioning system (GPS) circuits, compass circuits, touch screen circuits, keyboard circuits, mouse circuits, etc.

Note that in various embodiments, either sideband interconnect 270 or main interconnect 280 can be coupled between SoC 200 and another semiconductor component (eg, another IC such as a multi-band radio solution).

Again, while the illustration of FIG. 2 is at a relatively high level, variations are possible. For example, multiple low power PHYs may be provided to enable higher rate data communications, for example, via multiple channels, where each channel is associated with a separate PHY. Referring now to FIG. 3 , a block diagram of a physical unit according to another embodiment of the present invention is shown. As shown in FIG. 3 , the physical unit 300 includes a link training and state manager 310. This state manager may be as described above, and can be a logical set for enabling a protocol stack having a first communication protocol to interface with a physical unit having a second (e.g., different) communication protocol.

As further seen in FIG. 3 , the link training and state manager 310 can communicate with multiple M-PHYs 320 ₀ -320 _n . By providing more than one such PHY, higher rate data communications can be performed. It is noted that while each M-PHY shown in FIG. 3 may include some amount of logic for enabling its individual independent communications to occur, overall control of the communications of these different M-PHYs may be via the link training and state manager 310. Moreover, it is to be understood that while multiple M-PHYs are shown in FIG. 3 , in other embodiments, multiple PHY units of another type can exist, and additional multiple heterogeneous PHY units can be provided. It is noted that each M-PHY unit can be used as part of a unique logical link, or used in a group, where the group is associated with a single logical link. Each device can typically consume a single logical link, but in some embodiments a single physical device can consume multiple logical links, for example, to provide dedicated link resources for different functions of a multi-function component.

Referring now to FIG4 , shown is a block diagram illustrating further details of a protocol stack according to an embodiment of the present invention. As shown in FIG4 , the stack 400 includes various layers, including: a transaction layer 410, a data link layer 420, and a physical layer 430. As described above, these different layers can be configured using the conventional transaction and data link portions of the PCIe ^TM protocol stack or a modified version of such a stack to accommodate interaction between these layers having the first communication protocol and a physical layer having another communication protocol, which in the embodiment of FIG4 may be M-PHY according to the MIPI specification.

As seen in FIG4 , with respect to the transmission direction of information transmitted from the protocol stack 400, incoming information to the protocol stack, for example, from other circuits of the SoC (such as a core or other processing logic) is received in a transmission packet assembler 412 of the transaction layer that typically combines control and data paths to form TLPs. After being assembled into transmission packets (transmission packets can be packets of, for example, 1 to 4096 bytes (or with a smaller maximum allowed size, such as 128 or 256) in various embodiments), the assembled packets are provided to a flow controller 414, which determines whether sufficient flow control credits are available based on the number of next (one or more) TLPs queued for transmission, and controls the injection of the packets into the data link layer 420. More specifically, these injected packets are provided to an error detector and sequencer 422, which in one embodiment can generate a TLP sequence number and LCRC. As further seen, the data link layer 420 further includes a transport message mechanism 426, which in turn generates DLLPs for link management functions and is coupled to a data link transport controller 425, which is a controller function for flow control and data link integrity (ACK/NAK) mechanisms; note that this can be subdivided so that these functions are implemented using different logic blocks.

As further seen, the processed packets are provided to the retry buffer 424, which holds a copy of each TLP until acknowledged by a component on the other side of the link, noting that in practice this can be implemented using buffers further up the stack (in or above the assembler 412), and they can be stored in corresponding entries until selected for transmission to the physical layer 430 via the data/message selector 428. In general, the transaction and data link layers described above can operate according to conventional PCIe ^™ protocol stack circuitry, with certain modifications described further below.

Conversely with respect to the physical layer 430, much more modification of certain logical components of this layer (such as modified according to the PCIe ^TM protocol stack) may occur and be used to provide an interface to the actual physical portion of a physical unit having another communication protocol. As seen, incoming data packets may be applied to a frame generator 432, which adds physical layer frame symbols and generates frames for the data packets, and provides them to a bandwidth/position mapper 434, which shifts bytes in the data path to generate the required alignment for external transmissions to adjust the data path width as necessary, and is then coupled to a trainer and hop sequencer 436 that may be used to perform link training and hop sequencing. As seen, the frame generator 432, trainer/sequencer 436, and data/sequence selector 438 may all be coupled to a physical layer transmission controller 435, which is the transceiver portion of the LTSSM and related logic. Block 436 is the logic for generating physical layer transmissions such as training sets (TS) and hop sequencing sets. Thus, the framed data packets can be selected and provided to the physical circuitry to perform encoding, serialization, and driving the serialized signals corresponding to the processed data packets onto the physical interconnect. In one embodiment, the mapping of the symbol differences between different communication protocols can be performed in the frame generator 432.

As can be seen, multiple individual channels or lanes can be provided for this physical interconnect. In the embodiment shown, each physical channel or lane can include its own independent PHY unit transmission circuit _4450-445j , each of which can be part of an M-PHY unit according to the MIPI specification in one embodiment. As _described herein, unlike PCIe ^™ , where the number of transmitters and receivers matches, there can be different numbers of transmitters and receivers. Therefore, as can be seen, each transmission circuit 445 can include an encoder for encoding symbols according to 8b/10b encoding, a serializer for serializing the encoded symbols, and a driver for driving the signal onto the physical interconnect. As further seen, each lane or lane can be associated with a logic unit _4400-440j , which can be a logic circuit according to the MIPI specification for M-PHY, for managing physical communication _via the corresponding lane.

It is noted that these multiple channels can be configured to operate at different rates, and embodiments may include different numbers of such channels. In addition, there may be different numbers of channels and channel speeds in the transmit and receive directions. Thus, while a given logic unit 440 controls the operation of a corresponding channel of a PHY 445, it is understood that the physical layer transmission controller 435 may be used to control the overall transmission of information via the physical interconnect. It is noted that in some cases, some very basic functions are performed by different logic associated with each channel; for situations where channels can be assigned to more than a single link, multiple LTSSM instances may be provided; for trained links, there is a single LTSSM in each component that controls both the transceiver and receiver sides. This overall control can include power control, link speed control, link width control, initialization, etc.

Still referring to FIG. 4 , incoming information received via the physical interconnect can similarly be passed through the physical layer 430, the data link layer 420, and the transaction layer 410 via the receiving mechanisms of these layers. In the embodiment shown in FIG. 4 , each PHY unit can further include a receiving circuit, namely a receiving circuit 455 ₀ -455 _{k ,} which in the embodiment _shown can exist for each lane of the physical link. It should be noted that in this embodiment, the number of receiver circuits 455 and transmitter circuits 445 is different. As seen, this physical circuit can include an input buffer for receiving incoming information, a deserializer for deserializing the information, and a decoder that can be used to decode symbols transmitted in 8b/10b encoding. As further seen, each lane or channel can be associated with a logical unit 450 ₀ -450 _{k , which} can be a logical circuit according to a given specification (e.g., a MIPI specification for M-PHY) for managing physical communication via the corresponding lane.

The decoded symbols may then be provided to the logic portion of the physical layer 430, which as seen may include a resilient buffer 460, wherein the resilient buffer accommodates clock differences between this component and another component on the link; note that in various embodiments its location may be shifted to, for example, below the 8b/10b decoder, or combined with a channel deskew buffer, and store incoming decoded symbols. This information may then be provided to a width/position mapper 462, from which it may be provided to a channel deskew buffer 464 that performs deskew across multiple channels, and for a multi-channel scenario, the buffer 464 may be able to handle differences in signal skew between channels to realign bytes. The information via deskew may then be provided to a frame processor 466, which may eliminate frames present in the incoming information. As seen, a physical layer receive controller 465 may be coupled to and control the resilient buffer 460, the mapper 462, the deskew buffer 464, and the frame processor 466.

Still referring to FIG4, the recovered data packets can be provided to a receive message mechanism 478 and an error detector, sequence checker, and link level retry (LLR) requester 475. This circuit can perform error correction checks on incoming data packets, such as by performing a CRC checksum operation, performing an ordering check, and requesting a link level retry for erroneously received data packets. Both the receive message mechanism 478 and the error detector/requester 475 can be under the control of a data link receive controller 480.

Still referring to FIG4, the packets processed in unit 475 may thus be provided to transaction layer 410, and more specifically to flow controller 485, which performs flow control on the packets to provide them to packet interpreter 495. Packet interpreter 495 performs interpretation of the packets and forwards them to a selected destination, such as a given core or other logic circuitry of the receiver. Although shown at this high level in the embodiment of FIG4, it is to be understood that the scope of the present invention is not limited in this regard.

It should be noted that PHY440 can use the same 8b/10b encoding supported by PCIe ^TM for transmission. The 8b/10b encoding scheme provides special symbols that are different from the data symbols used to represent characters. These special symbols can be used for various link management mechanisms described in the physical layer chapter of the PCIe ^TM specification. The use of additional special symbols by M-PHY is described in the MIPI M-PHY specification. Embodiments can provide mapping between PCIe ^TM and MIPI M-PHY symbols.

Referring now to Table 1, an exemplary mapping of PCIe ^TM symbols to M-PHY symbols is shown in accordance with one embodiment of the present invention. Thus, this table illustrates the mapping of special symbols for the aggregated protocol stack in accordance with one embodiment of the present invention.

Table 1

The 8b/10b decoding rules are the same as those defined for the PCIe ^TM specification. The only exception to the 8b/10b rules is when a TAIL OF BURST is detected, which is a specific sequence that violates the 8b/10b rules. According to various embodiments, the physical layer 430 can provide notification to the data link layer 420 of any errors encountered during the TAIL OF BURST.

In one embodiment, the framing of symbols and application to lanes can be as defined in the PCIe ^TM specification, while data scrambling can be the same as defined in the PCIe ^TM specification. However, it is noted that data symbols transmitted in the PREPARE phase of communications according to the MIPI specification are not scrambled.

With respect to link initialization and training, the link manager may provide configuration and initialization of a link that may include one or more channels as discussed above, support for normal data transfer, support for state transitions when recovering from link errors, and port restart from low power states.

To enable such operations, the following physical and link-related characteristics may be known in advance (eg, prior to initialization): PHY parameters (eg, including initial link speed and supported speeds; and initial link width and supported link widths).

In one embodiment, training may include various operations. Such operations may include: initializing the link with the configured link speed and width, per-channel bit lock, per-channel symbol lock, channel polarity, and channel-to-channel anti-torsion deskew for multi-channel links. In this way, training can discover channel polarity and perform adjustments accordingly. However, it is noted that link training according to embodiments of the present invention may not include link data rate and width negotiation, link speed and width degradation. In contrast, as described above, once the link is initialized, both entities know the initial link width and speed in advance, and therefore can avoid the time and computational costs associated with negotiation.

PCIe ^TM ordered sets can be used with the following modifications: TS1 and TS2 ordered sets are used to facilitate IP reuse, but many fields of the training ordered sets are ignored. Also, fast training sequences are not used. Electrical idle ordered sets (EIOS) can be retained to facilitate IP reuse, as can hopping OS, but the frequency of hopping OS can be at a different speed than according to the PCIe ^TM specification. Also note that the data stream ordered sets and symbols can be the same as according to the PCIe ^TM specification.

The following events are transmitted to facilitate link training and management: (1) Present, which can be used to indicate the presence of an active PHY at the remote end of the link; and (2) Configuration Ready, which is triggered to indicate completion of PHY parameter configuration and that the PHY is ready to operate with a configured profile. In one embodiment, the system information can be transmitted via a unified sideband signal in accordance with an embodiment of the present invention.

For the purpose of controlling the electrical idle condition, the PHY has a TAIL OF BURST sequence for indicating that the transmitter is entering the electrical idle state. In one embodiment, the sideband channel can be used to signal the exit from electrical idle. Note that this indication can be coupled with the PHY suppress break mechanism. The OPENS sequence of symbols can be transmitted as EIOS to indicate the entry into the electrical idle state.

In some embodiments, a Fast Training Sequence (FTS) is not defined. Instead, the PHY may use a specific physical layer sequence for exiting from the shutdown/sleep state to a burst state that can be used to address bit lock, symbol lock, and channel-to-channel deskew. A small amount of FTS can be defined as a symbol sequence for robustness. The start of a data stream ordered set may be according to the PCIe ^TM specification, as is link error recovery.

Regarding link data rates, in various embodiments, the initial data rate of the link initialization may be a predetermined data rate. A data rate change from this initial link speed may occur by going through a recovery state. Embodiments may support asymmetric link data rates, where different data rates in opposite directions are allowed.

In one embodiment, the supported link widths may be in accordance with those in the PCIe ^TM specification. Additionally, as described above, because the link widths are predetermined, embodiments may not support protocols for negotiating link widths, and thus link training may be simplified. Of course, embodiments may provide support for asymmetric link widths in opposite directions. At the same time, the initial link width and initial data rate configured for each direction of the link may be known in advance before training begins.

With respect to the physical ports of the PHY unit, the ability of an xN port to form an xN (where N can be 32, 16, 12, 8, 4, 2, and 1) link as well as an x1 link is not required, and the ability of an xN port to form an arbitrary link width between N and 1 is optional. An example of this behavior includes an x16 port, which can be configured as only one link, but the width of the link can be configured to the required width of x12, x8, x4, x2, as well as x16 and x1. In this way, designers seeking to implement devices using a protocol stack according to an embodiment of the present invention can connect ports between these components in a manner that allows two different components to meet the above requirements. If ports between components are connected in a manner that does not conform to the intended use defined by the component's port description/data sheet, the behavior is undefined.

Additionally, the ability to split a port into two or more links is not disabled. If such support is appropriate for a given design, the port can be configured to support a specific width during training. An example of this behavior would be a x16 port that could be configured with two x8 links, 4 x4 links, or 16 x1 links.

When 8b/10b encoding is used, the unambiguous lane-to-lane deskew mechanism as in the PCIe ^TM specification is the COM symbol of the ordered set received during the training sequence or SKP ordered set, since the ordered set is transmitted simultaneously on all lanes of the configured link. The MK0 symbol transmitted during the sync sequence of the HS-BURST can be used for lane-to-lane deskew.

As briefly described above with reference to Figure 4, link training and state manager can be configured to perform various operations, including the upper layer of the PCIe ^TM protocol stack being adapted to the lower PHY unit of different protocols. In addition, this link manager can configure and manage single or multiple channels, and can include support for the following: symmetric link bandwidth, compatibility of the state machine with PCIe ^TM affairs and data link layer, link training, optional symmetric link down state and control of the sideband signal for robust communication. Therefore, the embodiment provides the implementation of PCIe ^TM affairs and data link layer with limited modification to account for different link speeds and asymmetric links. In addition, using the link manager according to an embodiment of the present invention, it is possible to realize support for multi-channel, asymmetric link configuration, sideband unification and dynamic bandwidth scaling, while further realizing the bridging between different communication protocol layers.

Referring now to FIG. 5 , a state diagram 500 for a link training state machine is shown, which can be part of a link manager according to an embodiment of the present invention. As shown in FIG. 5 , link training can begin in a detection state 510. This state occurs at power-on reset and is applicable to both upstream and downstream ports. After reset is complete, all configured channels can transition to a given state, the HIBERN8 state, in which each end of the link can signal using a sideband channel, such as via a PRESENCE signal. Note that in this detection state, a high impedance signal, i.e., a DIF-Z signal, can be driven on all channels.

Thus, when the PRESENCE event is signaled and received, control passes from the Detect State 510 to the Configuration State 520 and drives this high impedance on all configured lanes. In the Configuration State 520, the PHY parameters can be configured, and once completed on all configured lanes at each end of the link, a configuration ready signal (CFG-RDY) can be indicated, for example, using a sideband interconnect, while maintaining high impedance on all lanes.

Therefore, once this configuration ready indication is sent and received via the sideband interconnect, control is passed to the shutdown state 530. That is, in this L0.STALL state, the PHY transitions to the STALL state and continues to drive high impedance on all configuration channels. As can be seen, depending on whether data is available for transmission or reception, control can be passed to the active state L1 (state 530), the low power state (L1 state 540), the deep low power state (L1.OFF state 545) or returned to the configuration state 520.

Thus, in the STALL state, the negative drive signal DIF-N can be transmitted on all configured channels. Then, when directed by the initiator, the BURST sequence can be started. Thus, after the MARKER0 (MK0) symbol is transmitted, control passes to the active state 530.

In one embodiment, the receiver may detect the exit from the STALL state on all configured lanes and perform bit lock and symbol lock according to, for example, the MIPI specification.In an embodiment with a multi-lane link, this MK0 symbol may be used to establish lane-to-lane deskew.

Conversely, when directed to a low power state (i.e., L1 state 540), all configured channels may transition to the SLEEP state. Then, when directed to a deeper low power state (i.e., L1.OFF state 545), all configured channels may transition to the HIBERN8 state. Finally, when directed back to the configuration state, similarly, all configured channels transition to the HIBERN8 state.

Still referring to Figure 5, for active data transfers, control is thus passed to the active state 550. In particular, this is the state where the link and transaction layers begin to exchange information using data link layer packets (DLLPs) and TLPs. In this way, payload transfers can occur, and at the end of such transfers, a TAIL OFBURST symbol can be transmitted.

As seen, control energy passes from this active state back to the STALL state 530 , to the RECOVERY state 560 (eg, in response to a receiver error, or when otherwise directed), or to a deeper low power (eg, L2) state 570 .

To return to the shutdown state, the transmitter may send the EIOS sequence on all configured channels, followed by the TAIL of BURST indication.

If an error occurs or is otherwise directed, control can also pass to the recovery state 560. Here, the transition to recovery causes all configured channels to enter the STALL state in both directions. To achieve this, a GO TO STALL signal can be sent on the sideband interconnect, and the transmitter of this signal can wait for a response. When this stall signal has been sent and received, as indicated by a GO TO STALL indication received on the sideband interconnect, control passes back to the STALL state 530. Note that this recovery state thus uses the sideband establishment protocol to coordinate simultaneous entry into the STALL state.

With respect to the low power states L1 and L1.OFF, operation is according to states 540 and 545. In particular, control is passed from the STALL state to the L1 low power state 540 to enable the PHY to be placed in the SLEEP state. In this state, the negative drive signal, i.e., the DIF-N signal, can be driven on all configured channels. When directed to exit the state, control is passed back to the STALL state, for example, by signaling a PRESENCE signal on the sideband interconnect.

As also seen, a deeper low state L1.OFF can be entered when all L1.OFF conditions are met. In one embodiment, these conditions may include full power gating or turning off power to the PHY unit. In this deeper low power state, the PHY may be placed in a HIRERN8 state and drive high impedance signals on all configured channels. To exit this state, control is passed back to the STALL state via driving DIF-N on all configured channels.

5, there may be an additional state, a further deeper low power state (L2) 570, which can be entered from the active state when power is ready to be turned off. In one embodiment, this state may be the same as that of the PCIe ^™ specification.

Referring now to Table 2, there is shown a mapping between LTSSM states according to the PCIe ^™ specification and corresponding M-PHY states according to an embodiment of the present invention.

Table 2

As described above with reference to FIG. 2 , an embodiment provides a unified sideband mechanism that can be used for link management and optional in-band support. In this manner, using sideband circuits and interconnects, link management and control can occur independently of the higher speed (and more power-hungry) circuits of the physical layer used for the primary interconnect. Further in this manner, this sideband channel can be used when portions of the PHY unit associated with the primary interconnect are powered down, resulting in reduced power consumption. Moreover, this unified sideband mechanism can be used prior to training the primary interconnect, and can also be used when a fault occurs on the primary interconnect.

Still further, via this unified sideband mechanism, there can be a single interconnect in each direction, such as a differential pair, thereby reducing pin count and enabling the addition of new capabilities. Embodiments can also enable faster, more robust clock/power gating, and can use this link to eliminate ambiguity in conventional protocols such as the PCIe ^TM sideband mechanism.

However, the scope of the present invention is not limited in this regard, and in different embodiments, the sideband interconnect (e.g., sideband interconnect 270 of FIG. 2) can be implemented as a single-wire bidirectional sideband signal, a two-wire bidirectional unidirectional signal set, a low-speed in-band signaling mechanism (such as available using an M-PHY in a low-power pulse width modulation (PWM) mode), or as an in-band high-speed signaling mechanism, such as a physical layer ordered set or DLLP.

As an example and not for the purpose of limitation, various physical layer methods can be supported. When using sideband interconnects, the first method can be a single-wire bidirectional sideband signal that provides a minimum number of pins. In some embodiments, this signal can be multiplexed on an existing sideband, such as a PERST#, WAKE#, or CLKREQ signal. The second method can be a two-wire bidirectional unidirectional signal set, which can be simpler and more efficient to some extent than a single-wire method, but at the cost of additional pins. This implementation can be multiplexed on an existing sideband, such as PERST# for a host device and CLKREQ# for a device host (in this example, the existing signal directionality is maintained, simplifying the dual-mode implementation). The third method can be a low-speed in-band signaling mechanism, such as M-PHY LS PWM mode, which reduces the number of pins relative to the sideband mechanism and can still support similar low power levels. Because this operating mode is mutually exclusive with high-speed operation, it can be combined with high-speed in-band mechanisms such as physical layer ordered sets or DLLPs. Although this method is not low-power, it maximizes commonality with existing high-speed IO. When combined with low-speed in-band signaling, this approach can provide a good low-power solution.

To implement one or more of these configurations in a given system, a semantic layer can be provided that can be used to determine the meaning of information exchanged above the physical layer and the policy layer, which can be used to comprehend device/platform level actions/reactions. In one embodiment, these layers can exist in the SB PHY unit.

By providing a layered approach, embodiments allow for different physical layer implementations that may include both sideband capabilities (which may be preferred in certain implementations due to simplicity and/or low power operation) and in-band (which may be preferred for other implementations, e.g., to avoid the need for additional pin count).

In one embodiment, multiple sideband signals can be configured, for example, via a semantic layer, into a single data packet for communication via a unified sideband mechanism (or an in-band mechanism). In one embodiment, Table 3 below shows various signals that may be present in one embodiment. In the table shown, the logical direction of the signal is shown by an arrow, where an upper arrow is defined as the direction to a host (e.g., a root complex), and a lower arrow is defined as the direction to a device (e.g., a peripheral device such as a radio solution).

Table 3

Device exists↑

Power is good↓

Power off↓

Reference clock is good↓

Basic reset↓

Configuration preparation↑↓

Prepare for training ↑↓

Start training↑↓

L1pg request↑↓

L1pg rejected↑↓

L1pg authorization↑↓

OBFF CPU active↓

OBFF DMA↓

OBFF Idle↓

Wake up ↑

Handshake response reception↑↓

Now referring to Fig. 6, a flow chart for each state of the sideband mechanism according to an embodiment of the present invention is shown. As shown in Fig. 6, these various states can be about the root complex (e.g., host control operation). State diagram 600 can provide control of each state via the host. As seen, operation begins in pre-boot state 610, in which a presence signal can be transmitted. It should be noted that this presence signal can be as described above about link management operation. Then, control is passed to boot state 620, in which various signals can be transmitted, i.e., power good signal, reset signal, reference clock state signal, and ready training signal. It should be noted that all these signals can be transmitted via a single data packet, wherein each of these signals can correspond to an indicator or field of the data packet (e.g., a 1-bit indicator of the data packet).

Still referring to FIG. 6 , control next passes to active state 630 , where the system may be in an active state (e.g., S0 ), a corresponding device (e.g., a downstream device may be in an active device state (e.g., D0 ) and a link may be in an active state, shutdown, or low power state (e.g., L0 , L0s, or L1 ). As can be seen, in this state, various signals may be transmitted, including an OBFF signal, a clock request signal, a reference clock state, a request L0 signal, and a ready to train signal.

Next, for example, after performing the above-mentioned signaling, control can be transferred to a low power state 640. As can be seen, in this low power state 640, the system can be in an active state, while the device can be in a relatively low latency low power state (e.g., D3 hot). In addition, the link can be in a given low power state (e.g., L2 or L3). As can be seen in these states, the signals transmitted via the unified sideband packet can include a wake-up signal, a reset signal, and a power good signal.

When the system enters a deeper low power state, a second low power state 650 can be entered (e.g., when the system is in the S0 state and the device is in the D3 cold state and the link is similarly in the L2 or L3 state. As seen, the same wake-up, reset, and power good signals can be transmitted. As also seen in FIG. 6 , the same signals can occur in a deeper low power state 660 (e.g., system low power state S3) and a device low power state (e.g., D3 cold) as well as the same link low power states L2 and L3. While this particular set of sideband information being communicated is shown, understand that the scope of the present invention is not limited in this regard.

Embodiments thus provide a hierarchical structure with extensibility that balances simplicity with low latency against flexibility. In this way, existing sideband signals and additional sideband signals can be replaced with a smaller number of signals, and future expansion of the sideband mechanism can be achieved without adding more pins.

Referring now to FIG. 7 , a flow chart of a method according to an embodiment of the present invention is shown. As shown in FIG. 7 , a method 700 may be used to transmit data via an aggregated protocol stack, the aggregated protocol stack comprising an upper layer of a communication protocol and a lower layer of a different communication protocol, such as a physical layer. In the example shown, an aggregated protocol stack as described above is assumed, i.e., an upper transaction and data link layer having a PCIe ^TM protocol and a physical layer of a different specification (e.g., a MIPI specification). Of course, there may also be additional logic that enables the two communication protocols to be aggregated into a single protocol stack, such as the logic and circuits discussed above with respect to FIG. 4 .

As seen in FIG. 7 , method 700 can begin by receiving a first transaction in a protocol stack of a first communication protocol (block 710). For example, various logic such as a root complex of a kernel, other execution engines, etc. seek to send information to another device. Therefore, such information can be passed to the transaction layer. As seen, control is passed to block 720, where the transaction can be processed and provided to the logic portion of the PHY of the second communication protocol. Such processing can include various operations discussed above with respect to the flow of FIG. 4 , wherein various operations such as receiving data, performing flow control, link operations, and packet operations can occur. In addition, various operations of providing data link layer data packets to the PHY can occur. Next, control is passed to block 730, wherein this first transaction can be converted into a second format transaction in the logic portion of the PHY. For example, any conversion of symbols (when necessary) can be performed. In addition, various conversion operations performed to thereby convert the transaction into a format for transmission on the link can occur. Therefore, control can be passed to block 740, wherein this second format transaction can be transmitted from the PHY to the device via the link. As an example, the second format transaction could be serialized data after line encoding, serialization, etc. While shown at this high level in the embodiment of FIG. 7 , understand the scope of the present invention is not limited in this regard.

Now referring to Fig. 8, a block diagram of a component present in a computer system according to an embodiment of the present invention is shown. As shown in Fig. 8, system 800 can include many different components. These components can be implemented as IC, its parts, discrete electronic devices or other modules adapted to circuit boards such as the motherboard or plug-in cards of the computer system, or implemented as components otherwise merged in the chassis of the computer system. It should also be noted that the block diagram of Fig. 8 is intended to illustrate the high-level view of many components of the computer system. However, it is to be understood that in some embodiments, additional components may exist, and in addition, different arrangements of the components shown may occur in other embodiments.

As seen in FIG8 , processor 810 (which may be a low-power multi-core processor socket such as an ultra-low voltage processor) may serve as the main processing unit and central hub for communicating with the various components of the system. Such a processor can be implemented as a SoC. In one embodiment, processor 810 may be based on A processor based on an Intel Core ^™ architecture (such as an i3, i5, i7, or another such processor available from Intel Corporation of Santa Clara, Calif.) may be used in conjunction with an A5 processor. However, it is to be understood that other low-power processors such as those available from Advanced Micro Devices (AMD) of Sunnyvale, Calif., an ARM-based design from ARM Holdings plc, or a MIPS-based design from MIPS Technologies, Inc. of Sunnyvale, Calif., or a licensee or adopter thereof, may instead be present in other embodiments such as the Apple A5 processor.

The processor 810 can communicate with a system memory 815, which can be implemented in an embodiment through multiple memory devices to provide a certain amount of system memory. As an example, the memory can be based on a low power double data rate (LPDDR) design based on the Joint Electron Device Engineering Conference (JEDEC), such as the current LPDDR2 standard (published in April 2009) according to JEDEC JESD 209-2E, or the next generation LPDDR standard called LPDDR3, which will provide an extension to LPDDR2 to increase bandwidth. As an example, there can be 2/4/8 gigabytes (GB) of system memory and can be coupled to the processor 810 via one or more memory interconnects. In various embodiments, individual memory devices can have different package types, such as a single die package (SDP), a dual die package (DDP), or a quad die package (QDP). These devices can be directly soldered to the motherboard in some embodiments to provide a low profile solution, while in other embodiments, the devices can be configured as one or more memory modules, which can then be coupled to the motherboard by a given connector.

In order to provide continuous storage of information (such as data, applications, one or more operating systems, etc.), mass storage 820 can also be coupled to processor 810. In various embodiments, in order to realize thinner and lighter system design, and in order to improve system responsiveness, this mass storage can be implemented via SSD. However, in other embodiments, mass storage can be mainly implemented using hard disk drive (HDD), wherein a small amount of SSD memory acts as SSD cache to realize non-volatile storage of background state and other such information during shutdown events, so that fast power-on can occur when restarting system activities. Also shown in Figure 8, flash memory device 822 can be coupled to processor 810, for example, via serial peripheral interface (SPI). This flash memory device can provide non-volatile storage of system software including basic input/output software (BIOS) and other firmware of the system.

Various input/output (IO) devices may be present within the system 800. A display 824 is particularly shown in the embodiment of FIG. 8 , which may be a high-resolution LCD or LED panel configured within the cover of the chassis. This display panel may also provide a touch screen 825, for example externally adapted to the display panel so that user input can be provided to the system to achieve desired operations, such as information display, information access, etc., via user interaction with this touch screen. In one embodiment, the display 824 may be coupled to the processor 810 via a display interconnect that may be implemented as a high-performance graphics interconnect. The touch screen 825 may be coupled to the processor 810 via another interconnect, which in one embodiment may be an I ² C interconnect. As further shown in FIG. 8 , in addition to the touch screen 825, user input by touch may also occur via a touch pad 830, which may be configured within the chassis and may also be coupled to the same I ² C interconnect as the touch screen 825.

For perceptual computing and other purposes, various sensors may be present within the system and may be coupled to the processor 810 in different ways. Certain inertial and environmental sensors may be coupled to the processor 810 via a sensor hub 840 (e.g., via an I ² C interconnect). In the embodiment shown in FIG8 , these sensors may include an accelerometer 841, an ambient light sensor (ALS) 842, a compass 843, and a gyroscope 844. In one embodiment, other environmental sensors may include one or more thermal sensors 846, which may be coupled to the processor 810 via a system management bus (SMBus) bus. It is also understood that according to embodiments of the present invention, one or more of the sensors may be coupled to the processor 810 via an LPS link.

As also seen in FIG. 8 , various peripherals can also be coupled to the processor 810 via a low pin count (LPC) interconnect. In the illustrated embodiment, various components can be coupled via an embedded controller 835. These components can include a keyboard 836 (e.g., coupled via a PS2 interface), a fan 837, and a thermal sensor 839. In some embodiments, a touchpad 830 can also be coupled to the EC 835 via a PS2 interface. In addition, a security processor (such as a Trusted Platform Module (TPM) 838 according to the Trusted Computing Group (TCG) TPM Specification Version 1.2 (October 2, 2003)) can also be coupled to the processor 810 via this LPC interconnect.

The system 800 can communicate with peripheral devices in various ways including wireless ways. In the embodiment shown in Figure 8, there are various wireless modules, each of which can correspond to a radio configured for a specific wireless communication protocol. A method for wireless communication within a short range (such as a near field) can be via a near field communication (NFC) unit 845, which in one embodiment can communicate with the processor 810 via SMBus. It should be noted that via this NFC unit 845, devices in close proximity to each other can communicate. For example, by adapting two closely related devices together and enabling information (such as identification information, payment information, data such as image data, etc.) to be transmitted, a user can enable the system 800 to communicate with another (for example) portable device (such as a user's smart phone). Wireless power transmission can also be performed using the NFC system.

As further seen in FIG. 8 , additional wireless units can include other short-range wireless engines, including a WLAN unit 850 and a Bluetooth unit 852. Using the WLAN unit 850, Wi-Fi ^™ communications according to a given Institute of Electrical and Electronics Engineering (IEEE) 802.11 standard can be implemented, while via the Bluetooth unit 852, short-range communications via the Bluetooth protocol can occur. These units can communicate with the processor 810 via, for example, a USB link or a universal asynchronous receiver transmitter (UART) link. Or these units can be coupled to the processor 810 via an interconnect via a low-power interconnect such as the aggregated PCIe/MIPI interconnect described herein or another such protocol such as the serial data input/output (SDIO) standard. Of course, the actual physical connection between these peripheral devices, which can be configured on one or more plug-in cards, can be by way of an NGFF connector adapted to a motherboard.

In addition, wireless wide area communications (e.g., according to a cellular or other wireless wide area protocol) can occur via a WWAN unit 856, which can in turn be coupled to a subscriber identity module (SIM) 857. In addition, a GPS module 855 may also be present to enable reception and use of location information. Note that in the embodiment shown in FIG. 8 , the WWAN unit 856 and an integrated capture device such as a camera module 854 can communicate via a given USB protocol (such as a USB 2.0 or 3.0 link), or a UART or I ² C protocol. The actual physical connection of these units can again be via an NGFF plug-in card adapted to a NGFF connector configured on the motherboard.

To provide audio input and output, the audio processor can be implemented via a digital signal processor (DSP) 860, which can be coupled to the processor 810 via a high-resolution audio (HAD) link. Similarly, the DSP 860 can communicate with an integrated coder/decoder (CODEC) and amplifier 862, which in turn can be coupled to an output speaker 863 that can be implemented within the chassis. Similarly, the amplifier and CODEC 862 can be coupled to receive audio input from a microphone 865, which in an embodiment can be implemented via a dual array microphone to provide high-quality audio input to enable voice-activated control of various operations within the system. It is also noted that audio output can be provided from the amplifier/COEDC 862 to a headphone jack 864.

Therefore, the embodiment can be used in many different environments. Now referring to Figure 9, an example system 900 that can be used with the embodiment is shown. As seen, the system 900 can be a smart phone or other wireless communicator. As shown in the block diagram of Figure 9, the system 900 may include a baseband processor 910, which can be a multi-core processor capable of processing baseband processing tasks and application processing. Therefore, the baseband processor 910 can perform various signal processing about communication, and perform computing operations for the device. Then, the baseband processor 910 can be coupled to a user interface/display 920, which can be implemented by a touch screen display in some embodiments. In addition, the baseband processor 910 can be coupled to a memory system, which includes a non-volatile memory (i.e., flash memory 930) and a system memory (i.e., dynamic random access memory (DRAM) 935) in the embodiment of Figure 9. As further seen, the baseband processor 910 can be further coupled to a capture device 940, such as an image capture device capable of recording video and/or still images.

In order to realize the transmission and reception of communication, various circuits can be coupled between the baseband processor 910 and the antenna 980. In particular, there can be a radio frequency (RF) transceiver 970 and a wireless local area network (WLAN) transceiver 975. In general, the RF transceiver 970 can be used to receive and transmit wireless data and make calls according to a given wireless communication protocol such as a 3G or 4G wireless communication protocol according to code division multiple access (CDMA), global mobile communication system (GSM), long term evolution (LTE) or other protocols. Other wireless communications such as receiving or transmitting radio signals, such as AM/FM, or global positioning satellite (GPS) signals can also be provided. In addition, via the WLAN transceiver 975, local wireless signals can also be realized, such as according to the Bluetooth ^TM standard or the IEEE802.11 standard (such as IEEE802.11a/b/g/n). It should be noted that the link between the baseband processor 910 and one or both of the transceivers 970 and 975 can be via a low power aggregation interconnect that combines and maps the functionality of a PCIe ^TM interconnect and a low power interconnect (such as a MIPI interconnect). Although shown at this high level in the embodiment of FIG. 9 , it is to be understood that the scope of the present invention is not limited in this regard.

Embodiments may be used in many different types of systems. For example, in one embodiment, a communication device can be arranged to perform the various methods and techniques described herein. Of course, the scope of the present invention is not limited to communication devices, and on the contrary, other embodiments can involve other types of apparatuses for processing instructions, or one or more machine-readable media, including instructions that, in response to being executed on a computing device, cause the device to perform one or more methods and techniques described herein.

Embodiments may be implemented in code and may be stored on a non-transitory storage medium having stored thereon instructions that can be used to program a system to perform the instructions. The storage medium may include, but is not limited to: any type of magnetic disk, including floppy disks, optical disks, solid state drives (SSDs), compact disk read only memory (CD-ROMs), compact disk rewritable (CD-RWs), and magneto-optical disks; semiconductor devices such as read-only memory (ROMs), random access memories (RAMs) (such as dynamic random access memories (DRAMs), static random access memories (SRAMs)), erasable programmable read-only memories (EPROMs), flash memory, electrically erasable programmable read-only memories (EEPROMs); magnetic or optical cards, or any other type of medium suitable for storing electronic instructions.

While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations that fall within the true spirit and scope of the present invention.

Claims (19)

1. An apparatus, comprising:

fast interconnect for peripheral components^TM(PCIe^TM) A protocol stack of a communication protocol, the protocol stack comprising a transaction layer and a link layer; and

a Physical (PHY) unit coupled to the protocol stack to provide communication between the apparatus and devices coupled to the apparatus via a physical link, the PHY unit having a low power communication protocol and including a physical unit circuit according to the low power communication protocol and logic to interface the protocol stack with the physical unit circuitAn edit layer, the logical layer including a link training state machine to perform link training for the physical link and including to have the PCIe^TMMapping logic to map a first special symbol of a communication protocol to a second special symbol having the low power communication protocol.

2. The apparatus of claim 1, wherein the physical link has a width from the apparatus to the device that is asymmetric to that from the device to the apparatus, and the physical link is configurable to operate from the apparatus to the device at a frequency that is asymmetric to that from the device to the apparatus.

3. The apparatus of claim 1, wherein the link training state machine initializes a physical link from a reset of the apparatus to an initial link width and frequency in advance without negotiating with the device.

4. The apparatus of claim 3, wherein the link training state machine causes a change in link width of the physical link without negotiating with the device.

5. The apparatus of claim 1, further comprising a sideband channel coupled between the apparatus and the device separate from the physical link, the sideband channel comprising a serial link having a second PHY unit separate from the PHY unit, and wherein the second PHY unit transmits a first presence signal to the device and receives a second presence signal from the device, the link training state machine configuring the physical link in response to receiving the second presence signal in the second PHY unit.

6. A method, comprising:

performing, in a first integrated circuit coupled to a second integrated circuit via a physical link, power-on with low power in response to power-up of the first integrated circuitA detection state of a link training state machine of a Physical (PHY) unit of a communication protocol including physical unit circuitry, the PHY unit coupled to a fast interconnect for peripheral components including a transaction layer and a link layer^TM(PCIe^TM) A protocol stack of a communication protocol;

after performing the detection state, performing, in the first integrated circuit, a configuration state of the link training state machine, including sending a configuration ready signal to the second integrated circuit via a sideband link coupled between the first and second integrated circuits; and

in the first integrated circuit, in response to receiving a second configuration ready signal from the second integrated circuit via the sideband link, performing a shutdown state of a link training state machine, wherein during the shutdown state the PHY unit drives a differential N signal on the physical link.

7. The method of claim 6, further comprising: initiating a burst sequence in the down state to transition into an active state of the link training state machine.

8. The method of claim 7, further comprising: in the active state, a payload is transferred from the first integrated circuit to the second integrated circuit, and then a tail of a burst signal is transferred to transition to the shutdown state.

9. The method of claim 6, further comprising: transition from the shutdown state into a first low power state and drive the differential N signal on the physical link in the first low power state.

10. The method of claim 9, further comprising: transition from the first low-power state to the shutdown state in response to receiving a presence signal from the second integrated circuit via the sideband link.

11. The method of claim 9, further comprising: transitioning from the shutdown state to a second low power state when a set of predetermined conditions are met, the second low power state being lower than the first low power state, and driving a differential high impedance signal on the physical link in the second low power state.

12. The method of claim 7, further comprising: transitioning from the active state to a recovery state in response to a receiver error.

13. The method of claim 6, further comprising:

sending a shutdown initiation signal to the second integrated circuit via the sideband channel; and

transition to the shutdown state in response to receiving a shutdown indication signal from the second integrated circuit via the sideband link.

14. The method of claim 7, further comprising: transitioning from the active state to a powered-down state in response to a communication received in a PHY unit from the protocol stack.

15. A system, comprising:

a multi-core processor comprising a plurality of cores and a protocol stack that enables communication between the multi-core processor and a peripheral device via a physical link, the protocol stack comprising:

fast interconnect based on peripheral components^TM(PCIe^TM) A transaction layer of a communication protocol;

according to the PCIe^TMA data link layer of a communication protocol; and

physical layer including a physical layer transport controller and Physical (PHY) unit transport circuitry according to a low power communication protocol, wherein the physical layer transport controller adapts the PHY unit transport circuitry to have PCIe^TMA transaction layer and a data link layer of a communication protocol, the physical layer further including a link training state machine that performs link training for the physical link and including the PCIe to be in^TMMapping logic to map a first special symbol of a communication protocol to a second special symbol having the low power communication protocol; and

a peripheral coupled to the multicore processor.

16. The system of claim 15, wherein the link training state machine: in response to a power-up of the multi-core processor, performing a configuration state of the link training state machine after performing a detection state, including sending a configuration ready signal to the peripheral device via a sideband link coupled between the multi-core processor and the peripheral device; and performing a shutdown state of the link training state machine in response to receiving a second configuration ready signal from the peripheral device via the sideband link, wherein during the shutdown state, the PHY unit transmission circuitry drives a differential N signal on the physical link.

17. The system of claim 16, wherein the link training state machine initiates a burst sequence in the shutdown state to transition into an active state of the link training state machine and transmits a payload from the multicore processor to the peripheral device in the active state, and then transmits a tail of a burst signal to transition into the shutdown state.

18. The system of claim 17, wherein the link training state machine sends a shutdown initiation signal to the peripheral device via the sideband link and transitions to the shutdown state in response to receiving a shutdown indication signal from the peripheral device via the sideband link.

19. The system of claim 15, wherein the peripheral device comprises a multi-radio integrated circuit.