CN104360112B - Semiconductor test tool and forming method thereof - Google Patents
Semiconductor test tool and forming method thereof Download PDFInfo
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- CN104360112B CN104360112B CN201410607155.1A CN201410607155A CN104360112B CN 104360112 B CN104360112 B CN 104360112B CN 201410607155 A CN201410607155 A CN 201410607155A CN 104360112 B CN104360112 B CN 104360112B
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- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
A kind of semiconductor test tool and forming method thereof, wherein semiconductor test tool, including：Substrate；An at least row in substrate tests syringe needle, and the adjacent test syringe needle mutual dislocation arrangement in each row, each syringe needle of testing includes：First testing needle, first testing needle include the first noumenon, the first test lead positioned at the first noumenon one end and the first connection end positioned at the first noumenon other end；Cover the insulating barrier on the first noumenon surface of first testing needle；The second testing needle positioned at surface of insulating layer around first testing needle, second testing needle and the first test coaxial needle, second testing needle includes the second body, the second test lead positioned at second body one end and the second connection end positioned at the second body other end, and the second test end surfaces flush with the first test end surfaces.Syringe needle dislocation arrangement is tested, the distance between adjacent test syringe needle is reduced, realizes the electrical performance testing to the tested terminal of small spacing.
Description
Technical field
The present invention relates to semiconductor test technical field, more particularly to a kind of semiconductor test tool and forming method thereof.
Background technology
Test processing procedure is the electrical functionality for the product that test encapsulation is completed after IC package, to ensure IC functions of dispatching from the factory
On integrality, and the product to having tested is made to classify according to its electrical functionality, as the Appreciation gist of IC different brackets products, most
Make appearance test operation afterwards and to product.
Electrical functionality test is that the various electrical parameters for being directed to product are tested to determine product energy normal operation.
The test of two-point contact such as Kelvin's test etc., uses Double ejection pin or double golden hands more on traditional same tested terminal
Refer to the mode of parallel side-by-side distribution, it is primarily present following deficiency：
1st, the accuracy of manufacture is relatively low：With the continuous diminution of semiconductor product size, the size of terminal and different quilts are tested
The spacing surveyed between terminal is also constantly reducing, in order to comply with this trend, the Double ejection pin or double golden hands of Conventional parallel and column distribution
Refer to test mode bottleneck on the problem of its close spacing to become increasingly conspicuous, required precision more and more higher, some can not even have been realized
.
2nd, structural strength is weaker：In order to realize that two-point contact is tested in limited space on tested terminal, thimble or gold
Finger is corresponding increasingly thinner, and its Mechanical Structure Strength is also more and more weaker.
3rd, service life is shorter：The test contact head of traditional thimble or golden finger is easier to frayed, is especially carried in precision
Go out requirements at the higher level, mechanical strength it is relatively low when, the degree of wear is bigger, and then reduces the service life of measurement jig.
4th, measuring accuracy is relatively low：To comply with the compact growth requirement of semiconductor, increasingly thinner thimble or golden finger
Caused resistance value constantly increases, while when carrying out high-current test, can produce larger pressure drop and influence test number
Judgement；On the other hand, the Double ejection pin of parallel side-by-side distribution or double golden fingers also easily produce because of offset deviation between the two
The deviation of raw test number；In addition, tradition and the Double ejection pin of column distribution in order to reduce the distance between two pins and use two back to
The way of contact on inclined-plane, contact head easily rotate out of tested terminal and then influence because of the torsion of telescopic spring in its overall structure
Measuring accuracy.
The content of the invention
The present invention solves the problems, such as it is how to improve the precision and stability of existing electrical performance testing.
To solve the above problems, the present invention provides a kind of test syringe needle, including：Substrate；An at least row in substrate
Syringe needle is tested, the adjacent test syringe needle mutual dislocation arrangement in each row, each syringe needle of testing includes：First testing needle, it is described
First testing needle includes the first noumenon, the first test lead positioned at the first noumenon one end and the positioned at the first noumenon other end
One connection end；Cover the insulating barrier on the first noumenon surface of first testing needle；Positioned at surface of insulating layer around described first
Second testing needle of testing needle, the second testing needle and the first test coaxial needle, the second testing needle include the second body, positioned at second
Second test lead of body one end and the second connection end positioned at the second body other end, the second test end surfaces and the
One test end surfaces flush.
Optionally, to be centrally located at first straight for some odd numbers test syringe needle that the dislocation arrangement refers in each row
On line, some even number test syringe needles are centrally located in second straight line, and first straight line is parallel to each other with second straight line.
Optionally, formed with signal circuit in the substrate, the signal circuit includes first input end, the
One output end, the second input and the second output end, first output end electrically connect with the first connection end of the first testing needle,
Second output end electrically connects with the second connection end of the second testing needle, the first input end and the second input respectively with
Outside test circuit electrical connection.
Present invention also offers a kind of forming method of semiconductor test tool, including：Substrate is provided；On the substrate
Form an at least row and test syringe needle, the adjacent test syringe needle mutual dislocation arrangement on the same row, the test syringe needle includes：
First testing needle, first testing needle include the first noumenon, the first test lead positioned at the first noumenon one end and positioned at the
First connection end of the one body other end；Cover the insulating barrier on the first noumenon surface of first testing needle；Positioned at insulating barrier
Around the second testing needle of first testing needle, the second testing needle and the first test coaxial needle, the second testing needle include surface loop
Second body, the second test lead positioned at second body one end and the second connection end positioned at the second body other end, it is described
Second test end surfaces flush with the first test end surfaces.
Optionally, the forming process of the test syringe needle is：At least one is formed on the substrate and ranked first testing needle, often
Adjacent first testing needle mutual dislocation arrangement in one row；Insulation is formed in the side wall of each first testing needle in each row
Layer；The second testing needle is formed on the surface of insulating barrier, second testing needle is around corresponding first testing needle.
Optionally, the first testing needle dislocation arrangement refers to the centre bit of some testing needles of odd number first in each row
In in first straight line, some testing needles of even number first are centrally located in second straight line, first straight line and second straight line phase
It is mutually parallel.
Optionally, the forming process of first testing needle, insulating barrier and the second testing needle is：Formed on the substrate
The first metal layer；Etch the first metal layer and form at least one and ranked first testing needle, adjacent first testing needle in each row
Between mutual dislocation arrange；Form the insulating thin layer for covering each first testing needle side wall and top surface；Without mask etching
Technique etches the insulating thin layer and forms insulating barrier in the side wall of the first testing needle；Formed and cover the insulating barrier and the first survey
The second metal layer of test point top surface；Without second metal layer described in mask etching, the second testing needle is formed in surface of insulating layer.
Optionally, the forming process of first testing needle, insulating barrier and the second testing needle is：Formed on the substrate
Sacrifice layer, has at least exhausting hole for exposing substrate surface in the sacrifice layer, phase between the adjacent through-holes in each row
Mutually dislocation arrangement；Full metal is filled in the through hole, forms some first testing needles；Remove the sacrifice layer；Form covering
The insulating thin layer of each first testing needle side wall and top surface；The insulating thin layer is etched the without mask etching technique
The side wall of one testing needle forms insulating barrier；Form the second metal layer for covering the insulating barrier and the first testing needle top surface；
Without second metal layer described in mask etching, the second testing needle is formed in surface of insulating layer.
Optionally, the forming process of the first detection pin, the second detection pin and insulating barrier is：Formed on the substrate
Dielectric layer, through hole and the annular through-hole around each first through hole are ranked first formed with least one in the dielectric layer, first is logical
Isolated between hole and annular through-hole by certain media layer, mutual dislocation is arranged between the adjacent first through hole in each row；
Metal is filled in first through hole and forms the first testing needle, metal is filled in annular through-hole and forms the second testing needle；Remove second
Dielectric layer on the outside of testing needle, remaining dielectric layer is as insulating barrier between the first testing needle and the second testing needle.
Optionally, formed with signal circuit in the substrate, the signal circuit includes first input end, the
One output end, the second input and the second output end, first output end electrically connect with the first connection end of the first testing needle,
Second output end electrically connects with the second connection end of the second testing needle, the first input end and the second input respectively with
Outside test circuit electrical connection.
Compared with prior art, technical scheme has advantages below：
First testing needle and the second testing needle are integrated in one by the test syringe needle in the semiconductor test tool of the present invention
Test on syringe needle, the second testing needle around first testing needle, between the second testing needle and the first testing needle with insulating barrier every
From, so that it is less simultaneously in the size for ensureing testing needle, lift the mechanical strength of testing needle；On the other hand, the first testing needle
It is coaxially to be distributed with the second testing needle so that the precision of spacing is higher between the first testing needle and the second testing needle, improves survey
The precision of examination；Another further aspect, need multiple testing needles (such as Double ejection pin or golden finger) that electricity could be carried out compared to prior art
Performance test is learned, of the invention test syringe needle can carry out the test of electric property；Another further aspect is adjacent in each row
Test syringe needle dislocation arrangement so that the distance between adjacent test syringe needle on each row can reduce, so as to realize pair
In the electrical performance testing of multiple tested terminals of small spacing.
Further, it is easy to the transmission of test signal in test process formed with signal circuit in the substrate and obtains
, and improve semiconductor test tool integrated level.
The forming method of the semiconductor test tool of the present invention, passes through the advanced semiconductor integration making technology system of technique
Make so that the size of some test syringe needles formed in substrate is identical with surface topography, and it is adjacent test syringe needle between
Away from identical, when the semiconductor test tool that the inventive method is formed is used for into electrical performance testing, the precision of test is improved.
Brief description of the drawings
Fig. 1~Fig. 4 is the structural representation of semiconductor test tool of the embodiment of the present invention；
Fig. 5~Fig. 9 is the structural representation of one embodiment of the invention semiconductor test tool forming process；
Figure 10~Figure 13 is the structural representation of another embodiment of the present invention semiconductor test tool forming process.
Embodiment
As background technology is sayed, the performance of existing thimble or golden finger still has much room for improvement.
Therefore, the invention provides a kind of semiconductor test tool, including substrate；At least row test in substrate
Syringe needle, the adjacent test syringe needle mutual dislocation arrangement in each row, each syringe needle of testing include：First testing needle, described first
Testing needle includes the first noumenon, the first test lead positioned at the first noumenon one end and the positioned at the first noumenon other end first company
Connect end；Cover the insulating barrier on the first noumenon surface of first testing needle；Positioned at surface of insulating layer around the described first test
Second testing needle of pin, the second testing needle and the first test coaxial needle, the second testing needle include the second body, positioned at the second body
Second test lead of one end and the second connection end positioned at the second body other end, the second test end surfaces and first are surveyed
Examination end surfaces flush.First testing needle and the second testing needle are integrated in by the test syringe needle in the semiconductor test tool of the present invention
On one test syringe needle, the second testing needle is around first testing needle, with insulation between the second testing needle and the first testing needle
Layer isolation, thus it is less simultaneously in the size for ensureing testing needle, lift the mechanical strength of testing needle；On the other hand, first survey
Test point and the second testing needle are coaxially to be distributed so that the precision of spacing is higher between the first testing needle and the second testing needle, improves
The precision of test；Another further aspect, multiple testing needles (such as Double ejection pin or golden finger) are needed just to enter compared to prior art
Row electrical performance testing, of the invention test syringe needle can carry out the test of electric property；Another further aspect, in each row
Adjacent test syringe needle dislocation arrangement so that the distance between adjacent test syringe needle on each row can reduce, so as to reality
Referring now to the electrical performance testing of the tested terminal of small spacing.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.When the embodiment of the present invention is described in detail, for purposes of illustration only, schematic diagram can disobey general proportion
Make partial enlargement, and the schematic diagram is example, and it should not be limited the scope of the invention herein.In addition, in reality
The three-dimensional space of length, width and depth should be included in making.
Fig. 1~Fig. 4 is the structural representation of semiconductor test tool of the embodiment of the present invention；Fig. 5~Fig. 9 is real for the present invention one
Apply a structural representation for semiconductor test tool forming process；Figure 10~Figure 13 is another embodiment of the present invention semiconductor test
The structural representation of tool forming process.
It refer to Fig. 1 and Fig. 2, Fig. 2 is Fig. 1 along line of cut cross-sectional view, is provided in one embodiment of the invention
Semiconductor test tool, including：
Substrate 200；
An at least row in substrate 200 tests syringe needle 20, the adjacent mutual dislocation of test syringe needle 20 row in each row
Cloth, each syringe needle 20 of testing include：First testing needle 201；Cover the insulating barrier 202 of the sidewall surfaces of the first testing needle 201；
The second testing needle 203 positioned at the surface loop of insulating barrier 202 around first testing needle 201, the second testing needle 203 and the first test
Pin 201 is coaxial, and the top surface of the second testing needle 203 flushes with the top surface of the first test lead 31.
Fig. 3 is refer to, Fig. 3 is the mplifying structure schematic diagram of a test syringe needle in Fig. 2, and the test syringe needle 20 includes：
First testing needle 201, first testing needle 201 include the first noumenon, positioned at the first noumenon one end the first test lead 21 with
And positioned at the first connection end 22 of the first noumenon other end；Cover the insulation on the first noumenon surface of first testing needle 201
Layer 202；The second testing needle 203 positioned at the surface loop of insulating barrier 202 around first testing needle 201, the second testing needle 203 and
One testing needle 201 is coaxial, the second testing needle 203 include the second body, the second test lead 23 positioned at second body one end and
Positioned at the second connection end 24 of the second body other end, the surface of the second test lead 23 flushes with the surface of the first test lead 31.
The test lead 23 of first test lead 21 and second when being tested with tested termination contact.
Please continue to refer to Fig. 1, there is the substrate 200 an at least row to test syringe needle, the test syringe needle 20 in each row
For quantity more than or equal to 2, the row of the test syringe needle in the substrate 200 is more than or equal to 1 row, for example can be 1 row, 2 rows, 3
Row, 4 rows etc., in the present embodiment, there are two rows to test syringe needle using in substrate 200 and be used as example.
The adjacent test syringe needle 20 dislocation arrangement that each row in the substrate 200 is tested in syringe needle, the dislocation arrangement
Refer to that the test syringe needle 20 of some odd numbers in each row is centrally located in first straight line, such as the first straight line in Fig. 2
AB, some even number test syringe needles 20 are centrally located in second straight line, such as the second straight line CD in Fig. 2, first straight line
AB is parallel to each other with second straight line CD.In this implementation, the center of the test syringe needle refers to the center of the first testing needle 201.
Vertical range between the first straight line AB and second straight line CD is 0.5 micron~5 millimeters.
Arranged by the way that the adjacent test syringe needle in each row is misplaced so that between the adjacent test syringe needle on each row
Distance can reduce, so as to realize the electrical performance testing of the tested terminal for small spacing.
First testing needle 201 is shaped as cylinder, and the section shape of corresponding first testing needle 201 is circle,
The section shape of the insulating barrier 202 is annular, and the section shape of second testing needle 203 is annular.Need to illustrate
, the section shape of first testing needle can be other shapes, for example the section shape of first testing needle can
Think regular polygon, such as equilateral triangle, square.
The test syringe needle of the present invention is formed by semiconductor integration making technology, thus the first testing needle 201 formed
Diameter can be smaller, and in one embodiment, a diameter of 100 nanometers~500 microns of first testing needle 201, can be 200
Nanometer~50 microns.
The width of the corresponding insulating barrier 202 and the width of the second testing needle 203 can also very little, in an embodiment
In, the width of the insulating barrier 202 is 80 nanometers~400 microns, can be 100 nanometers~10 microns, second testing needle
203 width is 60 nanometers~300 microns, can be 90 nanometers~25 microns.
It should be noted that in other embodiments of the invention, diameter, the insulating barrier 202 of first testing needle 201
Thickness and the thickness of the 3rd testing needle 203 can be other numerical value.
The material of the testing needle 203 of first testing needle 201 and second be copper, gold, tungsten or alloy material or other
Suitable metal material or metal compound material.
The electric isolation that the insulating barrier 202 is used between the first testing needle 201 and the second testing needle 203, the present embodiment
In, the top surface (the first test lead 21) of the top surface of the insulating barrier 202 and the first testing needle 201 and the second testing needle
203 top surface (the second test lead 23) flushes, that is, causes the first test lead 21 and the second testing needle of the first testing needle 201
There is no space between 203 the second test lead 23, in test, prevent the first test lead 21 or the of the first testing needle 201
Second test lead 23 of two testing needles 203 thus between gap be present and deformed under the stress of outside, and cause the
First test lead 21 of one testing needle 201 and the second test lead 23 of the second testing needle 203 make electrical contact with, so as to influence the essence of test
Degree.
The insulating barrier 202 can be single or multiple lift (>=2 layers) stacked structure.
The material of the insulating barrier 202 can be insulating dielectric materials, such as silica, silicon nitride, silicon oxynitride, nitrogen carbon
One or more in SiClx, fire sand, the material of the insulating barrier can also be resin material, such as, epoxy resin, gather
Imide resin, polyvinyl resin, benzocyclobutane olefine resin or polybenzoxazoles resin.
In one embodiment, from the direction that the second test lead 23 is pointed to away from the second test lead 23, second testing needle
The width of 203 part body is gradually reduced.It is specific to refer to Fig. 1, the width of the part body of second testing needle 203,
It is smaller closer to second test lead 23 its width, when that will be used to test with testing needle 20 more so that adjacent test syringe needle 20
The distance between test lead increases.
First testing needle 201 and the second testing needle 203 are integrated in a test by the test syringe needle 20 of the embodiment of the present invention
On syringe needle, the second testing needle 203 is used around first testing needle 201 between second testing needle 203 and the first testing needle 201
Insulating barrier 202 is isolated, thus it is less simultaneously in the size for ensureing testing needle, lift the mechanical strength of testing needle；On the other hand,
First testing needle 201 and the second testing needle 203 are coaxially to be distributed so that between the first testing needle 201 and the second testing needle 203
Away from precision it is higher, and the spacing in test process between the first testing needle 201 and the second testing needle 203 will not change
Become, improve the precision of test；Another further aspect, need multiple testing needles (such as Double ejection pin or golden finger) compared to prior art
Electrical performance testing could be carried out, the embodiment of the present invention is integrated in a survey due to the first testing needle 201 and the second testing needle 203
On test point head, using because one test syringe needle of the embodiment of the present invention can carry out the test of electric property.
When the test syringe needle 20 of the application present invention is carried out into electrical performance testing, in one embodiment, this can be sent out
Bright test syringe needle is applied to resistance test or high-current test, and the one end for testing syringe needle 20 and tested termination contact make
First test lead 21 of the first testing needle 201 and the surface of the second test lead 23 of the second testing needle 203 and the table of tested terminal
Face contacts, and applies test voltage between the first testing needle 201 and the second testing needle 202, and measurement passes through the first testing needle
201st, the electric current on the second testing needle 203 and tested terminal, and pass through test voltage divided by electric current obtains test electricity
Resistance.
When carrying out the test of resistance using the test syringe needle 20 of the present invention, due to the first testing needle 201 and the second testing needle
203 be coaxial, thus tests electric current and uniformly spread by the first testing needle 201 to surrounding, flows to the second testing needle 203,
I.e. so that the tested terminal between the first testing needle 201 and the second testing needle 203 is tested the annular region of terminal (with insulation
The parts of the contact of layer 202) on the electric current that flows through of different directions be average, improve the precision of test.
In other embodiments of the invention, the test syringe needle of the present invention can be applied to the electric property of other forms
Test, such as the test that multiple test syringe needles can be applied to carry out electric property, for example test electric current can be from a testing needle
The first testing needle or the second testing needle of head flow to the first testing needle or the second testing needle of another test syringe needle, or test
Circuit can flow to the first testing needle of another test syringe needle from second testing needle for testing syringe needle and the second testing needle
With the second testing needle.
Please continue to refer to Fig. 2, formed with signal circuit in the substrate 200, the signal circuit includes the
One input, the first output end, the second input and the second output end, the of first output end and the first testing needle 201
One connection end electrically connects, and second output end electrically connects with the second connection end of the second testing needle 203, the first input end
Electrically connected with test circuit of second input respectively with outside.The test circuit is used to provide test signal, the signal
Transmission circuit is used to transmit test signal caused by test circuit to the first testing needle 201 and the second testing needle 203, and will survey
The electric signal transmission obtained during examination to test circuit, test circuit is handled the electric signal of reception, obtains test ginseng
Number.
Material PCB resins of the substrate 200 etc., the first input end and the first output end pass through positioned at intrabasement
First metal wire electrically connects, and second input and the second output end positioned at intrabasement second metal wire by electrically connecting.
In one embodiment, the substrate 200 includes front and the back side relative with front, and the back side of the substrate includes
Interface area, some first output ends and the second output end are located at the front of substrate 200, with the first testing needle and the second testing needle
Position correspondence, some first input ends and the second input can concentrate on the interface area at the back side of substrate 200 so that some
First input end and the second input can be connected by one or more interfaces with the test circuit of outside, simplify semiconductor
Interface circuit between the test circuit of measurement jig and outside.In a specific embodiment, the substrate 200 can pass through
Multi-layer PCB resin substrate presses to be formed, and each layer of PCB resin substrate includes some interconnection structures, and each interconnection structure includes
It is connected through the through-hole interconnection structure of the PCB resin substrates and on PCB resin substrates surface with through-hole interconnection structure
Metal level, when multi-layer PCB resin substrate presses, multiple interconnection structures are electrically connected to form the first metal wire or the second metal wire, because
And allow some first input ends and the second input concentrates on the interface area at the back side of substrate 200.
In another embodiment, the substrate 200 includes front and the back side relative with front, the back side bag of the substrate
Include interface area, some first output ends and the second output end are located at the front of substrate 200, some first input ends and second defeated
Enter end positioned at the back side of substrate 200, the first through hole interconnection structure through substrate 200 and the can be formed in the substrate 200
Two through hole interconnection structures, the first input end and the first output end pass through the first through hole interconnection structure in substrate 200
Electrical connection, second input and the second output end are electrically connected by the second through-hole interconnection structure in substrate 200；Institute
Stating on the back side of substrate 200 also has some first interconnection metal layer and the second interconnection metal layers again again, and described first connects up again
One end of metal level electrically connects with first input end, and the other end of the first interconnection metal layer again is located in interface area, and described
Two again one end of interconnection metal layer electrically connected with the second input, the other end of the described second interconnection metal layer again is located at interface area
In domain, in interface area first again interconnection metal layer and second again interconnection metal layer pass through one or more interfaces with it is outside
Test circuit is connected.
In other embodiments, test circuit (not shown), the test electricity are could be formed with the substrate 200
Road includes the first signal end and secondary signal end, and the first signal end electrically connects with the first connection end of the first testing needle 201, and second
Signal end electrically connects with the second connection end of the second testing needle 203.The test circuit is when being tested, to the first testing needle
201 and second testing needle 203 apply test signal (such as voltage signal or current signal), and to the electric signal of acquisition (such as
Current signal etc.) carry out processing acquisition test parameter (such as resistance etc.).In one embodiment, the substrate 200 includes
Semiconductor substrate (such as silicon substrate or substrate etc.) and the dielectric layer in Semiconductor substrate, formed in the Semiconductor substrate
There is a semiconductor devices (such as transistor etc.), metal interconnecting wires and passive device (such as resistance, electric capacity are formed in the dielectric layer
Deng), semiconductor devices and passive device are connected and composed test circuit, the first signal end and secondary signal by the metal interconnecting wires
End can be drawn by the first metal wire electrically connected in dielectric layer with test circuit and the second metal wire.
Fig. 4 is refer to, Fig. 4 is structural representation when semiconductor test tool of the invention is used for electrical performance testing,
Semiconductor test tool is placed in tester table first；Then encapsulating structure 300 to be tested is placed in semiconductor test tool
On, there are some tested terminals 31 on the encapsulating structure 300 to be tested, the part surface of the tested terminal 31 with it is right
Answer test syringe needle 20 test lead (test lead for the first testing needle 201 the first test lead and the second testing needle 203 second
Test lead) electrical connection；Then apply test signal between the first testing needle 201 and the second testing needle 203, carry out electric property
Test.
Electricity can be carried out by the semiconductor test tool of the present invention simultaneously to multiple tested terminals of encapsulating structure 300
Performance test is learned, improves the efficiency of test and the degree of accuracy of test.
It should be noted that the semiconductor test tool of the present invention can apply to manual test and (manually load to be tested
Encapsulating structure) automatic test can also be applied to (mechanical hand loads encapsulating structure to be tested automatically).
The embodiment of the present invention additionally provide it is a kind of formed aforesaid semiconductor measurement jig method, specifically refer to Fig. 5~
Fig. 9.
It refer to Fig. 5, there is provided substrate 200；At least one, which is formed, in the substrate 200 ranked first testing needle 201, Mei Yipai
In the adjacent mutual dislocation of first testing needle 201 arrangement.
Quantity >=2 of the first testing needle 201 in each row, the adjacent first testing needle dislocation arrangement in each row are
Some testing needles of odd number first referred in each row are centrally located in first straight line, some testing needles of even number first
It is centrally located in second straight line, first straight line is parallel to each other with second straight line.It is adjacent in each row in the embodiment of the present invention
First testing needle 201 dislocation arrangement so that the test syringe needle in each row being subsequently formed is also dislocation arrangement.
Formed with signal circuit in the substrate 200, the signal circuit includes first input end, first defeated
Go out end, the second input and the second output end, first output end to electrically connect with the first connection end of the first testing needle 201,
Second output end electrically connects with the second connection end of the second testing needle 203, the first input end and the second input point
Test circuit not with outside electrically connects.The test circuit is used to provide test signal, and the signal circuit is used for will
Test signal caused by test circuit transmitted to the first testing needle 201 and the second testing needle 203, and will be obtained in test process
Electric signal transmission to test circuit, test circuit is handled the electric signal of reception, obtains test parameter.
Material PCB resins of the substrate 200 etc., the first input end and the first output end pass through positioned at intrabasement
First metal wire electrically connects, and second input and the second output end positioned at intrabasement second metal wire by electrically connecting.
In one embodiment, the substrate 200 includes front and the back side relative with front, and the back side of the substrate includes
Interface area, some first output ends and the second output end are located at the front of substrate 200, with the first testing needle and the second testing needle
Position correspondence, some first input ends and the second input can concentrate on the interface area at the back side of substrate 200 so that some
First input end and the second input can be connected by one or more interfaces with the test circuit of outside, simplify semiconductor
Interface circuit between the test circuit of measurement jig and outside.In a specific embodiment, the substrate 200 can pass through
Multi-layer PCB resin substrate presses to be formed, and each layer of PCB resin substrate includes some interconnection structures, and each interconnection structure includes
It is connected through the through-hole interconnection structure of the PCB resin substrates and on PCB resin substrates surface with through-hole interconnection structure
Metal level, when multi-layer PCB resin substrate presses, multiple interconnection structures are electrically connected to form the first metal wire or the second metal wire, because
And allow some first input ends and the second input concentrates on the interface area at the back side of substrate 200.
In another embodiment, the substrate 200 includes front and the back side relative with front, the back side bag of the substrate
Include interface area, some first output ends and the second output end are located at the front of substrate 200, some first input ends and second defeated
Enter end positioned at the back side of substrate 200, the first through hole interconnection structure through substrate 200 and the can be formed in the substrate 200
Two through hole interconnection structures, the first input end and the first output end pass through the first through hole interconnection structure in substrate 200
Electrical connection, second input and the second output end are electrically connected by the second through-hole interconnection structure in substrate 200；Institute
Stating on the back side of substrate 200 also has some first interconnection metal layer and the second interconnection metal layers again again, and described first connects up again
One end of metal level electrically connects with first input end, and the other end of the first interconnection metal layer again is located in interface area, and described
Two again one end of interconnection metal layer electrically connected with the second input, the other end of the described second interconnection metal layer again is located at interface area
In domain, in interface area first again interconnection metal layer and second again interconnection metal layer pass through one or more interfaces with it is outside
Test circuit is connected.
In other embodiments, test circuit (not shown), the test electricity are could be formed with the substrate 200
Road includes the first signal end and secondary signal end, and the first signal end electrically connects with the first connection end of the first testing needle 201, and second
Signal end electrically connects with the second connection end of the second testing needle 203.The test circuit is when being tested, to the first testing needle
201 and second testing needle 203 apply test signal (such as voltage signal or current signal), and to the electric signal of acquisition (such as
Current signal etc.) carry out processing acquisition test parameter (such as resistance etc.).
First testing needle 201 is cylinder, and the first testing needle 201 obtains along the direction parallel to the surface of substrate 200
Section shape for circle, a diameter of 500 nanometers~500 microns of first testing needle 201.
It should be noted that the section shape of first testing needle can be other shapes, for example described first surveys
Test point is shaped as regular polygon, such as equilateral triangle, square.
In one embodiment, the forming process of first testing needle 201 is：The first gold medal is formed in the substrate 200
Belong to layer (not shown)；Patterned mask layer is formed on the first metal layer；Using the patterned mask layer as mask,
Etch the first metal layer formation at least one and ranked first testing needle 201；Remove the patterned mask layer.
In another embodiment, the forming process of first testing needle 201 is：Formed and sacrificed in the substrate 200
Layer (not shown), have in the sacrifice layer and expose the surface of a substrate 200 at least exhausting hole, it is adjacent logical in each row
Mutual dislocation is arranged between hole；Full the first metal layer is filled in the through hole, forms some first testing needles；Remove described sacrificial
Domestic animal layer.
Mutual dislocation arrangement refers in some odd number through holes in each row between adjacent through-holes in each row
The heart is located in first straight line, and some even number through holes are centrally located in second straight line, and first straight line is mutual with second straight line
It is parallel.
In the through hole fill the first metal layer technique be electroplating technology, in through-holes filling the first metal layer it
Before, in addition to：Conductive layer is formed in the side wall of the through hole and bottom and the surface of sacrifice layer, the conductive layer is as plating
Negative electrode during technique.
The material of the conductive layer is the one or more in Ti, Ta, TiN, TaN etc., and conductive layer can be individual layer or more
Layer (>=2 layers) stacked structure.
In one embodiment, the conductive layer can be double stacked structure, the conductive layer bag of the double stacked structure
Ti layers and the TiN layer on Ti layers are included, or is located at the TaN layers on Ta layers including Ta layers.
The thickness of the conductive layer is less than the radius of through hole, and in one embodiment, the thickness of the conductive layer is 50~200
Nanometer, the formation process of conductive layer is sputtering.
After conductive layer is formed, electroplating technology is carried out, forms the first metal layer layer, the first metal layer is located at conductive layer
Go up and fill through hole, after electroplating technology is carried out, in addition to：Chemical mechanical milling tech is carried out, removes the of sacrificial layer surface
One metal level and conductive layer, form the first testing needle 201, and the first testing needle 201 includes the first metal layer and encirclement described first
The non-proliferation barrier layer of metal level, the non-proliferation barrier layer is made up of remaining conductive layer after cmp, for preventing
Only the metal in metal level spreads into the insulating barrier being subsequently formed.
The material of the first metal layer is copper, gold, tungsten or alloy material or other suitable metal materials.
The surface (lower surface) that first testing needle 201 contacts with the surface of substrate 200 is the first connection end, and first surveys
The surface (top surface) relative with the first connection end of test point 201 is the first test lead.
With reference to reference to figure 6 and Fig. 7, insulating barrier 202 is formed in the side wall of each first testing needle 201.
The forming process of the insulating barrier 202 is：Formed and cover the exhausted of each side wall of first testing needle 201 and top surface
Edge film layer 204；The insulating thin layer 204, which is etched, without mask etching technique forms insulation in the side wall of the first testing needle 201
Layer 202.
The thickness of the insulating barrier 202 is 80 nanometers~400 microns, and the material of the insulating barrier 202 can be that insulation is situated between
One or more in material, such as silica, silicon nitride, silicon oxynitride, fire sand, fire sand.
The insulating barrier 202 can be single or multiple lift (>=2 layers) stacked structure.
The no mask etching technique is anisotropic plasma etching industrial, in one embodiment, the plasma
The etching gas that etching technics uses are specifically as follows CF for fluorine-containing and carbon gas4、C2F6、C4F8、CHF3、CH2F2In one
Kind is several, and source power is 500~1000W, and bias power is 0~100W, and etching cavity pressure is 2~500mtorr.
In the present embodiment, the insulating barrier 202 is the silicon oxide layer of individual layer,
In other embodiments of the invention, the material of the insulating barrier 202 can also be resin material, the resinous wood
Material can be epoxy resin, polyimide resin, polyvinyl resin, benzocyclobutane olefine resin or polybenzoxazoles resin.
The formation process of the insulating barrier 202 is screen printing technique etc..
With reference to reference to figure 8 and Fig. 9, the second testing needle 203, second testing needle 203 are formed on the surface of insulating barrier 202
Around corresponding first testing needle 201.
The forming process of second testing needle 203 is：The covering testing needle 201 of insulating barrier 202 and first is formed to push up
The second metal layer 205 on portion surface；Without second metal layer 205 described in mask etching, the second test is formed on the surface of insulating barrier 202
Pin 203.
The formation process of the second metal layer 205 is sputtering, and the material of second metal layer 205 is copper, gold, tungsten or alloy
Material or other suitable metal materials, the thickness of second metal layer 205 is 60 nanometers~300 microns.
Technique without second metal layer described in mask etching 205 is anisotropic plasma etching industrial, is implemented one
In example, the etching gas that the plasma etching industrial uses is SF6、NF3、Cl2, one or more in HBr, source power is
500~1500W, bias power are 0~100W, and etching cavity pressure is 10~500mtorr.
Each first testing needle 201 forms a test syringe needle with the corresponding testing needle 203 of insulating barrier 202 and second, and
The each row formed is tested in syringe needle, and misplace arrangement between adjacent test syringe needle.
Another embodiment of the present invention additionally provides a kind of method for forming aforesaid semiconductor measurement jig, specifically refer to figure
10~Figure 13.
It refer to Figure 10 and Figure 11, Figure 11 is Figure 10 overlooking the structure diagram, and Figure 10 is Figure 11 along line of cut EF directions
Cross-sectional view, there is provided substrate 200；In the substrate 200 formed dielectric layer 207, state in dielectric layer 207 formed with
At least one ranked first through hole 208 and surround the annular through-hole 209 of each first through hole 208, the adjacent first through hole in each row
Mutual dislocation is arranged between 208, is isolated between first through hole 208 and annular through-hole 209 by certain media layer.
Mutual dislocation arrangement refers to some odd numbers in each row the between adjacent first through hole 208 in each row
One through hole is centrally located in first straight line, such as first straight line AB in Figure 11, the centre bit of some even number first through hole
In in second straight line, for example second straight line CD in Figure 11, first straight line AB are parallel to each other with second straight line CD.
The first through hole 208 and annular through-hole 209 expose the surface of substrate 200, follow-up in the first through hole 208
Fill metal and form the first testing needle, follow-up filling metal forms the second testing needle in second through hole.
Formed with signal circuit or test circuit in the substrate 200, on signal circuit or test circuit
Description refer to previous embodiment, will not be repeated here.
The first through hole 208 is circle, and annular through-hole 209 is annular, and annular through-hole 209 is around the first through hole
208, isolated between first through hole 208 and annular through-hole 209 by certain media layer material.
In other embodiments of the invention, the shape of the first through hole can be other shapes, for example can be
Regular polygon, it is specifically as follows equilateral triangle, square etc..
In one embodiment, the material of the dielectric layer 207 is insulating dielectric materials, such as silica, silicon nitride, nitrogen oxygen
One or more in SiClx, fire sand, fire sand, medium is formed by chemical gaseous phase deposition technique on a substrate 200
Layer 207, then forms patterned photoresist layer on the dielectric layer 207, using the patterned photoresist layer as mask,
The dielectric layer 207 is etched, some first through hole 208 and the annular around each first through hole 208 are formed in dielectric layer 207
Through hole 209；After forming the annular through-hole 209 of first through hole 208, the patterned photoresist layer is removed.
In another embodiment, the material of the dielectric layer 207 is resin glue, and the resin glue is epoxide-resin glue, gathered
Imide resin glue, polyvinyl adhesive, benzocyclobutene resin glue or polybenzoxazoles resin glue, by dry film process, wet
Membrane process, typography or plastic roll technique form dielectric layer 207 in the substrate 200；Then exposed and developed technique is passed through
Some first through hole 208 and the annular through-hole 209 around each first through hole 208 are formed in the dielectric layer, simplifies work
Skill step, formation process are simple.
With reference to figure 12, filling metal forms the first testing needle 201 in first through hole 208 (with reference to figure 10), logical in annular
Filling metal forms the second testing needle 203 in hole 209 (with reference to figure 10).
The testing needle 203 of first testing needle 201 and second is formed by same processing step.
The technique that metal is filled in first through hole 208 and annular through-hole 209 is electroplating technology, in the He of first through hole 208
Before metal being filled in annular through-hole 209, in addition to：The first through hole 208 and annular through-hole 209 side wall and bottom with
And the surface of sacrifice layer forms conductive layer, the negative electrode when conductive layer is as electroplating technology.
The material of the conductive layer is the one or more in Ti, Ta, TiN, TaN etc., and conductive layer can be individual layer or more
Layer (>=2 layers) stacked structure.
In one embodiment, the conductive layer can be double stacked structure, the conductive layer bag of the double stacked structure
Ti layers and the TiN layer on Ti layers are included, or is located at the TaN layers on Ta layers including Ta layers.
The thickness of the conductive layer is less than smaller in both the radius of first through hole 208 and the radius of annular through-hole 209
Radius value, the formation process of conductive layer is sputtering.
After conductive layer is formed, electroplating technology is carried out, forms metal level, the metal level is located on conductive layer and fills the
One through hole 208 and annular through-hole 209, after electroplating technology is carried out, in addition to：Chemical mechanical milling tech is carried out, removes medium
The metal level and conductive layer on 207 surface of layer, form the first testing needle 201 and the second testing needle 203, the first testing needle 201 and the
Two testing needles 203 include metal level and surround the non-proliferation barrier layer of the metal level, and the non-proliferation barrier layer is chemistry
Remaining conductive layer is formed after mechanical lapping, for preventing the metal in metal level from being spread into the insulating barrier being subsequently formed.
The material of the metal level is copper, gold, tungsten or alloy material or other suitable metal materials.
The first testing needle 201 and the second testing needle 203, the first testing needle are formed by electroplating technology simultaneously in the present embodiment
201 and second testing needle 203 will not be by the damage etched so that the surface shape of the first testing needle 201 and the second testing needle 203
Looks are preferable.
With reference to figure 13, the dielectric layer 207 (with reference to figure 12) in the outside of the second testing needle 203 is removed, exposes the second testing needle
203 sidewall surfaces, remaining dielectric layer is as insulating barrier 202 between the first testing needle 201 and the second testing needle 203.
Before the dielectric layer 207 in the outside of the second testing needle 203 is removed, tested in first testing needle 201 and second
Photoresist mask layer is formed on dielectric layer between the testing needle 201 of pin 203 and first and the second testing needle 203；Then with institute
It is mask to state photoresist, and etching removes the dielectric layer 207 in the outside of the second testing needle 203.
The technique of dielectric layer 207 that etching removes the outside of the second testing needle 203 can be wet etching or dry etch process.
Between each testing needle 203 of first testing needle 201 and second and the first testing needle 201 and the second testing needle 203
Insulating barrier form one test syringe needle 20.
The semiconductor test tool of the present invention, made by the advanced semiconductor integration making technology of technique so that formed
Substrate 200 on formed it is some test syringe needles 20 sizes it is identical with surface topography, and it is adjacent test syringe needle 20 between
Away from identical, when the semiconductor test tool that the inventive method is formed is used for into electrical performance testing, the precision of test is improved.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (7)
- A kind of 1. semiconductor test tool, it is characterised in that including：Substrate；An at least row in substrate tests syringe needle, the adjacent test syringe needle mutual dislocation arrangement in each row, each test Syringe needle includes：First testing needle, first testing needle include the first noumenon, positioned at the first noumenon one end the first test lead with And positioned at the first connection end of the first noumenon other end；Cover the insulating barrier on the first noumenon surface of first testing needle；Position The second testing needle in surface of insulating layer around first testing needle, the second testing needle and the first test coaxial needle, second surveys Test point includes the second body, the second test lead positioned at second body one end and the second connection positioned at the second body other end End, the second test end surfaces flush with the first test end surfaces；Wherein, the semiconductor test tool is made by semiconductor integrated technique, including scheme a, scheme b and scheme c：Scheme a, the forming process of first testing needle, insulating barrier and the second testing needle are：First is formed on the substrate Metal level；Etch the first metal layer and form at least one and ranked first testing needle, between adjacent first testing needle in each row Mutual dislocation is arranged；Form the insulating thin layer for covering each first testing needle side wall and top surface；Without mask etching technique The side wall that the insulating thin layer is etched in the first testing needle forms insulating barrier；Formed and cover the insulating barrier and the first testing needle The second metal layer of top surface；Without second metal layer described in mask etching, the second testing needle is formed in surface of insulating layer；Scheme b, the forming process of first testing needle, insulating barrier and the second testing needle are：Formed and sacrificed on the substrate Layer, has at least exhausting hole for exposing substrate surface in the sacrifice layer, mutually wrong between the adjacent through-holes in each row Position arrangement；Full metal is filled in the through hole, forms some first testing needles；Remove the sacrifice layer；It is each to form covering The insulating thin layer of first testing needle side wall and top surface；The insulating thin layer is etched without mask etching technique to survey first The side wall of test point forms insulating barrier；Form the second metal layer for covering the insulating barrier and the first testing needle top surface；Nothing is covered Film etches the second metal layer, and the second testing needle is formed in surface of insulating layer；Scheme c, the forming process of first testing needle, the second testing needle and insulating barrier are：Medium is formed on the substrate Layer, ranked first through hole and the annular through-hole around each first through hole formed with least one in the dielectric layer, first through hole and Isolated between annular through-hole by certain media layer, mutual dislocation is arranged between the adjacent first through hole in each row；First Metal is filled in through hole and forms the first testing needle, metal is filled in annular through-hole and forms the second testing needle；Remove the second test Dielectric layer on the outside of pin, remaining dielectric layer is as insulating barrier between the first testing needle and the second testing needle.
- 2. semiconductor test tool as claimed in claim 1, it is characterised in that if the dislocation arrangement refers in each row Dry odd number test syringe needle is centrally located in first straight line, and some even number test syringe needles are centrally located at second straight line On, first straight line is parallel to each other with second straight line.
- 3. semiconductor test tool as claimed in claim 1, it is characterised in that transmit electricity formed with signal in the substrate Road, the signal circuit include first input end, the first output end, the second input and the second output end, and described first Output end electrically connects with the first connection end of the first testing needle, second output end and the second connection end electricity of the second testing needle The test circuit of connection, the first input end and the second input respectively with outside electrically connects.
- A kind of 4. forming method of semiconductor test tool, it is characterised in that including：Substrate is provided；An at least row is formed on the substrate tests syringe needle, the adjacent test syringe needle mutual dislocation arrangement on the same row, The test syringe needle includes：First testing needle, first testing needle include the first noumenon, first positioned at the first noumenon one end Test lead and positioned at the first connection end of the first noumenon other end；Cover the exhausted of the first noumenon surface of first testing needle Edge layer；The second testing needle positioned at surface of insulating layer around first testing needle, the second testing needle and the first test coaxial needle, Second testing needle includes the second body, the second test lead positioned at second body one end and the positioned at the second body other end Two connection ends, the second test end surfaces flush with the first test end surfaces；Wherein, the semiconductor test tool is made by semiconductor integrated technique, including scheme a, scheme b and scheme c：Scheme a, the forming process of first testing needle, insulating barrier and the second testing needle are：First is formed on the substrate Metal level；Etch the first metal layer and form at least one and ranked first testing needle, between adjacent first testing needle in each row Mutual dislocation is arranged；Form the insulating thin layer for covering each first testing needle side wall and top surface；Without mask etching technique The side wall that the insulating thin layer is etched in the first testing needle forms insulating barrier；Formed and cover the insulating barrier and the first testing needle The second metal layer of top surface；Without second metal layer described in mask etching, the second testing needle is formed in surface of insulating layer；Scheme b, the forming process of first testing needle, insulating barrier and the second testing needle are：Formed and sacrificed on the substrate Layer, has at least exhausting hole for exposing substrate surface in the sacrifice layer, mutually wrong between the adjacent through-holes in each row Position arrangement；Full metal is filled in the through hole, forms some first testing needles；Remove the sacrifice layer；It is each to form covering The insulating thin layer of first testing needle side wall and top surface；The insulating thin layer is etched without mask etching technique to survey first The side wall of test point forms insulating barrier；Form the second metal layer for covering the insulating barrier and the first testing needle top surface；Nothing is covered Film etches the second metal layer, and the second testing needle is formed in surface of insulating layer；Scheme c, the forming process of first testing needle, the second testing needle and insulating barrier are：Medium is formed on the substrate Layer, ranked first through hole and the annular through-hole around each first through hole formed with least one in the dielectric layer, first through hole and Isolated between annular through-hole by certain media layer, mutual dislocation is arranged between the adjacent first through hole in each row；First Metal is filled in through hole and forms the first testing needle, metal is filled in annular through-hole and forms the second testing needle；Remove the second test Dielectric layer on the outside of pin, remaining dielectric layer is as insulating barrier between the first testing needle and the second testing needle.
- 5. the forming method of semiconductor test tool as claimed in claim 4, it is characterised in that the formation of the test syringe needle Process is：At least one is formed on the substrate ranked first testing needle, the adjacent first testing needle mutual dislocation row in each row Cloth；Insulating barrier is formed in the side wall of each first testing needle in each row；The second testing needle is formed on the surface of insulating barrier, Second testing needle is around corresponding first testing needle.
- 6. the forming method of semiconductor test tool as claimed in claim 5, it is characterised in that the first testing needle dislocation arrangement Refer to that some testing needles of odd number first in each row are centrally located in first straight line, some even numbers first are tested Pin is centrally located in second straight line, and first straight line is parallel to each other with second straight line.
- 7. the forming method of semiconductor test tool as claimed in claim 4, it is characterised in that formed with letter in the substrate Number transmission circuit, the signal circuit include first input end, the first output end, the second input and the second output end, First output end electrically connects with the first connection end of the first testing needle, second output end and the second of the second testing needle Connection end electrically connects, and the test circuit of the first input end and the second input respectively with outside electrically connects.
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| CN201410607155.1A CN104360112B (en) | 2014-10-30 | 2014-10-30 | Semiconductor test tool and forming method thereof |
| US14/927,693 US10001509B2 (en) | 2014-10-30 | 2015-10-30 | Semiconductor testing fixture and fabrication method thereof |
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