CN104319248B - The forming method of semiconductor test gauge - Google Patents
The forming method of semiconductor test gauge Download PDFInfo
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- CN104319248B CN104319248B CN201410606075.4A CN201410606075A CN104319248B CN 104319248 B CN104319248 B CN 104319248B CN 201410606075 A CN201410606075 A CN 201410606075A CN 104319248 B CN104319248 B CN 104319248B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Measuring Leads Or Probes (AREA)
Abstract
A kind of forming method of semiconductor test gauge, including：Substrate is provided；Some some test syringe needles being separated from each other are formed on the substrate；Fixed bed on the substrate, the fixed bed fill the space between adjacent test syringe needle and the partial sidewall surface of coverage test syringe needle.By forming fixed bed, the fixed bed improves the mechanical strength of test syringe needle, and fixed bed can disperse the stress tested syringe needle be subject to during tested termination contact, prevents testing needle head from deforming or departing from from substrate surface in test.
Description
Technical field
The present invention relates to semiconductor test technical field, more particularly to a kind of forming method of semiconductor test gauge.
Background technology
Test processing procedure is the electrical functionality for the product that test encapsulation is completed after IC package, to ensure IC functions of dispatching from the factory
On integrality, and the product to having tested is made to classify according to its electrical functionality, as the Appreciation gist of IC different brackets products, most
Make appearance test operation afterwards and to product.
Electrical functionality test is that the various electrical parameters for being directed to product are tested to determine product energy normal operation.
The test of two-point contact such as Kelvin's test etc. on traditional same tested terminal, more using Double ejection pin or double golden hands
Refer to the mode of parallel side-by-side distribution, it is primarily present following deficiency：
1st, the accuracy of manufacture is relatively low：Continuous with semiconductor product size reduces, and is tested the size of terminal and different quilts
The spacing surveyed between terminal is also constantly reducing, in order to comply with this trend, Conventional parallel and the Double ejection pin of column distribution or double golden hands
Refer to test mode bottleneck on the problem of its close spacing to become increasingly conspicuous, required precision is higher and higher, some can not even have been realized
.
2nd, structural strength is weaker：In order to realize that two-point contact is tested in limited space on tested terminal, thimble or gold
Finger is accordingly increasingly thinner, its Mechanical Structure Strength is also more and more weaker.
3rd, service life is shorter：The test contact head of traditional thimble or golden finger is easier to frayed, is especially carried in precision
Go out requirements at the higher level, mechanical strength it is relatively low when, degree of wear bigger, thereby reduces the service life of measurement jig.
4th, measuring accuracy is relatively low：To comply with the light and short growth requirement of semiconductor, increasingly thinner thimble or golden finger
Caused resistance value constantly increases, while when carrying out high-current test, can produce larger pressure drop and influence test number
Judgement；On the other hand, the Double ejection pin of parallel side-by-side distribution or double golden fingers are also easily produced because of offset deviation between the two
The deviation of raw test number；In addition, tradition and the Double ejection pin of column distribution in order to reduce the distance between two pins and use two back to
The way of contact on inclined-plane, contact head easily rotate out of tested terminal and then influence because of the torsion of telescopic spring in its overall structure
Measuring accuracy.
The content of the invention
The present invention solves the problems, such as it is how to improve the precision and stability of existing electrical performance testing.
To solve the above problems, the present invention provides a kind of forming method of semiconductor test gauge, including：Substrate is provided；
Some some test syringe needles being separated from each other are formed on the substrate；Fixed bed on the substrate, the fixed bed are filled out
Fill the space between adjacent test syringe needle and the partial sidewall surface of coverage test syringe needle.
Optionally, the test syringe needle is single metal needle.
Optionally, the forming method of the test syringe needle is：Metal layer is formed in substrate；The metal layer is etched to be formed
Some test syringe needles；The dielectric layer for covering the substrate and test syringe needle is formed, is etched back to remove the dielectric layer of segment thickness, base
Remaining dielectric layer is as fixed bed on bottom.
Optionally, dielectric layer is formed on the substrate, is had in the dielectric layer and is exposed some logical of substrate surface
Hole；Metal is filled in the through hole and forms some test syringe needles；It is etched back to remove the dielectric layer of segment thickness, it is remaining in substrate
Dielectric layer as fixed bed.
Optionally, the test syringe needle is coaxial test syringe needle, and the coaxial test syringe needle includes the first testing needle, described
First testing needle includes the first noumenon, the first test lead positioned at the first noumenon one end and the positioned at the first noumenon other end
One connecting pin；Cover the insulating layer on the first noumenon surface of first testing needle；Positioned at surface of insulating layer around described first
Second testing needle of testing needle, the second testing needle and the first test coaxial needle, the second testing needle include the second body, positioned at second
Second test lead of body one end and the second connection end positioned at the second body other end, the second test end surfaces and the
One test end surfaces flush.
Optionally, the forming process of first testing needle is：The first metal layer is formed on the substrate；Described in etching
The first metal layer forms some first testing needles.
Optionally, the forming process of first testing needle is：Sacrifice layer is formed on the substrate, in the sacrifice layer
With some through holes for exposing substrate surface；Full metal is filled in the through hole, forms some first testing needles；Remove institute
State sacrifice layer.
Optionally, the forming process of the insulating layer and the second testing needle is：Formed and cover each first testing needle side wall
With the insulating thin layer of top surface；No mask etching technique etches the insulating thin layer and is formed in the side wall of the first testing needle
Insulating layer；Form the second metal layer for covering the insulating layer and the first testing needle top surface；Without described in mask etching second
Metal layer, the second testing needle is formed in surface of insulating layer.
Optionally, the forming process of the first detection pin, insulating layer, the second detection pin and fixed bed is：In the base
Form dielectric layer on bottom, the annular through-hole in the dielectric layer formed with some first through hole and around each first through hole, the
Isolated between one through hole and annular through-hole by certain media layer；Metal is filled in first through hole and forms the first testing needle,
Metal is filled in annular through-hole and forms the second testing needle；The dielectric layer of the segment thickness on the outside of the second testing needle is removed, first surveys
Remaining dielectric layer is tested remaining dielectric layer in the substrate between syringe needle and is made as insulating layer between test point and the second testing needle
For fixed bed.
Optionally, formed with signal circuit in the substrate, the signal circuit includes first input end, the
One output terminal, the second input terminal and the second output terminal, first output terminal are electrically connected with the first connecting pin of the first testing needle,
Second output terminal is electrically connected with the second connection end of the second testing needle, the first input end and the second input terminal respectively with
Exterior test circuit is electrically connected.
Compared with prior art, technical scheme has the following advantages：
Semiconductor test gauge forming method of the present invention, including：Substrate is provided；Some mutual points are formed on the substrate
From some test syringe needles；Fixed bed on the substrate, space between the adjacent test syringe needle of fixed bed filling and
The partial sidewall surface of coverage test syringe needle.The fixed bed improves the mechanical strength of test syringe needle, and fixed bed can disperse
The stress being subject to during test syringe needle and tested termination contact, prevents testing needle head from deforming or from substrate table in test
Emaciated face from.
Further, the test syringe needle is coaxial test syringe needle, and the first testing needle and the second testing needle are integrated in a survey
On test point head, the second testing needle surround first testing needle, and insulator separation is used between the second testing needle and the first testing needle,
So that it is less at the same time in the size for ensureing testing needle, lift the mechanical strength of testing needle；On the other hand, the first testing needle and
Two testing needles are coaxially to be distributed so that the precision of spacing is higher between the first testing needle and the second testing needle, improves test
Precision；Another further aspect, needs multiple testing needles (such as Double ejection pin or golden finger) to carry out electrical property compared with the prior art
It can test, of the invention test syringe needle can carry out the test of electric property.
Brief description of the drawings
Fig. 1~Fig. 4 is the structure diagram of one embodiment of the invention semiconductor test gauge；
Fig. 5~Figure 10 is the structure diagram of one embodiment of the invention semiconductor test gauge forming process；
Figure 11~Figure 14 is the structure diagram of another embodiment of the present invention semiconductor test gauge forming process；
Figure 15 is the structure diagram of another embodiment of the present invention semiconductor test gauge；
The structure diagram of Figure 16~Figure 17 further embodiment of this invention semiconductor test gauge forming processes；
The structure diagram of Figure 18~Figure 20 yet another embodiment of the invention semiconductor test gauge forming processes.
Embodiment
As described in the background art, the performance of existing thimble or golden finger still has much room for improvement.
For this reason, the present invention provides a kind of semiconductor test gauge, including：Substrate；It is some in substrate to be separated from each other
Some test syringe needles；Fixed bed in substrate, the fixed bed fill the space between adjacent test syringe needle and covering
Test second test lead of partial sidewall surface the second body one end of syringe needle.The fixed bed is used for the machine for improving test syringe needle
Tool intensity, fixed bed can disperse the stress tested syringe needle be subject to during tested termination contact, and testing needle is prevented in test
Head deforms or departs from from substrate surface.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.When the embodiment of the present invention is described in detail, for purposes of illustration only, schematic diagram can disobey general proportion
Make partial enlargement, and the schematic diagram is example, and it should not be limited the scope of the invention herein.In addition, in reality
The three-dimensional space of length, width and depth should be included in making.
Fig. 1~Fig. 4 is the structure diagram of one embodiment of the invention semiconductor test gauge；Fig. 5~Figure 10 is the present invention
The structure diagram of one embodiment semiconductor test gauge forming process；Figure 11~Figure 14 is another embodiment of the present invention semiconductor
The structure diagram of measurement jig forming process；Figure 15 is the structural representation of another embodiment of the present invention semiconductor test gauge
Figure；The structure diagram of Figure 16~Figure 17 further embodiment of this invention semiconductor test gauge forming processes；Figure 18~Figure 20 sheets
The structure diagram of invention another embodiment semiconductor test gauge forming process.
Please referring to Fig.1, one embodiment of the invention provides a kind of semiconductor test gauge, including：
Substrate 200；
Some test syringe needles 20 being separated from each other in substrate 200；
Fixed bed 210 in substrate 200, the fixed bed 210 are filled the space between adjacent test syringe needle and are covered
The partial sidewall surface of lid test syringe needle 20.
In the present embodiment, the test syringe needle 20 is coaxial test syringe needle, is please referred to Fig.2, and Fig. 2 is a test in Fig. 1
The enlarged structure schematic diagram of syringe needle, the test syringe needle 20 include：
First testing needle 201, first testing needle 201 include the first noumenon, are surveyed positioned at the first of the first noumenon one end
Try end 21 and positioned at the first connecting pin 22 of the first noumenon other end；
Cover the insulating layer 202 on the first noumenon surface of first testing needle 201；
The second testing needle 203 positioned at 202 surface loop of insulating layer around first testing needle 201, the second testing needle 203 with
First testing needle 201 is coaxial, the second testing needle 203 include the second body, positioned at second body one end the second test lead 23 with
And the second connection end 24 positioned at the second body other end, 23 surface of the second test lead and 31 surface of the first test lead are neat
It is flat.
Incorporated by reference to referring to figs. 2 and 3 Fig. 3 is cross-sectional views of the Fig. 2 along hatching AB directions, and described first surveys
The shape of test point 201 is cylinder, and the section shape of corresponding first testing needle 201 is circular, the section of the insulating layer 202
Shape is circular ring shape, and the section shape of second testing needle 203 is circular ring shape.It should be noted that first testing needle
Section shape can be other shapes, for example the section shape of first testing needle can be regular polygon, such as just
Triangle, square.
The test syringe needle of the present invention is formed by semiconductor integration making technology, thus the first testing needle 201 formed
Diameter can be smaller, and in one embodiment, a diameter of 100 nanometers~500 microns of first testing needle 201, can be 200
Nanometer~50 microns.
The width of the corresponding insulating layer 202 and the width of the second testing needle 203 can also very little, in an embodiment
In, the width of the insulating layer 202 is 80 nanometers~400 microns, can be 100 nanometers~10 microns, second testing needle
203 width is 60 nanometers~300 microns, can be 90 nanometers~25 microns.
It should be noted that in other embodiments of the invention, according to the needs of test, first testing needle 201
Diameter, the thickness of insulating layer 202 and the thickness of the 3rd testing needle 203 can be other suitable numerical value.
The material of first testing needle, 201 and second testing needle 203 for copper, gold, tungsten or alloy material or other
Suitable metal material or metal compound material.
The insulating layer 202 is used for the electric isolation between the first testing needle 201 and the second testing needle 203, the present embodiment
In, the top surface (the first test lead 21) of the top surface of the insulating layer 202 and the first testing needle 201 and the second testing needle
203 top surface (the second test lead 23) flushes, i.e., so that the first test lead 21 and the second testing needle of the first testing needle 201
There is no gap between 203 the second test lead 23, in test, prevent the first test lead 21 or the of the first testing needle 201
Second test lead 23 of two testing needles 203 thus between deform there are gap under exterior stress, and cause the
First test lead 21 of one testing needle 201 and the second test lead 23 of the second testing needle 203 make electrical contact with, so as to influence the essence of test
Degree.
The insulating layer 202 can be single or multiple lift (>=2 layers) stacked structure.
The material of the insulating layer 202 can be insulating dielectric materials, such as silica, silicon nitride, silicon oxynitride, nitrogen carbon
One or more in SiClx, fire sand, the material of the insulating layer can also be resin material, such as, epoxy resin, gather
Imide resin, polyvinyl resin, benzocyclobutane olefine resin or polybenzoxazoles resin.
From the direction that the second test lead 23 is directed toward away from the second test lead 23, the part body of second testing needle 203
Width be gradually reduced.Specifically please refer to Fig.1, the width of the part body of second testing needle 203, closer to the second test
Hold 23 its width it is smaller, will more with testing needle 20 be used for test when so that it is adjacent test syringe needle 20 test lead between away from
From increase.
Please continue to refer to Fig. 1, also there is fixed bed 210, the surface of the fixed bed 210 is less than survey in the substrate 200
The top surface of test point first 20, and the fixed bed 210 covers the partial sidewall surface of the test syringe needle 20, the fixed bed
210 are used to improve the mechanical strength for testing syringe needle 20, when fixed bed 210 can disperse to test syringe needle 20 with tested termination contact
The stress being subject to, prevents test syringe needle 20 from deforming or departing from from 200 surface of substrate in test.
The material of the fixed bed 210 for silica, silicon nitride, silicon oxynitride, fire sand, fire sand or resin,
Or other suitable materials.
The thickness of the fixed bed 210 can be the 1/4~2/3 of 20 height of testing needle.
By the present invention test syringe needle 20 apply is carrying out electrical performance testing when, in one embodiment, can by
The test syringe needle of invention is applied to resistance test or high-current test, will test one end and the tested termination contact of syringe needle 20,
Make the first test lead 21 of the first testing needle 201 and 23 surface of the second test lead of the second testing needle 203 and tested terminal
Surface contacts, and applies test voltage between the first testing needle 201 and the second testing needle 202, and measurement passes through the first testing needle
201st, the electric current on the second testing needle 203 and tested terminal, and pass through test voltage divided by electric current obtains test electricity
Resistance.
In one embodiment, when carrying out the test of resistance using the test syringe needle 20 of the present invention, due to the first testing needle 201
It is coaxial with the second testing needle 203, thus tests electric current and uniformly spread around by the first testing needle 201, flows to the
Two testing needles 203, i.e., so that tested terminal between the first testing needle 201 and the second testing needle 203 annular region (with it is exhausted
The part that edge layer 202 contacts) on the electric current that flows through of different directions be average, improve the precision of test.
In other embodiments of the invention, the test syringe needle of the present invention can be applied to the electric property of other forms
Test, such as the test that multiple test syringe needles can be applied to carry out electric property, for example test electric current can be from a testing needle
The first testing needle or the second testing needle of head flow to the first testing needle or the second testing needle of another test syringe needle, or test
Circuit can flow to the first testing needle of another test syringe needle from second testing needle for testing syringe needle and the second testing needle
With the second testing needle.
The quantity of the test syringe needle 20 is more than or equal to two, and in a specific embodiment, the test syringe needle 20 exists
Arrange in substrate 200 in ranks.
Formed with signal circuit in the substrate 200, the signal circuit includes first input end, first defeated
Outlet, the second input terminal and the second output terminal, first output terminal are electrically connected with the first connecting pin of the first testing needle 201,
Second output terminal is electrically connected with the second connection end of the second testing needle 203, the first input end and the second input terminal point
It is not electrically connected with exterior test circuit.The test circuit is used to provide test signal, and the signal circuit is used for will
The test signal that test circuit produces is transmitted to the first testing needle 201 and the second testing needle 203, and will be obtained in test process
Electric signal transmission to test circuit, test circuit handles the electric signal of reception, obtains test parameter.
Material PCB resins of the substrate 200 etc., the first input end and the first output terminal pass through positioned at intrabasement
First metal wire is electrically connected, and second input terminal and the second output terminal positioned at intrabasement second metal wire by being electrically connected.
In one embodiment, the substrate 200 includes front and the back side opposite with front, and the back side of the substrate includes
Interface area, some first output terminals and the second output terminal are located at the front of substrate 200, with the first testing needle and the second testing needle
Position correspondence, some first input ends and the second input terminal can concentrate on the interface area at 200 back side of substrate so that some
First input end and the second input terminal can be connected by one or more interfaces with exterior test circuit, simplify semiconductor
Interface circuit between the test circuit of measurement jig and outside.In a specific embodiment, the substrate 200 can pass through
Multi-layer PCB resin substrate presses to be formed, and each layer of PCB resin substrate includes some interconnection structures, and each interconnection structure includes
It is connected through the through-hole interconnection structure of the PCB resin substrates and on PCB resin substrates surface with through-hole interconnection structure
Metal layer, when multi-layer PCB resin substrate presses, multiple interconnection structures are electrically connected to form the first metal wire or the second metal wire, because
And allow some first input ends and the second input terminal concentrates on the interface area at 200 back side of substrate.
In another embodiment, the substrate 200 includes front and the back side opposite with front, the back side bag of the substrate
Include interface area, some first output terminals and the second output terminal are located at the front of substrate 200, some first input ends and second defeated
Enter end positioned at the back side of substrate 200, the first through hole interconnection structure through substrate 200 and the can be formed in the substrate 200
Two through hole interconnection structures, the first input end and the first output terminal pass through the first through hole interconnection structure in substrate 200
It is electrically connected, second input terminal and the second output terminal are electrically connected by the second through-hole interconnection structure in substrate 200；Institute
Stating on the back side of substrate 200 also has some first interconnection metal layer and the second interconnection metal layers again again, and described first connects up again
One end of metal layer is electrically connected with first input end, and the other end of the first interconnection metal layer again is located in interface area, and described
Two again one end of interconnection metal layer be electrically connected with the second input terminal, the other end of the described second interconnection metal layer again is located at interface area
In domain, in interface area first again interconnection metal layer and second again interconnection metal layer pass through one or more interfaces with it is exterior
Test circuit is connected.
In other embodiments, test circuit (not shown), the test electricity are could be formed with the substrate 200
Road includes the first signal end and secondary signal end, and the first signal end is electrically connected with the first connecting pin of the first testing needle 201, and second
Signal end is electrically connected with the second connection end of the second testing needle 203.The test circuit is when being tested, to the first testing needle
201 and second testing needle 203 apply test signal (such as voltage signal or current signal), and to the electric signal of acquisition (such as
Current signal etc.) carry out processing acquisition test parameter (such as resistance etc.).
With reference to figure 4, Fig. 4 is structure diagram when semiconductor test gauge of the invention is used for electrical performance testing, first
First semiconductor test gauge is placed in tester table；Then encapsulating structure 300 to be tested is placed on semiconductor test gauge,
There are some tested terminals 31, the tested terminal 31 can be encapsulation to be tested on the encapsulating structure to be tested 300
The pad or pin of structure 300, the part surface of the tested terminal 31 (are tested with the test lead of corresponding test syringe needle 20
Hold the second test lead of the first test lead and the second testing needle 203 for the first testing needle 201) it is electrically connected；Then surveyed first
Apply test signal between 201 and second testing needle 203 of test point, carry out the test of electric property.
Electricity can be carried out at the same time to multiple tested terminals of encapsulating structure 300 by the semiconductor test gauge of the present invention
Performance test is learned, improves the efficiency of test and the accuracy of test.
It should be noted that the semiconductor test gauge of the present invention can be applied to manual test and (manually load to be tested
Encapsulating structure) automatic test can also be applied to (mechanical hand loads encapsulating structure to be tested automatically).
The embodiment of the present invention additionally provide it is a kind of formed aforesaid semiconductor measurement jig method, specifically refer to Fig. 5~
Figure 10.
It refer to Fig. 5, there is provided substrate 200；Some first testing needles 201 are formed in the substrate 200.
First testing needle 201 is cylinder, and the first testing needle 201 is obtained along the direction parallel to 200 surface of substrate
Section shape be circle, a diameter of 500 nanometers~500 microns of first testing needle 201, formed in the substrate 200
The first testing needle 201 quantity be more than or equal to 2, in the present embodiment, to form 3 the first testing needles 201 on a substrate 200
As example.
It should be noted that the section shape of first testing needle can be other shapes, for example described first surveys
The shape of test point is regular polygon, such as equilateral triangle, square.
In one embodiment, the forming process of first testing needle 201 is：The first gold medal is formed in the substrate 200
Belong to layer (not shown)；Patterned mask layer is formed on the first metal layer；Using the patterned mask layer as mask,
Etch the first metal layer and form some first testing needles 201；Remove the patterned mask layer.
In another embodiment, the forming process of first testing needle 201 is：Formed and sacrificed in the substrate 200
Layer (not shown), has some through holes for exposing 200 surface of substrate in the sacrifice layer；Filled in the through hole full
The first metal layer, forms some first testing needles；Remove the sacrifice layer.
In the through hole fill the first metal layer technique be electroplating technology, in through-holes filling the first metal layer it
Before, further include：Conductive layer is formed in the side wall of the through hole and bottom and the surface of sacrifice layer, the conductive layer is as plating
Cathode during technique.
The material of the conductive layer is the one or more in Ti, Ta, TiN, TaN etc., and conductive layer can be individual layer or more
Layer (>=2 layers) stacked structure.
In one embodiment, the conductive layer can be double stacked structure, the conductive layer bag of the double stacked structure
Ti layers and the TiN layer on Ti layers are included, or including the Ta layers of TaN layers being located on Ta layers.
The thickness of the conductive layer is less than the radius of through hole, and in one embodiment, the thickness of the conductive layer is 50~200
Nanometer, the formation process of conductive layer is sputtering.
After conductive layer is formed, electroplating technology is carried out, forms the first metal layer layer, the first metal layer is located at conductive layer
Go up and fill through hole, after electroplating technology is carried out, further include：Chemical mechanical milling tech is carried out, removes the of sacrificial layer surface
One metal layer and conductive layer, form the first testing needle 201, and the first testing needle 201 includes the first metal layer and encirclement described first
The non-proliferation barrier layer of metal layer, the non-proliferation barrier layer is made of remaining conductive layer after chemical mechanical grinding, for preventing
Only the metal in metal layer is spread into the insulating layer being subsequently formed.
The material of the first metal layer is copper, gold, tungsten or alloy material or other suitable metal materials.
The surface (lower surface) that first testing needle 201 is contacted with 200 surface of substrate is the first connecting pin, and first surveys
The surface (top surface) opposite with the first connecting pin of test point 201 is the first test lead.
Formed with signal circuit in the substrate 200, the signal circuit includes first input end, first defeated
Outlet, the second input terminal and the second output terminal, first output terminal are electrically connected with the first connecting pin of the first testing needle 201,
Second output terminal is electrically connected with the second connection end of the second testing needle 203, the first input end and the second input terminal point
It is not electrically connected with exterior test circuit.The test circuit is used to provide test signal, and the signal circuit is used for will
The test signal that test circuit produces is transmitted to the first testing needle 201 and the second testing needle 203, and will be obtained in test process
Electric signal transmission to test circuit, test circuit handles the electric signal of reception, obtains test parameter.
Material PCB resins of the substrate 200 etc., the first input end and the first output terminal pass through positioned at intrabasement
First metal wire is electrically connected, and second input terminal and the second output terminal positioned at intrabasement second metal wire by being electrically connected.
In one embodiment, the substrate 200 includes front and the back side opposite with front, and the back side of the substrate includes
Interface area, some first output terminals and the second output terminal are located at the front of substrate 200, with the first testing needle and the second testing needle
Position correspondence, some first input ends and the second input terminal can concentrate on the interface area at 200 back side of substrate so that some
First input end and the second input terminal can be connected by one or more interfaces with exterior test circuit, simplify semiconductor
Interface circuit between the test circuit of measurement jig and outside.In a specific embodiment, the substrate 200 can pass through
Multi-layer PCB resin substrate presses to be formed, and each layer of PCB resin substrate includes some interconnection structures, and each interconnection structure includes
It is connected through the through-hole interconnection structure of the PCB resin substrates and on PCB resin substrates surface with through-hole interconnection structure
Metal layer, when multi-layer PCB resin substrate presses, multiple interconnection structures are electrically connected to form the first metal wire or the second metal wire, because
And allow some first input ends and the second input terminal concentrates on the interface area at 200 back side of substrate.
In another embodiment, the substrate 200 includes front and the back side opposite with front, the back side bag of the substrate
Include interface area, some first output terminals and the second output terminal are located at the front of substrate 200, some first input ends and second defeated
Enter end positioned at the back side of substrate 200, the first through hole interconnection structure through substrate 200 and the can be formed in the substrate 200
Two through hole interconnection structures, the first input end and the first output terminal pass through the first through hole interconnection structure in substrate 200
It is electrically connected, second input terminal and the second output terminal are electrically connected by the second through-hole interconnection structure in substrate 200；Institute
Stating on the back side of substrate 200 also has some first interconnection metal layer and the second interconnection metal layers again again, and described first connects up again
One end of metal layer is electrically connected with first input end, and the other end of the first interconnection metal layer again is located in interface area, and described
Two again one end of interconnection metal layer be electrically connected with the second input terminal, the other end of the described second interconnection metal layer again is located at interface area
In domain, in interface area first again interconnection metal layer and second again interconnection metal layer pass through one or more interfaces with it is exterior
Test circuit is connected.
In other embodiments, test circuit (not shown), the test electricity are could be formed with the substrate 200
Road includes the first signal end and secondary signal end, and the first signal end is electrically connected with the first connecting pin of the first testing needle 201, and second
Signal end is electrically connected with the second connection end of the second testing needle 203.The test circuit is when being tested, to the first testing needle
201 and second testing needle 203 apply test signal (such as voltage signal or current signal), and to the electric signal of acquisition (such as
Current signal etc.) carry out processing acquisition test parameter (such as resistance etc.).In one embodiment, the substrate 200 includes
Semiconductor substrate (such as silicon substrate or substrate etc.) and the dielectric layer in Semiconductor substrate, form in the Semiconductor substrate
There is a semiconductor devices (such as transistor etc.), metal interconnecting wires and passive device (such as resistance, capacitance are formed in the dielectric layer
Deng), semiconductor devices and passive device are connected and composed test circuit, the first signal end and secondary signal by the metal interconnecting wires
End can be drawn by the first metal wire being electrically connected in dielectric layer with test circuit and the second metal wire.
With reference to reference to figure 6 and Fig. 7, insulating layer 202 is formed on the side wall of each first testing needle 201.
The forming process of the insulating layer 202 is：Formed and cover the exhausted of each first testing needle, 201 side wall and top surface
Edge film layer 204；No mask etching technique etches the insulating thin layer 204 and forms insulation in the side wall of the first testing needle 201
Layer 202.
The thickness of the insulating layer 202 is 80 nanometers~400 microns, and the material of the insulating layer 202 can be that insulation is situated between
One or more in material, such as silica, silicon nitride, silicon oxynitride, fire sand, fire sand.
The insulating layer 202 can be single or multiple lift (>=2 layers) stacked structure.
The no mask etching technique is anisotropic plasma etching industrial, in one embodiment, the plasma
The etching gas that etching technics uses are specifically as follows CF for fluorine-containing and carbon gas4、C2F6、C4F8、CHF3、CH2F2In one
Kind is several, and source power is 500~1000W, and bias power is 0~100W, and etching cavity pressure is 2~500mtorr.
In the present embodiment, the insulating layer 202 is the silicon oxide layer of individual layer,
In other embodiments of the invention, the material of the insulating layer 202 can also be resin material, the resinous wood
Material can be epoxy resin, polyimide resin, polyvinyl resin, benzocyclobutane olefine resin or polybenzoxazoles resin.
The formation process of the insulating layer 202 is screen printing technique etc..
With reference to reference to figure 8 and Fig. 9, the second testing needle 203, second testing needle 203 are formed on the surface of insulating layer 202
Around corresponding first testing needle 201.
The forming process of second testing needle 203 is：Covering 202 and first testing needle 201 of insulating layer is formed to push up
The second metal layer 205 on portion surface；Without second metal layer 205 described in mask etching, the second test is formed on 202 surface of insulating layer
Pin 203.
The formation process of the second metal layer 205 is sputtering, and 205 material of second metal layer is copper, gold, tungsten or alloy
Material or other suitable metal materials, the thickness of second metal layer 205 is 60 nanometers~300 microns.
The technique of second metal layer 205 described in no mask etching is anisotropic plasma etching industrial, is implemented one
In example, the etching gas that the plasma etching industrial uses is SF6、NF3、Cl2, one or more in HBr, source power is
500~1500W, bias power are 0~100W, and etching cavity pressure is 10~500mtorr.
Each first testing needle 201 forms a test syringe needle 20 with corresponding 202 and second testing needle 203 of insulating layer.
0 is please referred to Fig.1, fixed bed 210 is formed in the substrate 200, the fixed bed 210 fills adjacent test syringe needle
The partial sidewall surface in space and coverage test syringe needle 20 between 20.
The forming process of the fixed bed 210 is：Form the fixation material for covering 20 surface of the substrate 200 and test syringe needle
The bed of material；The fixed material layer is etched back to, forms fixed bed 210.
Before fixed material layer is etched back to, step is further included：Flatening process is carried out to the fixed material layer, such as
Chemical mechanical milling tech, exposes the top surface of test syringe needle 20；Then the fixation material layer being etched back to after planarization, shape
Into fixed bed 210.
In one embodiment, can be in the top table of the test syringe needle 20 before the fixed material layer is etched back to
Form mask layer on face, the mask layer is when being etched back to fixed material layer, and the damage that prevents syringe needle from being etched is solid being formed
After given layer 210, the mask layer is removed.
In another embodiment, before the fixed material layer of etching, if when not forming mask layer on testing syringe needle 20,
Then the material of the material and insulating layer 202 of the fixed bed 210 differs so that when etching fixes material layer, insulating layer 202 is not
It can be etched or etch rate is very low, ensure the integrality of insulating layer 202.
The material of the fixed bed 210 for silica, silicon nitride, silicon oxynitride, fire sand, fire sand or resin,
Or other suitable materials.
The thickness of the fixed bed 210 can be the 1/4~2/3 of 20 height of testing needle.
Another embodiment of the present invention additionally provides a kind of method for forming foregoing semiconductor test gauge, specifically refer to
Figure 11~Figure 14.
Please refer to Fig.1 1, there is provided substrate 200；Dielectric layer 207 is formed in the substrate 200, states and is formed in dielectric layer 207
There are some first through hole 208 and the annular through-hole 209 around each first through hole 208, first through hole 208 and annular through-hole 209
Between isolated by certain media layer.
The first through hole 208 and annular through-hole 209 expose the surface of substrate 200, follow-up in the first through hole 208
Fill metal and form the first testing needle, follow-up filling metal forms the second testing needle in second through hole.
Formed with signal circuit or test circuit in the substrate 200, on signal circuit or test circuit
Description refer to previous embodiment, and details are not described herein.
With reference to figure 12, Figure 12 is the overlooking the structure diagram of part-structure in Figure 11, and the first through hole 208 is circle,
Annular through-hole 209 is circular ring shape, annular through-hole 209 around the first through hole 208, first through hole 208 and annular through-hole 209 it
Between isolated by certain media layer material.
In other embodiments of the invention, the shape of the first through hole can be other shapes, for example can be
Regular polygon, is specifically as follows equilateral triangle, square etc..
In one embodiment, the material of the dielectric layer 207 is insulating dielectric materials, such as silica, silicon nitride, nitrogen oxygen
One or more in SiClx, fire sand, fire sand, medium is formed by chemical gaseous phase deposition technique on a substrate 200
Layer 207, then forms patterned photoresist layer on the dielectric layer 207, using the patterned photoresist layer as mask,
The dielectric layer 207 is etched, some first through hole 208 and the annular around each first through hole 208 are formed in dielectric layer 207
Through hole 209；After forming the annular through-hole 209 of first through hole 208, the patterned photoresist layer is removed.
In another embodiment, the material of the dielectric layer 207 is resin glue, and the resin glue is epoxide-resin glue, gathers
Imide resin glue, polyvinyl adhesive, benzocyclobutene resin glue or polybenzoxazoles resin glue, by dry film process, wet
Membrane process, typography or plastic roll technique form dielectric layer 207 in the substrate 200；Then exposed and developed technique is passed through
Some first through hole 208 and the annular through-hole 209 around each first through hole 208 are formed in the dielectric layer.
With reference to figure 13, filling metal forms the first testing needle 201 in first through hole 208 (with reference to figure 11), logical in annular
Filling metal forms the second testing needle 203 in hole 209 (with reference to figure 11).
First testing needle, 201 and second testing needle 203 is formed by same processing step.
The technique that metal is filled in first through hole 208 and annular through-hole 209 is electroplating technology, in 208 He of first through hole
Before filling metal in annular through-hole 209, further include：The first through hole 208 and annular through-hole 209 side wall and bottom with
And the surface of sacrifice layer forms conductive layer, the cathode when conductive layer is as electroplating technology.
The material of the conductive layer is the one or more in Ti, Ta, TiN, TaN etc., and conductive layer can be individual layer or more
Layer (>=2 layers) stacked structure.
In one embodiment, the conductive layer can be double stacked structure, the conductive layer bag of the double stacked structure
Ti layers and the TiN layer on Ti layers are included, or including the Ta layers of TaN layers being located on Ta layers.
The thickness of the conductive layer is less than smaller in both the radius of first through hole 208 and the radius of annular through-hole 209
Radius value, the formation process of conductive layer is sputtering.
After conductive layer is formed, electroplating technology is carried out, forms metal layer, the metal layer is located on conductive layer and fills the
One through hole 208 and annular through-hole 209, after electroplating technology is carried out, further include：Chemical mechanical milling tech is carried out, removes medium
The metal layer and conductive layer on 207 surface of layer, form the first testing needle 201 and the second testing needle 203, the first testing needle 201 and the
Two testing needles 203 include metal layer and surround the non-proliferation barrier layer of the metal layer, and the non-proliferation barrier layer is chemistry
Remaining conductive layer is formed after mechanical lapping, for preventing the metal in metal layer from being spread into the insulating layer being subsequently formed.
The material of the metal layer is copper, gold, tungsten or alloy material or other suitable metal materials.
The first testing needle 201 and the second testing needle 203, the first testing needle are formed by electroplating technology at the same time in the present embodiment
201 and second damage that will not be etched of testing needle 203 so that the surface shape of the first testing needle 201 and the second testing needle 203
Looks are preferable.
With reference to figure 14, the segment thickness dielectric layer 207 (with reference to figure 13) in the outside of the second testing needle 203 is removed, first tests
Remaining dielectric layer is remained in the substrate 200 between needle adjacent 20 as insulating layer 202 between 201 and second testing needle 203 of pin
Remaining dielectric layer is covered and surveyed less than the surface for testing syringe needle 20 as fixed bed 210, the top surface of the fixed bed 210
The partial sidewall of test point head.
Before the certain media layer 207 in the outside of the second testing needle 203 is removed, in first testing needle 201 and second
Photoresist mask layer is formed on dielectric layer between 203 and first testing needle 201 of testing needle and the second testing needle 203；Then
Using the photoresist as mask, etching removes the dielectric layer 207 of the segment thickness in the outside of the second testing needle 203, remaining medium
Layer is used as fixed bed 210.
The thickness of institute's fixed bed 210 is the 1/4~2/3 of test 20 height of syringe needle.
207 technique of dielectric layer that etching removes the outside of the second testing needle 203 can be wet etching or dry etch process.
In a specific embodiment, when the material of the dielectric layer 207 is silica, the quarter of wet-etching technology use
Erosion solution is hydrofluoric acid solution, and the etching gas that dry etching uses is fluorocarbon gas；The material of the dielectric layer 207
For silicon nitride when, the etching solution that wet-etching technology uses is phosphoric acid solution, and the etching gas that dry etching uses is carbon fluorine
Hydrogen compound gas；When the material of the dielectric layer 207 is resin glue, the etching solution that wet-etching technology uses is molten for sulfuric acid
Liquid, the etching gas that dry etching uses is oxygen.
A kind of semiconductor test gauge is additionally provided in another embodiment of the present invention, please refers to Fig.1 5, including：
Substrate 100；
Some some test syringe needles 101 being separated from each other in substrate 100；
Fixed bed 102 in substrate 100, the fixed bed 102 fill it is adjacent test syringe needle 101 between space and
The partial sidewall surface of coverage test syringe needle 101.
In the present embodiment, the test syringe needle 101 is single metal needle.
In the present embodiment, the test syringe needle 101 is circle along the section shape obtained parallel to 100 surface direction of substrate
Shape, a diameter of 100 nanometers~300 microns of the test syringe needle.
In other embodiments of the invention, the edge of the test syringe needle 101 is obtained parallel to 100 surface direction of substrate
Section shape can be other shapes, for example the section shape of the test syringe needle 101 can be regular polygon, such as positive three
It is angular, square.
The material of the test syringe needle 101 for copper, gold, tungsten or alloy material or other suitable metal materials or
Person's metal compound material.
The quantity for testing syringe needle 101 is more than or equal to 2.
Also there is fixed bed 102, the surface of the fixed bed 102 is less than the top for testing syringe needle 101 in the substrate 100
Surface, and the fixed bed 102 covers the partial sidewall surface of the test syringe needle 101, the fixed bed 102, which is used to improve, to be surveyed
The mechanical strength of test point first 101, fixed bed 102 can disperse the stress tested syringe needle 101 be subject to during tested termination contact,
Prevent test syringe needle 101 from deforming or departing from from 100 surface of substrate in test.
The material of the fixed bed 102 for silica, silicon nitride, silicon oxynitride, fire sand, fire sand or resin,
Or other suitable materials.
The thickness of the fixed bed 102 can be the 1/4~2/3 of 101 height of testing needle.
Include some input terminals and output formed with signal circuit, the signal circuit in the substrate 100
End, the output terminal are electrically connected with testing the lower surface of syringe needle 101, and the input terminal is electrically connected with exterior test circuit.
The test circuit is used to provide test signal, and the test signal that the signal circuit is used to produce test circuit is transmitted
To test syringe needle 101, and by the electric signal transmission obtained in test process to test circuit, electric signal of the test circuit to reception
Handled, obtain test parameter.
Material PCB resins of the substrate 100 etc., the input terminal and output terminal pass through positioned at intrabasement metal wire electricity
Connection.
In one embodiment, the substrate 100 includes front and the back side opposite with front, and the back side of the substrate includes
Interface area, some output terminals are located at the front of substrate 100, the position correspondence with testing 101 lower surface of syringe needle, some described
Input terminal concentrates on the interface area at 100 back side of substrate so that some input terminals can pass through one or more interfaces and outside
Test circuit be connected, simplify semiconductor test gauge and outside test circuit between interface circuit.It is specific one
In embodiment, the substrate 100 can press to be formed by multi-layer PCB resin substrate, if each layer of PCB resin substrate includes
Dry interconnection structure, each interconnection structure are included through the through-hole interconnection structure of the PCB resin substrates and positioned at PCB resin substrates
The metal layer being connected on surface with through-hole interconnection structure, when multi-layer PCB resin substrate presses, multiple interconnection structures are electrically connected to form
Metal wire, thus category line can bend arrangement so that some output terminals concentrate on the interface area at 100 back side of substrate.
In another embodiment, the substrate 100 includes front and the back side opposite with front, the back side bag of the substrate
Include interface area, some first output terminals and the second output terminal are located at the front of substrate 100, some first input ends and second defeated
Enter end positioned at the back side of substrate 100, the first through hole interconnection structure through substrate 100 and the can be formed in the substrate 100
Two through hole interconnection structures, the first input end and the first output terminal pass through the first through hole interconnection structure in substrate 100
It is electrically connected, second input terminal and the second output terminal are electrically connected by the second through-hole interconnection structure in substrate 100；Institute
Stating on the back side of substrate 100 also has some first interconnection metal layer and the second interconnection metal layers again again, and described first connects up again
One end of metal layer is electrically connected with first input end, and the other end of the first interconnection metal layer again is located in interface area, and described
Two again one end of interconnection metal layer be electrically connected with the second input terminal, the other end of the described second interconnection metal layer again is located at interface area
In domain, in interface area first again interconnection metal layer and second again interconnection metal layer pass through one or more interfaces with it is exterior
Test circuit is connected.
In other embodiments, test circuit (not shown), the test electricity are could be formed with the substrate 100
Road includes signal end, and signal end is electrically connected with testing the lower surface of syringe needle 101.The test circuit is led to when being tested
Cross signal end and test signal (such as voltage signal or current signal) is applied to test syringe needle 101, during the test, obtain electricity
Signal (such as current signal etc.), and processing acquisition test parameter (such as resistance etc.) is carried out to the electric signal of acquisition.
Further embodiment of this invention additionally provides a kind of method for forming above-mentioned semiconductor test gauge, specifically refer to figure
16~Figure 17.
Please refer to Fig.1 6, there is provided substrate 100；Some test syringe needles 101 are formed in the substrate 100.
It is described test syringe needle 101 forming process be：Metal layer (not shown) is formed in the substrate 100；
Patterned mask layer is formed on metal layer；Using the patterned mask layer as mask, the metal layer is etched, in the base
Some test syringe needles are formed on bottom.
Formed with signal circuit or test circuit in the substrate 100.On signal circuit or test circuit
Description, refer to previous embodiment, details are not described herein.
The material of the metal layer is copper, gold, tungsten either alloy material or other suitable metal materials or metal
Compound-material, etches the metal layer and uses anisotropic dry etch process.
7 are please referred to Fig.1, forms the dielectric layer for covering the substrate 100 and test syringe needle 101, it is thick to be etched back to removal part
The dielectric layer of degree, remaining dielectric layer is as fixed bed 102 in substrate.
The material of the dielectric layer for silica, silicon nitride, silicon oxynitride, fire sand, fire sand or resin or
Other suitable materials.
The technique for being etched back to remove the dielectric layer of segment thickness can be wet-etching technology or dry etch process, specifically
Etching technics refer to previous embodiment relevant portion introduction, details are not described herein.
Further embodiment of this invention additionally provides a kind of method for forming above-mentioned semiconductor test gauge, specifically refer to figure
18~Figure 20.
Please refer to Fig.1 8, there is provided substrate 100；Dielectric layer 104 is formed in the substrate 100, is had in the dielectric layer 104
There are some through holes 105 for exposing 100 surface of substrate.
Metal is subsequently filled in through hole 105, forms test syringe needle.
In one embodiment, the material of the dielectric layer 104 is insulating dielectric materials, such as silica, silicon nitride, nitrogen oxygen
One or more in SiClx, fire sand, fire sand, medium is formed by chemical gaseous phase deposition technique in substrate 100
Layer 104, then forms patterned photoresist layer on the dielectric layer 104, using the patterned photoresist layer as mask,
The dielectric layer 104 is etched, some through holes 105 are formed in dielectric layer 104；After forming through hole 105, remove described patterned
Photoresist layer.
In another embodiment, the material of the dielectric layer 104 is resin glue, and the resin glue is epoxide-resin glue, gathers
Imide resin glue, polyvinyl adhesive, benzocyclobutene resin glue or polybenzoxazoles resin glue, by dry film process, wet
Membrane process, typography or plastic roll technique form dielectric layer 104 in the substrate 100；Then exposed and developed technique is passed through
Some through holes 105 are formed in the dielectric layer 104.
Formed with signal circuit or test circuit in the substrate 100.On signal circuit or test circuit
Description, refer to previous embodiment, details are not described herein.
9 are please referred to Fig.1, filling metal forms test syringe needle 101 in the through hole 105 (with reference to figure 18).
The fill process of the metal is electroplating technology, specifically refer to previous embodiment relevant portion introduction, herein not
Repeat again.
0 is please referred to Fig.2, is etched back to remove the dielectric layer 104 (with reference to figure 19) of segment thickness, remaining Jie in substrate 100
Matter layer is as fixed bed 102.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, are not departing from this
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the scope of restriction.
Claims (5)
- A kind of 1. forming method of semiconductor test gauge, it is characterised in that including：Substrate is provided；Some some coaxial test syringe needles being separated from each other are formed on the substrate；Fixed bed on the substrate, space and coverage test syringe needle between the adjacent test syringe needle of fixed bed filling Partial sidewall surface；Wherein, the coaxial test syringe needle is formed by semiconductor integration making technology, passes through semiconductor integration making technology shape Process into test syringe needle and fixed bed includes scheme a and b；Scheme a, forms the first testing needle on the substrate；Formed and cover the exhausted of each first testing needle side wall and top surface Edge film layer；No mask etching technique etches the insulating thin layer and forms insulating layer in the side wall of the first testing needle；Formation is covered Cover the second metal layer of the insulating layer and the first testing needle top surface；Without second metal layer described in mask etching, insulating Layer surface forms the second testing needle；Form the fixation material layer for covering the substrate and test needle surface；It is etched back to described solid Determine material layer, form fixed bed；Scheme b, forms dielectric layer on the substrate, formed with some first through hole and around each first in the dielectric layer The annular through-hole of through hole, is isolated between first through hole and annular through-hole by certain media layer；Metal is filled in first through hole The first testing needle is formed, metal is filled in annular through-hole and forms the second testing needle；The part removed on the outside of the second testing needle is thick The dielectric layer of degree, remaining dielectric layer tests the base between syringe needle as insulating layer between the first testing needle and the second testing needle Remaining dielectric layer is as fixed bed on bottom.
- 2. the forming method of semiconductor test gauge as claimed in claim 1, it is characterised in that the coaxial test syringe needle bag The first testing needle is included, first testing needle includes the first noumenon, the first test lead positioned at the first noumenon one end and is located at First connecting pin of the first noumenon other end；Cover the insulating layer on the first noumenon surface of first testing needle；Positioned at insulation Layer surface surround the second testing needle of first testing needle, the second testing needle and the first test coaxial needle, the second testing needle bag Include the second body, the second test lead positioned at second body one end and the second connection end positioned at the second body other end, institute The second test end surfaces are stated to flush with the first test end surfaces.
- 3. the forming method of semiconductor test gauge as claimed in claim 2, it is characterised in that the shape of first testing needle It is into process：The first metal layer is formed on the substrate；Etch the first metal layer and form some first testing needles.
- 4. the forming method of semiconductor test gauge as claimed in claim 2, it is characterised in that the shape of first testing needle It is into process：Sacrifice layer is formed on the substrate, and there are some through holes for exposing substrate surface in the sacrifice layer；Institute State and full metal is filled in through hole, form some first testing needles；Remove the sacrifice layer.
- 5. the forming method of semiconductor test gauge as claimed in claim 1, it is characterised in that formed with letter in the substrate Number transmission circuit, the signal circuit include first input end, the first output terminal, the second input terminal and the second output terminal, First output terminal is electrically connected with the first connecting pin of the first testing needle, and the second of second output terminal and the second testing needle Connecting pin is electrically connected, and the first input end and the second input terminal are electrically connected with exterior test circuit respectively.
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| CN1886821A (en) * | 2003-11-26 | 2006-12-27 | 佛姆法克特股份有限公司 | Methods for making vertical electrical feed through structures |
| CN101713790A (en) * | 2008-09-29 | 2010-05-26 | 日本电产理德株式会社 | Inspection fixture, electrode of the fixture, method of making the electrode |
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| CN1886821A (en) * | 2003-11-26 | 2006-12-27 | 佛姆法克特股份有限公司 | Methods for making vertical electrical feed through structures |
| CN101713790A (en) * | 2008-09-29 | 2010-05-26 | 日本电产理德株式会社 | Inspection fixture, electrode of the fixture, method of making the electrode |
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