CN104280678B - Semiconductor test jig - Google Patents
Semiconductor test jig Download PDFInfo
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- CN104280678B CN104280678B CN201410606735.9A CN201410606735A CN104280678B CN 104280678 B CN104280678 B CN 104280678B CN 201410606735 A CN201410606735 A CN 201410606735A CN 104280678 B CN104280678 B CN 104280678B
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Abstract
A kind of semiconductor test jig, including：Substrate；Several several test syringe needles being separated from each other in substrate；Fixing layer in substrate, the fixing layer fill the space between adjacent test syringe needle and the partial sidewall surface of coverage test syringe needle.The fixing layer improves the mechanical strength of test syringe needle, and fixing layer can disperse the stress being subject to when testing syringe needle and tested termination contact, prevents testing needle head from deforming or being detached from from substrate surface in test.
Description
Technical field
The present invention relates to semiconductor test technical field, in particular to a kind of semiconductor test jig.
Background technique
Test processing procedure is the electrical functionality for the product that test encapsulation is completed after IC package, to guarantee IC function of dispatching from the factory
On integrality, and to the product tested according to its electrical functionality work classify, as the Appreciation gist of IC different brackets product, most
Make appearance test operation afterwards and to product.
Electrical functionality test is being tested for the various electrical parameters of product to determine product energy normal operation.
Test of two-point contact such as Kelvin's test etc. on traditional same tested terminal mostly uses Double ejection pin or double golden hands
The mode for referring to parallel side-by-side distribution, is primarily present following deficiency：
1, the accuracy of manufacture is lower：With the continuous diminution of semiconductor product size, it is tested the size and difference quilt of terminal
The spacing surveyed between terminal is also constantly reducing, in order to comply with this trend, Conventional parallel and the Double ejection pin of column distribution or double golden hands
Bottleneck becomes increasingly conspicuous on referring to test mode its close spacing the problem of, and required precision is higher and higher, some even cannot achieve
?.
2, structural strength is weaker：In order to which two-point contact test, thimble or gold are realized in limited space on tested terminal
Finger is accordingly increasingly thinner, and Mechanical Structure Strength is also more and more weaker.
3, service life is shorter：The test contact head of traditional thimble or golden finger is easier to frayed, especially mentions in precision
When requirements at the higher level, mechanical strength are relatively low out, the degree of wear is bigger, thereby reduces the service life of test fixture.
4, measuring accuracy is lower：To comply with the light and short growth requirement of semiconductor, increasingly thinner thimble or golden finger
Generated resistance value constantly increases, while when carrying out high-current test, can generate biggish pressure drop and influence test number
Judgement；On the other hand, the Double ejection pin of parallel side-by-side distribution or the also easy of double golden fingers produce because of offset deviation between the two
The deviation of raw test number；In addition, tradition and the Double ejection pin of column distribution used for the distance that reduces between two needles two back to
The way of contact on inclined-plane, contact head be easy because in its overall structure the torsion of telescopic spring due to rotate out of tested terminal so that influence
Measuring accuracy.
Summary of the invention
Problems solved by the invention is how to improve the precision and stability of existing electrical performance testing.
To solve the above problems, the present invention provides a kind of semiconductor test jig, including：Substrate；It is several in substrate
Several test syringe needles being separated from each other；Fixing layer in substrate, the fixing layer fill the sky between adjacent test syringe needle
Between and coverage test syringe needle partial sidewall surface.
Optionally, the test syringe needle is single metal needle.
Optionally, the test syringe needle is coaxial test syringe needle, and the coaxial test syringe needle includes the first testing needle, described
First testing needle includes the first noumenon, the first test lead positioned at the first noumenon one end and positioned at the first noumenon other end
One connecting pin；Cover the insulating layer on the first noumenon surface of first testing needle；Positioned at surface of insulating layer around described first
Second testing needle of testing needle, the second testing needle and the first test coaxial needle, the second testing needle include the second ontology, are located at second
Second test lead of ontology one end and second connection end positioned at the second ontology other end, the second test end surfaces and the
One test end surfaces flush.
Optionally, the diameter of first testing needle is 500 nanometers~500 microns, the width of insulating layer is 80 nanometers~
400 microns, the width of the second testing needle is 60 nanometers~300 microns.
Optionally, the material of the insulating layer is silica, silicon nitride, silicon oxynitride, fire sand, fire sand or tree
Rouge.
Optionally, signal circuit is formed in the substrate, the signal circuit includes first input end,
One output end, the second input terminal and second output terminal, first output end are electrically connected with the first connecting pin of the first testing needle,
The second output terminal is electrically connected with the second connection end of the second testing needle, the first input end and the second input terminal respectively with
External test circuit electrical connection.
Optionally, top surface of the surface of the fixing layer lower than the test syringe needle.
Optionally, the fixing layer with a thickness of the 1/4~2/3 of testing needle height.
Optionally, the material of the fixing layer is silica, silicon nitride, silicon oxynitride, fire sand, fire sand or tree
Rouge.
Compared with prior art, technical solution of the present invention has the following advantages that：
Semiconductor test jig provided by the invention, including：Substrate；Several several tests being separated from each other in substrate
Syringe needle；Fixing layer in substrate, the fixing layer fill the space between adjacent test syringe needle and coverage test syringe needle
Partial sidewall surface.The fixing layer improves the mechanical strength of test syringe needle, and fixing layer can disperse to test syringe needle and be tested
The stress being subject to when termination contact is tried, prevents testing needle head from deforming or being detached from from substrate surface in test.
Further, the test syringe needle is coaxial test syringe needle, and the first testing needle and the second testing needle are integrated in a survey
On test point head, the second testing needle uses insulator separation around first testing needle between the second testing needle and the first testing needle,
Thus it is lesser simultaneously in the size for guaranteeing testing needle, promote the mechanical strength of testing needle；On the other hand, the first testing needle and
Two testing needles are coaxially to be distributed, so that the precision of spacing is higher between the first testing needle and the second testing needle, improve test
Precision；In another aspect, multiple testing needles (such as Double ejection pin or golden finger) is needed just to can be carried out electrical property compared with the prior art
It can test, a test syringe needle of the invention can carry out the test of electric property.
Detailed description of the invention
FIG. 1 to FIG. 4 is the structural schematic diagram of one embodiment of the invention semiconductor test jig；
Fig. 5~Figure 10 is the structural schematic diagram of one embodiment of the invention semiconductor test jig forming process；
Figure 11~Figure 14 is the structural schematic diagram of another embodiment of the present invention semiconductor test jig forming process；
Figure 15 is the structural schematic diagram of another embodiment of the present invention semiconductor test jig；
The structural schematic diagram of Figure 16~Figure 17 further embodiment of this invention semiconductor test jig forming process；
The structural schematic diagram of Figure 18~Figure 20 yet another embodiment of the invention semiconductor test jig forming process.
Specific embodiment
As described in the background art, the performance of existing thimble or golden finger is still to be improved.
For this purpose, the present invention provides a kind of semiconductor test jigs, including：Substrate；It is several in substrate to be separated from each other
Several test syringe needles；Fixing layer in substrate, the fixing layer fill the space between adjacent test syringe needle and covering
Test second test lead of partial sidewall surface the second ontology one end of syringe needle.The fixing layer is used to improve the machine of test syringe needle
Tool intensity, fixing layer can disperse the stress being subject to when testing syringe needle and tested termination contact, prevent testing needle in test
Head deforms or is detached from from substrate surface.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.When describing the embodiments of the present invention, for purposes of illustration only, schematic diagram can disobey general proportion
Make partial enlargement, and the schematic diagram is example, should not limit the scope of the invention herein.In addition, in reality
It should include the three-dimensional space of length, width and depth in production.
FIG. 1 to FIG. 4 is the structural schematic diagram of one embodiment of the invention semiconductor test jig；Fig. 5~Figure 10 is the present invention
The structural schematic diagram of one embodiment semiconductor test jig forming process；Figure 11~Figure 14 is another embodiment of the present invention semiconductor
The structural schematic diagram of test fixture forming process；Figure 15 is the structural representation of another embodiment of the present invention semiconductor test jig
Figure；The structural schematic diagram of Figure 16~Figure 17 further embodiment of this invention semiconductor test jig forming process；Figure 18~Figure 20 sheet
The structural schematic diagram of invention another embodiment semiconductor test jig forming process.
Referring to FIG. 1, one embodiment of the invention provides a kind of semiconductor test jig, including：
Substrate 200；
Several test syringe needles 20 being separated from each other in substrate 200；
Fixing layer 210 in substrate 200, the fixing layer 210 are filled the space between adjacent test syringe needle and are covered
The partial sidewall surface of lid test syringe needle 20.
In the present embodiment, the test syringe needle 20 is coaxial test syringe needle, referring to FIG. 2, Fig. 2 is a test in Fig. 1
The enlarged structure schematic diagram of syringe needle, the test syringe needle 20 include：
First testing needle 201, first testing needle 201 include the first noumenon, the first survey positioned at the first noumenon one end
Try end 21 and the first connecting pin 22 positioned at the first noumenon other end；
Cover the insulating layer 202 on the first noumenon surface of first testing needle 201；
Positioned at 202 surface loop of insulating layer around the second testing needle 203 of first testing needle 201, the second testing needle 203 with
First testing needle 201 is coaxial, the second testing needle 203 include the second ontology, positioned at second ontology one end the second test lead 23 with
And the second connection end 24 positioned at the second ontology other end, 23 surface of the second test lead and 31 surface of the first test lead are neat
It is flat.
Incorporated by reference to referring to figs. 2 and 3, Fig. 3 is the schematic diagram of the section structure of the Fig. 2 along the direction hatching AB, and described first surveys
The shape of test point 201 is cylindrical body, and the section shape of corresponding first testing needle 201 is circle, the section of the insulating layer 202
Shape is circular ring shape, and the section shape of second testing needle 203 is circular ring shape.It should be noted that first testing needle
Section shape can be other shapes, for example the section shape of first testing needle can be regular polygon, such as just
Triangle, square.
Test syringe needle of the invention is formed by semiconductor integration making technology, thus the first testing needle 201 formed
Diameter can be smaller, and in one embodiment, the diameter of first testing needle 201 is 100 nanometers~500 microns, can be 200
Nanometer~50 microns.
The width of the corresponding insulating layer 202 and the width of the second testing needle 203 can also be with very littles, in an embodiment
In, it can be 100 nanometers~10 microns that the width of the insulating layer 202, which is 80 nanometers~400 microns, second testing needle
203 width is 60 nanometers~300 microns, can be 90 nanometers~25 microns.
It should be noted that in other embodiments of the invention, according to the needs of test, first testing needle 201
Diameter, the thickness of insulating layer 202 and the thickness of third testing needle 203 can be other suitable numerical value.
The material of first testing needle 201 and the second testing needle 203 be copper, gold, tungsten or alloy material or other
Suitable metal material or metal compound material.
The insulating layer 202 is for the electric isolation between the first testing needle 201 and the second testing needle 203, the present embodiment
In, the top surface (the first test lead 21) of the top surface of the insulating layer 202 and the first testing needle 201 and the second testing needle
203 top surface (the second test lead 23) flushes, i.e., so that the first test lead 21 of the first testing needle 201 and the second testing needle
There is no gap between 203 the second test lead 23, in test, prevents the first test lead 21 or the of the first testing needle 201
Second test lead 23 of two testing needles 203 thus between there are gaps to deform under external stress, and make the
The second test lead 23 electrical contact of the first test lead 21 and the second testing needle 203 of one testing needle 201, to influence the essence of test
Degree.
The insulating layer 202 can be single-layer or multi-layer (>=2 layers) stacked structure.
The material of the insulating layer 202 can be insulating dielectric materials, such as silica, silicon nitride, silicon oxynitride, nitrogen carbon
One or more of SiClx, fire sand, the material of the insulating layer can also be resin material, for example, epoxy resin, poly-
Imide resin, polyvinyl resin, benzocyclobutane olefine resin or polybenzoxazoles resin.
From the direction for being directed toward the second test lead 23 far from the second test lead 23, the part body of second testing needle 203
Width be gradually reduced.Specifically referring to FIG. 1, the width of the part body of second testing needle 203, is tested closer to second
Hold 23 its width it is smaller, when that mostly will be used to test with testing needle 20 so that it is adjacent test syringe needle 20 test lead between away from
From increase.
With continued reference to FIG. 1, also having fixing layer 210 in the substrate 200, the surface of the fixing layer 210 is lower than survey
The top surface of test point head 20, and the fixing layer 210 covers the partial sidewall surface of the test syringe needle 20, the fixing layer
210 for improving the mechanical strength of test syringe needle 20, when fixing layer 210 can disperse to test syringe needle 20 and tested termination contact
The stress being subject to prevents test syringe needle 20 from deforming or being detached from from 200 surface of substrate in test.
The material of the fixing layer 210 be silica, silicon nitride, silicon oxynitride, fire sand, fire sand or resin,
Or other suitable materials.
The thickness of the fixing layer 210 can be the 1/4~2/3 of 20 height of testing needle.
It applies by test syringe needle 20 of the invention when carrying out electrical performance testing, it in one embodiment, can be by this
The test syringe needle of invention be applied to resistance test or high-current test, by test syringe needle 20 one end and tested termination contact,
Make the first test lead 21 of the first testing needle 201 and 23 surface of the second test lead of the second testing needle 203 and tested terminal
Surface contact, and apply test voltage between the first testing needle 201 and the second testing needle 202, measurement passes through the first testing needle
201, the electric current on the second testing needle 203 and tested terminal, and test electricity is obtained divided by electric current by test voltage
Resistance.
In one embodiment, when carrying out the test of resistance using test syringe needle 20 of the invention, due to the first testing needle 201
It is coaxial with the second testing needle 203, thus tests electric current and uniformly spread around by the first testing needle 201, flows to the
Two testing needles 203, i.e., so that tested terminal between the first testing needle 201 and the second testing needle 203 annular region (with it is exhausted
The part that edge layer 202 contacts) on the electric current that flows through of different directions be it is average, improve the precision of test.
In other embodiments of the invention, test syringe needle of the invention can be applied to the electric property of other forms
Test, for example the test of electric property can be carried out using multiple test syringe needles, for example test electric current can be from a testing needle
The first testing needle or the second testing needle of head flow to the first testing needle or the second testing needle of another test syringe needle, or test
The second testing needle and the second testing needle that circuit can test syringe needle from one flow to the first testing needle of another test syringe needle
With the second testing needle.
The quantity of the test syringe needle 20 is more than or equal to two, and in a specific embodiment, the test syringe needle 20 exists
It arranges in substrate 200 in ranks.
It is formed with signal circuit in the substrate 200, the signal circuit includes first input end, first defeated
Outlet, the second input terminal and second output terminal, first output end are electrically connected with the first connecting pin of the first testing needle 201,
The second output terminal is electrically connected with the second connection end of the second testing needle 203, the first input end and the second input terminal point
It is not electrically connected with external test circuit.For the test circuit for providing test signal, the signal circuit is used for will
The test signal that test circuit generates is transmitted to the first testing needle 201 and the second testing needle 203, and will obtain in test process
Electric signal transmission is handled received electric signal to circuit, test circuit is tested, and obtains test parameter.
Material PCB resin of the substrate 200 etc., the first input end and the first output end are intrabasement by being located at
The electrical connection of first metal wire, second input terminal and second output terminal are electrically connected by being located at intrabasement second metal wire.
In one embodiment, the substrate 200 includes front and the back side opposite with front, and the back side of the substrate includes
Interface area, several first output ends and second output terminal are located at the front of substrate 200, with the first testing needle and the second testing needle
Position it is corresponding, several first input ends and the second input terminal can concentrate on the interface area at 200 back side of substrate, so that several
First input end and the second input terminal can be connected by one or more interfaces with external test circuit, simplify semiconductor
Interface circuit between test fixture and the test circuit of outside.In a specific embodiment, the substrate 200 can pass through
Multi-layer PCB resin substrate presses to be formed, and each layer of PCB resin substrate includes several interconnection structures, and each interconnection structure includes
It is connected through the through-hole interconnection structure of the PCB resin substrate and on PCB resin substrate surface with through-hole interconnection structure
Metal layer, when multi-layer PCB resin substrate presses, multiple interconnection structures are electrically connected to form the first metal wire or the second metal wire, because
And several first input ends and the second input terminal is allowed to concentrate on the interface area at 200 back side of substrate.
In another embodiment, the substrate 200 includes front and the back side opposite with front, the back side packet of the substrate
Include interface area, several first output ends and second output terminal are located at the front of substrate 200, several first input ends and second defeated
Enter the back side that end is located at substrate 200, the first through hole interconnection structure through substrate 200 and the can be formed in the substrate 200
Two through-hole interconnection structures, the first input end and the first output end pass through the first through hole interconnection structure in substrate 200
Electrical connection, second input terminal and second output terminal are electrically connected by the second through-hole interconnection structure being located in substrate 200；Institute
Stating on the back side of substrate 200 also has the several first interconnection metal layer and the second interconnection metal layers again again, and described first is routed again
One end of metal layer is electrically connected with first input end, and the other end of the first interconnection metal layer again is located in interface area, and described
Two again one end of interconnection metal layer be electrically connected with the second input terminal, the other end of the described second interconnection metal layer again is located at interface area
In domain, in interface area first again interconnection metal layer and second again interconnection metal layer pass through one or more interfaces and external
Circuit is tested to be connected.
In other embodiments, test circuit (not shown), the test electricity be could be formed in the substrate 200
Road includes the first signal end and second signal end, and the first signal end is electrically connected with the first connecting pin of the first testing needle 201, and second
Signal end is electrically connected with the second connection end of the second testing needle 203.The test circuit when testing, to the first testing needle
201 and second testing needle 203 apply test signal (such as voltage signal or current signal), and to the electric signal of acquisition (such as
Current signal etc.) carry out processing acquisition test parameter (such as resistance etc.).
With reference to Fig. 4, Fig. 4 is structural schematic diagram when semiconductor test jig of the invention is used for electrical performance testing, first
First semiconductor test jig is placed in tester table；Then encapsulating structure 300 to be tested is placed on semiconductor test jig,
There are several tested terminals 31, the tested terminal 31 can be encapsulation to be tested on the encapsulating structure to be tested 300
The pad or pin of structure 300, the test lead (test of the part of the surface of the tested terminal 31 and corresponding test syringe needle 20
End is the first test lead of the first testing needle 201 and the second test lead of the second testing needle 203) electrical connection；Then it is surveyed first
Apply test signal between test point 201 and the second testing needle 203, carries out the test of electric property.
Semiconductor test jig through the invention can multiple tested terminals to encapsulating structure 300 carry out electricity simultaneously
Performance test is learned, the efficiency of test and the accuracy of test are improved.
It (is manually loaded to be tested it should be noted that semiconductor test jig of the invention can be applied to manual test
Encapsulating structure) it also can be applied to test (mechanical hand loads encapsulating structure to be tested automatically) automatically.
The embodiment of the invention also provides it is a kind of formed aforesaid semiconductor test fixture method, specifically please refer to Fig. 5~
Figure 10.
Referring to FIG. 5, providing substrate 200；Several first testing needles 201 are formed in the substrate 200.
First testing needle 201 is cylindrical body, and the first testing needle 201 is obtained along the direction for being parallel to 200 surface of substrate
Section shape be circle, the diameter of first testing needle 201 is 500 nanometers~500 microns, is formed in the substrate 200
The first testing needle 201 quantity be more than or equal to 2, in the present embodiment, to form 3 the first testing needles 201 on a substrate 200
As example.
It should be noted that the section shape of first testing needle can be other shapes, for example described first surveys
The shape of test point is regular polygon, such as equilateral triangle, square.
In one embodiment, the forming process of first testing needle 201 is：The first gold medal is formed in the substrate 200
Belong to layer (not shown)；Patterned mask layer is formed on the first metal layer；Using the patterned mask layer as exposure mask,
It etches the first metal layer and forms several first testing needles 201；Remove the patterned mask layer.
In another embodiment, the forming process of first testing needle 201 is：It is formed and is sacrificed in the substrate 200
Layer (not shown), has several through-holes for exposing 200 surface of substrate in the sacrificial layer；Filling is full in the through hole
The first metal layer forms several first testing needles；Remove the sacrificial layer.
In the through hole fill the first metal layer technique be electroplating technology, in through-holes fill the first metal layer it
Before, further include：Conductive layer is formed in the side wall of the through-hole and bottom and the surface of sacrificial layer, the conductive layer is as plating
Cathode when technique.
The material of the conductive layer is one or more of Ti, Ta, TiN, TaN etc., and conductive layer can be single layer or more
Layer (>=2 layers) stacked structure.
In one embodiment, the conductive layer can be double stacked structure, the conductive layer packet of the double stacked structure
Include Ti layers and the TiN layer on Ti layer, or the TaN layer being located on Ta layer including Ta layers.
The thickness of the conductive layer be less than through-hole radius, in one embodiment, the conductive layer with a thickness of 50~200
Nanometer, the formation process of conductive layer are sputtering.
After forming conductive layer, electroplating technology is carried out, forms the first metal layer layer, the first metal layer is located at conductive layer
Through-hole is gone up and filled, after carrying out electroplating technology, further includes：Chemical mechanical milling tech is carried out, the of sacrificial layer surface is removed
One metal layer and conductive layer, form the first testing needle 201, and the first testing needle 201 includes the first metal layer and encirclement described first
The non-proliferation barrier layer of metal layer, the non-proliferation barrier layer is made of conductive layer remaining after chemical mechanical grinding, for preventing
Only the metal in metal layer is spread into the insulating layer being subsequently formed.
The material of the first metal layer is copper, gold, tungsten or alloy material or other suitable metal materials.
The surface (bottom surface) that first testing needle 201 is contacted with 200 surface of substrate is the first connecting pin, and first surveys
The surface (top surface) opposite with the first connecting pin of test point 201 is the first test lead.
It is formed with signal circuit in the substrate 200, the signal circuit includes first input end, first defeated
Outlet, the second input terminal and second output terminal, first output end are electrically connected with the first connecting pin of the first testing needle 201,
The second output terminal is electrically connected with the second connection end of the second testing needle 203, the first input end and the second input terminal point
It is not electrically connected with external test circuit.For the test circuit for providing test signal, the signal circuit is used for will
The test signal that test circuit generates is transmitted to the first testing needle 201 and the second testing needle 203, and will obtain in test process
Electric signal transmission is handled received electric signal to circuit, test circuit is tested, and obtains test parameter.
Material PCB resin of the substrate 200 etc., the first input end and the first output end are intrabasement by being located at
The electrical connection of first metal wire, second input terminal and second output terminal are electrically connected by being located at intrabasement second metal wire.
In one embodiment, the substrate 200 includes front and the back side opposite with front, and the back side of the substrate includes
Interface area, several first output ends and second output terminal are located at the front of substrate 200, with the first testing needle and the second testing needle
Position it is corresponding, several first input ends and the second input terminal can concentrate on the interface area at 200 back side of substrate, so that several
First input end and the second input terminal can be connected by one or more interfaces with external test circuit, simplify semiconductor
Interface circuit between test fixture and the test circuit of outside.In a specific embodiment, the substrate 200 can pass through
Multi-layer PCB resin substrate presses to be formed, and each layer of PCB resin substrate includes several interconnection structures, and each interconnection structure includes
It is connected through the through-hole interconnection structure of the PCB resin substrate and on PCB resin substrate surface with through-hole interconnection structure
Metal layer, when multi-layer PCB resin substrate presses, multiple interconnection structures are electrically connected to form the first metal wire or the second metal wire, because
And several first input ends and the second input terminal is allowed to concentrate on the interface area at 200 back side of substrate.
In another embodiment, the substrate 200 includes front and the back side opposite with front, the back side packet of the substrate
Include interface area, several first output ends and second output terminal are located at the front of substrate 200, several first input ends and second defeated
Enter the back side that end is located at substrate 200, the first through hole interconnection structure through substrate 200 and the can be formed in the substrate 200
Two through-hole interconnection structures, the first input end and the first output end pass through the first through hole interconnection structure in substrate 200
Electrical connection, second input terminal and second output terminal are electrically connected by the second through-hole interconnection structure being located in substrate 200；Institute
Stating on the back side of substrate 200 also has the several first interconnection metal layer and the second interconnection metal layers again again, and described first is routed again
One end of metal layer is electrically connected with first input end, and the other end of the first interconnection metal layer again is located in interface area, and described
Two again one end of interconnection metal layer be electrically connected with the second input terminal, the other end of the described second interconnection metal layer again is located at interface area
In domain, in interface area first again interconnection metal layer and second again interconnection metal layer pass through one or more interfaces and external
Circuit is tested to be connected.
In other embodiments, test circuit (not shown), the test electricity be could be formed in the substrate 200
Road includes the first signal end and second signal end, and the first signal end is electrically connected with the first connecting pin of the first testing needle 201, and second
Signal end is electrically connected with the second connection end of the second testing needle 203.The test circuit when testing, to the first testing needle
201 and second testing needle 203 apply test signal (such as voltage signal or current signal), and to the electric signal of acquisition (such as
Current signal etc.) carry out processing acquisition test parameter (such as resistance etc.).In one embodiment, the substrate 200 includes
Semiconductor substrate (such as silicon substrate or substrate etc.) and the dielectric layer in semiconductor substrate are formed in the semiconductor substrate
Have semiconductor devices (such as transistor etc.), forms metal interconnecting wires and passive device (such as resistance, capacitor in the dielectric layer
Deng), semiconductor devices and passive device are connected and composed test circuit, the first signal end and second signal by the metal interconnecting wires
End can be drawn by being located at the first metal wire and the second metal wire that are electrically connected in dielectric layer with test circuit.
In conjunction with reference Fig. 6 and Fig. 7, insulating layer 202 is formed on the side wall of each first testing needle 201.
The forming process of the insulating layer 202 is：It is formed and covers the exhausted of each first testing needle, 201 side wall and top surface
Edge film layer 204；No mask etching technique etches the insulating thin layer 204 and forms insulation in the side wall of the first testing needle 201
Layer 202.
The insulating layer 202 with a thickness of 80 nanometers~400 microns, the material of the insulating layer 202 can be situated between for insulation
One or more of material, such as silica, silicon nitride, silicon oxynitride, fire sand, fire sand.
The insulating layer 202 can be single-layer or multi-layer (>=2 layers) stacked structure.
The no mask etching technique is anisotropic plasma etching industrial, in one embodiment, the plasma
The etching gas that etching technics uses is specifically as follows CF for fluorine-containing and carbon gas4、C2F6、C4F8、CHF3、CH2F2In one
Kind is several, and source power is 500~1000W, and bias power is 0~100W, and etching cavity pressure is 2~500mtorr.
In the present embodiment, the insulating layer 202 is the silicon oxide layer of single layer,
In other embodiments of the invention, the material of the insulating layer 202 can also be resin material, the resinous wood
Material can be epoxy resin, polyimide resin, polyvinyl resin, benzocyclobutane olefine resin or polybenzoxazoles resin.
The formation process of the insulating layer 202 is screen printing technique etc..
In conjunction with reference Fig. 8 and Fig. 9, the second testing needle 203, second testing needle 203 are formed on the surface of insulating layer 202
Around corresponding first testing needle 201.
The forming process of second testing needle 203 is：It is formed and covers the insulating layer 202 and the first testing needle 201 top
The second metal layer 205 on portion surface；Without second metal layer 205 described in mask etching, the second test is formed on 202 surface of insulating layer
Needle 203.
The formation process of the second metal layer 205 is sputtering, and 205 material of second metal layer is copper, gold, tungsten or alloy
Material or other suitable metal materials, second metal layer 205 with a thickness of 60 nanometers~300 microns.
The technique of second metal layer 205 described in no mask etching is anisotropic plasma etching industrial, is implemented one
In example, the etching gas that the plasma etching industrial uses is SF6、NF3、Cl2, one or more of HBr, source power is
500~1500W, bias power are 0~100W, and etching cavity pressure is 10~500mtorr.
Each first testing needle 201 constitutes a test syringe needle 20 with corresponding insulating layer 202 and the second testing needle 203.
Referring to FIG. 10, forming fixing layer 210 in the substrate 200, the fixing layer 210 fills adjacent test syringe needle
The partial sidewall surface in space and coverage test syringe needle 20 between 20.
The forming process of the fixing layer 210 is：Form the fixation material for covering the substrate 200 and test 20 surface of syringe needle
The bed of material；It is etched back to the fixed material layer, forms fixing layer 210.
It further include step before being etched back to fixed material layer：Flatening process is carried out to the fixed material layer, such as
Chemical mechanical milling tech exposes the top surface of test syringe needle 20；Then the fixation material layer after being etched back to planarization, shape
At fixing layer 210.
It in one embodiment, can be in the top table of the test syringe needle 20 before being etched back to the fixed material layer
Mask layer is formed on face, the mask layer prevents syringe needle by the damage etched when being etched back to fixed material layer, solid being formed
After given layer 210, the mask layer is removed.
In another embodiment, before etching fixed material layer, if when not forming mask layer on testing syringe needle 20,
Then the material of the fixing layer 210 is not identical as the material of insulating layer 202, and when so that etching fixed material layer, insulating layer 202 is not
It can be etched or etch rate is very low, guarantee the integrality of insulating layer 202.
The material of the fixing layer 210 be silica, silicon nitride, silicon oxynitride, fire sand, fire sand or resin,
Or other suitable materials.
The thickness of the fixing layer 210 can be the 1/4~2/3 of 20 height of testing needle.
Another embodiment of the present invention additionally provides a kind of method for forming semiconductor test jig above-mentioned, specifically please refers to
Figure 11~Figure 14.
Figure 11 is please referred to, substrate 200 is provided；Dielectric layer 207 is formed in the substrate 200, is stated and is formed in dielectric layer 207
There are several first through hole 208 and the annular through-hole 209 around each first through hole 208, first through hole 208 and annular through-hole 209
Between be isolated by certain media layer.
The first through hole 208 and annular through-hole 209 expose the surface of substrate 200, subsequent in the first through hole 208
It fills metal and forms the first testing needle, subsequent filling metal forms the second testing needle in second through-hole.
Signal circuit or test circuit are formed in the substrate 200, about signal circuit or test circuit
Description please refers to previous embodiment, and details are not described herein.
It is the overlooking structure diagram of part-structure in Figure 11 with reference to Figure 12, Figure 12, the first through hole 208 is circle,
Annular through-hole 209 is circular ring shape, annular through-hole 209 around the first through hole 208, first through hole 208 and annular through-hole 209 it
Between be isolated by certain media layer material.
In other embodiments of the invention, the shape of the first through hole can be other shapes, for example can be
Regular polygon is specifically as follows equilateral triangle, square etc..
In one embodiment, the material of the dielectric layer 207 is insulating dielectric materials, such as silica, silicon nitride, nitrogen oxygen
One or more of SiClx, fire sand, fire sand form medium by chemical gaseous phase deposition technique on a substrate 200
Layer 207, then forms patterned photoresist layer on the dielectric layer 207, using the patterned photoresist layer as exposure mask,
The dielectric layer 207 is etched, forms several first through hole 208 and the annular around each first through hole 208 in dielectric layer 207
Through-hole 209；After forming the annular through-hole 209 of first through hole 208, the patterned photoresist layer is removed.
In another embodiment, the material of the dielectric layer 207 is resin glue, and the resin glue is epoxide-resin glue, gathers
Imide resin glue, polyvinyl adhesive, benzocyclobutene resin glue or polybenzoxazoles resin glue, by dry film process, wet
Membrane process, printing technology or plastic roll technique form dielectric layer 207 in the substrate 200；Then pass through exposure and imaging technique
Several first through hole 208 and the annular through-hole 209 around each first through hole 208 are formed in the dielectric layer.
With reference to Figure 13, filling metal forms the first testing needle 201 in first through hole 208 (referring to Figure 11), logical in annular
Filling metal forms the second testing needle 203 in hole 209 (referring to Figure 11).
First testing needle 201 and the second testing needle 203 are formed by same processing step.
The technique that metal is filled in first through hole 208 and annular through-hole 209 is electroplating technology, in 208 He of first through hole
Before filling metal in annular through-hole 209, further include：The first through hole 208 and annular through-hole 209 side wall and bottom with
And the surface of sacrificial layer forms conductive layer, the cathode when conductive layer is as electroplating technology.
The material of the conductive layer is one or more of Ti, Ta, TiN, TaN etc., and conductive layer can be single layer or more
Layer (>=2 layers) stacked structure.
In one embodiment, the conductive layer can be double stacked structure, the conductive layer packet of the double stacked structure
Include Ti layers and the TiN layer on Ti layer, or the TaN layer being located on Ta layer including Ta layers.
The thickness of the conductive layer is less than smaller in both the radius of first through hole 208 and the radius of annular through-hole 209
Radius value, the formation process of conductive layer is sputtering.
After forming conductive layer, electroplating technology is carried out, forms metal layer, the metal layer is located on conductive layer and fills the
One through-hole 208 and annular through-hole 209 further include after carrying out electroplating technology：Chemical mechanical milling tech is carried out, medium is removed
The metal layer and conductive layer on 207 surface of layer, form the first testing needle 201 and the second testing needle 203, the first testing needle 201 and the
Two testing needles 203 include metal layer and the non-proliferation barrier layer for surrounding the metal layer, and the non-proliferation barrier layer is chemistry
Remaining conductive layer is constituted after mechanical lapping, for preventing the metal in metal layer from spreading into the insulating layer being subsequently formed.
The material of the metal layer is copper, gold, tungsten or alloy material or other suitable metal materials.
The first testing needle 201 and the second testing needle 203, the first testing needle are formed simultaneously by electroplating technology in the present embodiment
201 and second testing needle 203 not will receive the damage of etching so that the surface shape of the first testing needle 201 and the second testing needle 203
Looks are preferable.
With reference to Figure 14, the segment thickness dielectric layer 207 (referring to Figure 13) in 203 outside of the second testing needle, the first test are removed
Remaining dielectric layer is remained in the substrate 200 between needle adjacent 20 as insulating layer 202 between needle 201 and the second testing needle 203
Remaining dielectric layer is covered and is surveyed lower than the surface for testing syringe needle 20 as fixing layer 210, the top surface of the fixing layer 210
The partial sidewall of test point head.
Before the certain media layer 207 for removing 203 outside of the second testing needle, in first testing needle 201 and second
Photoresist mask layer is formed on dielectric layer between testing needle 203 and the first testing needle 201 and the second testing needle 203；Then
Using the photoresist as exposure mask, the dielectric layer 207 of the segment thickness in 203 outside of the second testing needle of etching removal, remaining medium
Layer is used as fixing layer 210.
Institute's fixing layer 210 with a thickness of test 20 height of syringe needle 1/4~2/3.
207 technique of dielectric layer in 203 outside of the second testing needle of etching removal can be wet etching or dry etch process.
In a specific embodiment, when the material of the dielectric layer 207 is silica, the quarter of wet-etching technology use
Erosion solution is hydrofluoric acid solution, and the etching gas that dry etching uses is fluorocarbon gas；The material of the dielectric layer 207
When for silicon nitride, the etching solution that wet-etching technology uses is phosphoric acid solution, and the etching gas that dry etching uses is carbon fluorine
Hydrogen compound gas；When the material of the dielectric layer 207 is resin glue, the etching solution that wet-etching technology uses is molten for sulfuric acid
Liquid, the etching gas that dry etching uses is oxygen.
A kind of semiconductor test jig is additionally provided in another embodiment of the present invention, please refers to Figure 15, including：
Substrate 100；
Several several test syringe needles 101 being separated from each other in substrate 100；
Fixing layer 102 in substrate 100, the fixing layer 102 fill it is adjacent test syringe needle 101 between space and
The partial sidewall surface of coverage test syringe needle 101.
In the present embodiment, the test syringe needle 101 is single metal needle.
In the present embodiment, the test syringe needle 101 is circle along the section shape for being parallel to the acquisition of 100 surface direction of substrate
The diameter of shape, the test syringe needle is 100 nanometers~300 microns.
In other embodiments of the invention, the edge of the test syringe needle 101 is parallel to the acquisition of 100 surface direction of substrate
Section shape can be other shapes, for example the section shape of the test syringe needle 101 can be regular polygon, such as positive three
It is angular, square.
The material of the test syringe needle 101 be copper, gold, tungsten or alloy material or other suitable metal materials or
Person's metal compound material.
The quantity for testing syringe needle 101 is more than or equal to 2.
Also there is fixing layer 102, the surface of the fixing layer 102 is lower than the top for testing syringe needle 101 in the substrate 100
Surface, and the fixing layer 102 covers the partial sidewall surface of the test syringe needle 101, the fixing layer 102 is surveyed for improving
The mechanical strength of test point head 101, fixing layer 102 can disperse the stress being subject to when testing syringe needle 101 and tested termination contact,
Prevent test syringe needle 101 from deforming or being detached from from 100 surface of substrate in test.
The material of the fixing layer 102 be silica, silicon nitride, silicon oxynitride, fire sand, fire sand or resin,
Or other suitable materials.
The thickness of the fixing layer 102 can be the 1/4~2/3 of 101 height of testing needle.
Signal circuit is formed in the substrate 100, the signal circuit includes several input terminals and output
End, the output end are electrically connected with the bottom surface of test syringe needle 101, and the input terminal is electrically connected with external test circuit.
The test circuit is used to test the test signal transmission of circuit generation for providing test signal, the signal circuit
To test syringe needle 101, and by the electric signal transmission obtained in test process to circuit is tested, circuit is tested to received electric signal
It is handled, obtains test parameter.
Material PCB resin of the substrate 100 etc., the input terminal and output end are by being located at intrabasement metal wire electricity
Connection.
In one embodiment, the substrate 100 includes front and the back side opposite with front, and the back side of the substrate includes
Interface area, several output ends are located at the front of substrate 100, corresponding with the test position of 101 bottom surface of syringe needle, several described
Input terminal concentrates on the interface area at 100 back side of substrate, and several input terminals is allowed to pass through one or more interfaces and outside
Test circuit be connected, simplify semiconductor test jig and outside test circuit between interface circuit.It is specific one
In embodiment, the substrate 100 can press to be formed by multi-layer PCB resin substrate, if each layer of PCB resin substrate includes
Dry interconnection structure, each interconnection structure include through the through-hole interconnection structure of the PCB resin substrate and positioned at PCB resin substrate
The metal layer being connected on surface with through-hole interconnection structure, when multi-layer PCB resin substrate presses, multiple interconnection structures are electrically connected to form
Metal wire, thus category line can be bent arrangement, so that several output ends concentrate on the interface area at 100 back side of substrate.
In another embodiment, the substrate 100 includes front and the back side opposite with front, the back side packet of the substrate
Include interface area, several first output ends and second output terminal are located at the front of substrate 100, several first input ends and second defeated
Enter the back side that end is located at substrate 100, the first through hole interconnection structure through substrate 200 and the can be formed in the substrate 100
Two through-hole interconnection structures, the first input end and the first output end pass through the first through hole interconnection structure in substrate 100
Electrical connection, second input terminal and second output terminal are electrically connected by the second through-hole interconnection structure being located in substrate 100；Institute
Stating on the back side of substrate 100 also has the several first interconnection metal layer and the second interconnection metal layers again again, and described first is routed again
One end of metal layer is electrically connected with first input end, and the other end of the first interconnection metal layer again is located in interface area, and described
Two again one end of interconnection metal layer be electrically connected with the second input terminal, the other end of the described second interconnection metal layer again is located at interface area
In domain, in interface area first again interconnection metal layer and second again interconnection metal layer pass through one or more interfaces and external
Circuit is tested to be connected.
In other embodiments, test circuit (not shown), the test electricity be could be formed in the substrate 100
Road includes signal end, and signal end is electrically connected with the bottom surface of test syringe needle 101.The test circuit when testing, leads to
It crosses signal end and test signal (such as voltage signal or current signal) is applied to test syringe needle 101, during the test, obtain electricity
Signal (such as current signal etc.), and processing is carried out to the electric signal of acquisition and obtains test parameter (such as resistance etc.).
Further embodiment of this invention additionally provides a kind of method for forming above-mentioned semiconductor test jig, specifically please refers to figure
16~Figure 17.
Figure 16 is please referred to, substrate 100 is provided；Several test syringe needles 101 are formed in the substrate 100.
It is described test syringe needle 101 forming process be：Metal layer (not shown) is formed in the substrate 100；?
Patterned mask layer is formed on metal layer；Using the patterned mask layer as exposure mask, the metal layer is etched, in the base
Several test syringe needles are formed on bottom.
Signal circuit or test circuit are formed in the substrate 100.About signal circuit or test circuit
Description, please refer to previous embodiment, details are not described herein.
The material of the metal layer is copper, gold, tungsten or alloy material or other suitable metal materials or metal
Compound-material etches the metal layer using anisotropic dry etch process.
Figure 17 is please referred to, the dielectric layer for covering the substrate 100 and test syringe needle 101 is formed, it is thick to be etched back to removal part
The dielectric layer of degree, remaining dielectric layer is as fixing layer 102 in substrate.
The material of the dielectric layer be silica, silicon nitride, silicon oxynitride, fire sand, fire sand or resin or
Other suitable materials.
The technique for being etched back to the dielectric layer of removal segment thickness can be for wet-etching technology or dry etch process, specifically
Etching technics please refer to previous embodiment relevant portion introduction, details are not described herein.
Further embodiment of this invention additionally provides a kind of method for forming above-mentioned semiconductor test jig, specifically please refers to figure
18~Figure 20.
Figure 18 is please referred to, substrate 100 is provided；Dielectric layer 104 is formed in the substrate 100, is had in the dielectric layer 104
There are several through-holes 105 for exposing 100 surface of substrate.
It is subsequent that metal is filled in through-hole 105, form test syringe needle.
In one embodiment, the material of the dielectric layer 104 is insulating dielectric materials, such as silica, silicon nitride, nitrogen oxygen
One or more of SiClx, fire sand, fire sand form medium in substrate 100 by chemical gaseous phase deposition technique
Layer 104, then forms patterned photoresist layer on the dielectric layer 104, using the patterned photoresist layer as exposure mask,
The dielectric layer 104 is etched, forms several through-holes 105 in dielectric layer 104；After forming through-hole 105, remove described patterned
Photoresist layer.
In another embodiment, the material of the dielectric layer 104 is resin glue, and the resin glue is epoxide-resin glue, gathers
Imide resin glue, polyvinyl adhesive, benzocyclobutene resin glue or polybenzoxazoles resin glue, by dry film process, wet
Membrane process, printing technology or plastic roll technique form dielectric layer 104 in the substrate 100；Then pass through exposure and imaging technique
Several through-holes 105 are formed in the dielectric layer 104.
Signal circuit or test circuit are formed in the substrate 100.About signal circuit or test circuit
Description, please refer to previous embodiment, details are not described herein.
Figure 19 is please referred to, filling metal forms test syringe needle 101 in the through-hole 105 (referring to Figure 18).
The fill process of the metal is electroplating technology, specifically please refers to previous embodiment relevant portion introduction, herein not
It repeats again.
Figure 20 is please referred to, the dielectric layer 104 (with reference to Figure 19) of removal segment thickness, remaining Jie in substrate 100 are etched back to
Matter layer is as fixing layer 102.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (8)
1. a kind of semiconductor test jig, which is characterized in that including：
Substrate；
Several several test syringe needles being separated from each other in substrate；
Fixing layer in substrate, the fixing layer fill the space between adjacent test syringe needle and the portion of coverage test syringe needle
Divide sidewall surfaces；
Wherein, the test syringe needle and fixing layer are formed by semiconductor integration making technology, and the test syringe needle is single
Metal needle coaxially tests syringe needle, and when the test syringe needle is single metal needle, semiconductor integration making technology is formed
It tests syringe needle and fixing layer includes scheme a and b；When the test syringe needle is coaxial test syringe needle, semiconductor integration making technology
It forms test syringe needle and fixing layer includes scheme c and d；
Scheme a, is formed on the substrate metal layer；It etches the metal layer and forms several test syringe needles；It is formed and covers the substrate
With the dielectric layer of test syringe needle, it is etched back to the dielectric layer of removal segment thickness, remaining dielectric layer is as fixing layer in substrate；
Scheme b forms dielectric layer on the substrate, has several through-holes for exposing substrate surface in the dielectric layer；?
Metal is filled in the through-hole forms several test syringe needles；It is etched back to the dielectric layer of removal segment thickness, remaining Jie in substrate
Matter layer is as fixing layer；
Scheme c forms the first testing needle on the substrate；It is formed and covers the exhausted of each first testing needle side wall and top surface
Edge film layer；No mask etching technique etches the insulating thin layer and forms insulating layer in the side wall of the first testing needle；Formation is covered
Cover the second metal layer of the insulating layer and the first testing needle top surface；Without second metal layer described in mask etching, insulating
Layer surface forms the second testing needle；Form the fixation material layer for covering the substrate and test needle surface；It is etched back to described solid
Determine material layer, forms fixing layer；
Scheme d forms dielectric layer on the substrate, several first through hole is formed in the dielectric layer and around each first
The annular through-hole of through-hole is isolated between first through hole and annular through-hole by certain media layer；Metal is filled in first through hole
The first testing needle is formed, metal is filled in annular through-hole and forms the second testing needle；The part removed on the outside of the second testing needle is thick
The dielectric layer of degree, remaining dielectric layer tests the base between syringe needle as insulating layer between the first testing needle and the second testing needle
Remaining dielectric layer is as fixing layer on bottom.
2. semiconductor test jig as described in claim 1, which is characterized in that the coaxial test syringe needle includes the first test
Needle, first testing needle include the first noumenon, positioned at the first noumenon one end the first test lead and be located at the first noumenon it is another
First connecting pin of one end；Cover the insulating layer on the first noumenon surface of first testing needle；It is surround positioned at surface of insulating layer
Second testing needle of first testing needle, the second testing needle and first test coaxial needle, the second testing needle include the second ontology,
The second test lead positioned at second ontology one end and the second connection end positioned at the second ontology other end, second test lead
Surface is flushed with the first test end surfaces.
3. semiconductor test jig as claimed in claim 2, which is characterized in that the diameter of first testing needle is received for 500
Rice~500 microns, the width of insulating layer are 80 nanometers~400 microns, and the width of the second testing needle is 60 nanometers~300 microns.
4. semiconductor test jig as claimed in claim 2, which is characterized in that the material of the insulating layer is silica, nitrogen
SiClx, silicon oxynitride, fire sand or resin.
5. semiconductor test jig as claimed in claim 2, which is characterized in that be formed with signal transmission electricity in the substrate
Road, the signal circuit include first input end, the first output end, the second input terminal and second output terminal, and described first
Output end is electrically connected with the first connecting pin of the first testing needle, the second connection end electricity of the second output terminal and the second testing needle
Connection, the first input end and the second input terminal are electrically connected with external test circuit respectively.
6. semiconductor test jig as described in claim 1, which is characterized in that the surface of the fixing layer is lower than the test
The top surface of syringe needle.
7. semiconductor test jig as claimed in claim 6, which is characterized in that the fixing layer with a thickness of testing needle height
1/4~2/3.
8. semiconductor test jig as claimed in claim 6, which is characterized in that the material of the fixing layer is silica, nitrogen
SiClx, silicon oxynitride, fire sand or resin.
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| US14/927,749 US10006943B2 (en) | 2014-10-30 | 2015-10-30 | Semiconductor testing fixture and fabrication method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3286183B2 (en) * | 1996-09-30 | 2002-05-27 | アジレント・テクノロジー株式会社 | Coaxial connector floating mount device |
| CN2405224Y (en) * | 1999-11-30 | 2000-11-08 | 深圳市中兴通讯股份有限公司 | Measuring probe for coaxial radio-frequency signal |
| US6447328B1 (en) * | 2001-03-13 | 2002-09-10 | 3M Innovative Properties Company | Method and apparatus for retaining a spring probe |
| CN1936595A (en) * | 2006-09-05 | 2007-03-28 | 杭州高特电子设备有限公司 | Coaxial multi-detection-point detecting rod |
| CN101187675A (en) * | 2006-11-15 | 2008-05-28 | 杨朝雨 | Probe capable of transmitting high-frequency signal |
| KR100703044B1 (en) * | 2007-01-12 | 2007-04-09 | (주)에이펙스 | Inspection probe card and its manufacturing method |
| JP5386769B2 (en) * | 2008-09-29 | 2014-01-15 | 日本電産リード株式会社 | Inspection jig |
| JP2010133763A (en) * | 2008-12-03 | 2010-06-17 | Yokogawa Electric Corp | Coaxial probe structure |
| CN201673179U (en) * | 2010-03-10 | 2010-12-15 | 上海凯恒电子科技有限公司 | Special testing probe for AV port |
| US8564319B2 (en) * | 2010-06-17 | 2013-10-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Probe card for simultaneously testing multiple dies |
| CN102384991A (en) * | 2010-09-01 | 2012-03-21 | 陈建宏 | Coaxial probe of wafer probe card and test head using same |
| CN203606461U (en) * | 2013-10-29 | 2014-05-21 | 颖崴科技股份有限公司 | Coaxial semiconductor test equipment |
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2014
- 2014-10-30 CN CN201410606735.9A patent/CN104280678B/en active Active
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| CN104280678A (en) | 2015-01-14 |
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