CN104240644B - Light emitting diode pixel circuit and driving method thereof - Google Patents
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Abstract
Description
技术领域technical field
本发明是有关于一种像素电路,尤其是有关于一种发光二极管像素电路及其驱动方法。The present invention relates to a pixel circuit, in particular to a light emitting diode pixel circuit and a driving method thereof.
背景技术Background technique
在发光二极管像素电路之中,可以用一个发光二极管搭配四个晶体管及两个电容的组件配置方式来实现其像素电路架构,也就是采用所谓的4T2C电路架构。在此4T2C电路架构当中,其中一个晶体管用以作为驱动晶体管,且其中一个电容电性耦接于此驱动晶体管的控制端与源极端之间。当此4T2C电路架构于数据写入完毕而要使发光二极管发光时,是透过使驱动晶体管的控制端浮接(floating),并利用电性耦接于驱动晶体管的控制端与源极端之间的电容来将驱动晶体管的源极端的电压变化耦合至驱动晶体管的控制端,藉以补偿(或称消除)发光二极管本身的跨压及驱动晶体管的临界电压(Vt)对于发光亮度的影响。In the light-emitting diode pixel circuit, the pixel circuit architecture can be realized by using a light-emitting diode with four transistors and two capacitors, that is, the so-called 4T2C circuit architecture. In the 4T2C circuit structure, one of the transistors is used as a driving transistor, and one of the capacitors is electrically coupled between the control terminal and the source terminal of the driving transistor. When the 4T2C circuit structure is finished writing data and the light-emitting diode is to be made to emit light, the control terminal of the driving transistor is floated and electrically coupled between the control terminal and the source terminal of the driving transistor. The capacitor is used to couple the voltage change of the source terminal of the driving transistor to the control terminal of the driving transistor, so as to compensate (or eliminate) the influence of the cross-voltage of the light-emitting diode itself and the threshold voltage (Vt) of the driving transistor on the luminous brightness.
然而,由于每个晶体管本身即存在有寄生电容,因此在使发光二极管发光时,电性耦接于驱动晶体管的控制端与源极端之间的电容自驱动晶体管的源极端所耦合至控制端的电压,就会被上述的寄生电容分压(此可称为寄生电容效应),造成上述补偿的效果不佳。为了解决上述的问题,就必须增加电性耦接于驱动晶体管的控制端与源极端之间的电容的电容值,例如加大驱动晶体管的控制端与源极端之间的电容的电容值至Ct,可是此举却会进一步衍生出发光二极管的发光电流减少,以及使补偿速度变慢等问题。However, since each transistor has its own parasitic capacitance, when the light-emitting diode is turned on, the capacitance electrically coupled between the control terminal and the source terminal of the driving transistor is coupled to the voltage of the control terminal from the source terminal of the driving transistor. , it will be divided by the above-mentioned parasitic capacitance (this can be called the parasitic capacitance effect), resulting in poor effect of the above-mentioned compensation. In order to solve the above problems, it is necessary to increase the capacitance value of the capacitor electrically coupled between the control terminal and the source terminal of the drive transistor, for example, increase the capacitance value of the capacitor between the control terminal and the source terminal of the drive transistor to Ct , but this will further lead to problems such as the reduction of the light-emitting current of the light-emitting diode and the slowing down of the compensation speed.
发明内容Contents of the invention
本发明提供一种发光二极管像素电路,其可避免发生发光二极管的发光电流减少,以及补偿速度变慢等问题。The invention provides a light-emitting diode pixel circuit, which can avoid problems such as reduction of the light-emitting current of the light-emitting diode and slow compensation speed.
本发明另提供一种适用于上述发光二极管像素电路的驱动方法。The present invention further provides a driving method suitable for the LED pixel circuit.
本发明提出一种发光二极管像素电路,其包括第一晶体管、第二晶体管、第三晶体管、第四晶体管(用以作为驱动晶体管)、第一电容、第二电容、以及发光二极管。第一晶体管具有控制端、第一端以及第二端,且第一晶体管的控制端电性耦接于第一控制信号,而第一晶体管的第一端用以接收数据电位或是参考电位。第二晶体管具有控制端、第一端、以及第二端,且第二晶体管的控制端电性耦接于第二控制信号,而第二晶体管的第一端电性耦接于第一操作电源。第三晶体管具有控制端、第一端、以及第二端,且第三晶体管的控制端电性耦接于第三控制信号。第四晶体管具有控制端、第一端、以及第二端,且第四晶体管的第一端电性耦接于第二晶体管的第二端,第四晶体管的第二端电性耦接于第三晶体管的第二端,而第四晶体管的控制端电性耦接于第一晶体管的第二端。第一电容具有第一端及第二端,第一电容的第一端电性耦接于第四晶体管的控制端,且第一电容的第二端、第四晶体管的第二端以及第三晶体管的第二端共同电性耦接。第二电容具有第一端以及第二端,且第二电容的第一端、第一晶体管的第二端以及第一电容的第一端共同电性耦接,而第二电容的第二端电性耦接于第三晶体管的第一端。此外,第二电容的电容值大于第一电容的电容值。发光二极管具有第一端以及第二端,且发光二极管的第一端电性耦接于第四晶体管的第二端,而发光二极管的第二端电性耦接于第二操作电源。The present invention provides an LED pixel circuit, which includes a first transistor, a second transistor, a third transistor, a fourth transistor (used as a driving transistor), a first capacitor, a second capacitor, and a LED. The first transistor has a control terminal, a first terminal and a second terminal, and the control terminal of the first transistor is electrically coupled to the first control signal, and the first terminal of the first transistor is used for receiving a data potential or a reference potential. The second transistor has a control terminal, a first terminal, and a second terminal, and the control terminal of the second transistor is electrically coupled to the second control signal, and the first terminal of the second transistor is electrically coupled to the first operating power supply. . The third transistor has a control terminal, a first terminal, and a second terminal, and the control terminal of the third transistor is electrically coupled to the third control signal. The fourth transistor has a control terminal, a first terminal, and a second terminal, and the first terminal of the fourth transistor is electrically coupled to the second terminal of the second transistor, and the second terminal of the fourth transistor is electrically coupled to the first terminal. The second terminal of the three transistors, and the control terminal of the fourth transistor is electrically coupled to the second terminal of the first transistor. The first capacitor has a first terminal and a second terminal, the first terminal of the first capacitor is electrically coupled to the control terminal of the fourth transistor, and the second terminal of the first capacitor, the second terminal of the fourth transistor and the third The second ends of the transistors are electrically coupled together. The second capacitor has a first end and a second end, and the first end of the second capacitor, the second end of the first transistor, and the first end of the first capacitor are electrically coupled together, and the second end of the second capacitor Electrically coupled to the first terminal of the third transistor. In addition, the capacitance of the second capacitor is greater than the capacitance of the first capacitor. The light emitting diode has a first end and a second end, and the first end of the light emitting diode is electrically coupled to the second end of the fourth transistor, and the second end of the light emitting diode is electrically coupled to the second operating power source.
本发明又提出一种发光二极管像素电路,其除了包括有上述的第一晶体管、第二晶体管、第三晶体管、第四晶体管、第一电容、第二电容、以及发光二极管,并具有相同的电性耦接关系之外,更包括一第五晶体管。此第五晶体管具有控制端、第一端及第二端,且第五晶体管的控制端接收第四控制信号,第五晶体管的第一端电性耦接预设电位,而第五晶体管的第二端电性耦接于第三晶体管的第一端。The present invention also proposes a light-emitting diode pixel circuit, which includes the first transistor, the second transistor, the third transistor, the fourth transistor, the first capacitor, the second capacitor, and the light-emitting diode, and has the same electrical In addition to the sexual coupling relationship, it further includes a fifth transistor. The fifth transistor has a control terminal, a first terminal and a second terminal, and the control terminal of the fifth transistor receives the fourth control signal, the first terminal of the fifth transistor is electrically coupled to a preset potential, and the first terminal of the fifth transistor is electrically coupled to a preset potential. The two terminals are electrically coupled to the first terminal of the third transistor.
本发明又另提出一种发光二极管像素电路,其包括:第一晶体管、第二晶体管、第三晶体管(用以作为驱动晶体管)、发光二极管以及电容模块。第一晶体管具有控制端、第一端以及第二端,且第一晶体管的控制端电性耦接于第一控制信号,而第一晶体管的第一端用以接收数据电位或是参考电位。第二晶体管具有控制端、第一端以及第二端,且第二晶体管的控制端电性耦接于第二控制信号,而第二晶体管的第一端电性耦接于第一操作电源。第三晶体管具有控制端、第一端以及第二端,且第三晶体管的第一端电性耦接于第二晶体管的第二端,而第三晶体管的控制端电性耦接于第一晶体管的第二端。发光二极管具有第一端以及第二端,且发光二极管的第一端电性耦接于第三晶体管的第二端,而发光二极管的第二端电性耦接于第二操作电源。电容模块电性耦接于第三晶体管的控制端与第二端之间,且电容模块用以提供给第三晶体管的控制端与第二端之间一个等效电容,而电容模块在二极管像素电路处于重置期间与发光期间时所提供的等效电容的值大于二极管像素电路处于补偿期间与数据写入期间时所提供的等效电容的值。The present invention further provides a light emitting diode pixel circuit, which includes: a first transistor, a second transistor, a third transistor (used as a driving transistor), a light emitting diode and a capacitor module. The first transistor has a control terminal, a first terminal and a second terminal, and the control terminal of the first transistor is electrically coupled to the first control signal, and the first terminal of the first transistor is used for receiving a data potential or a reference potential. The second transistor has a control terminal, a first terminal and a second terminal, and the control terminal of the second transistor is electrically coupled to the second control signal, and the first terminal of the second transistor is electrically coupled to the first operating power supply. The third transistor has a control terminal, a first terminal and a second terminal, and the first terminal of the third transistor is electrically coupled to the second terminal of the second transistor, and the control terminal of the third transistor is electrically coupled to the first terminal. the second terminal of the transistor. The light emitting diode has a first end and a second end, and the first end of the light emitting diode is electrically coupled to the second end of the third transistor, and the second end of the light emitting diode is electrically coupled to the second operating power source. The capacitor module is electrically coupled between the control terminal and the second terminal of the third transistor, and the capacitor module is used to provide an equivalent capacitance between the control terminal and the second terminal of the third transistor, and the capacitor module is in the diode pixel The equivalent capacitance provided by the circuit during the reset period and the light emitting period is greater than the equivalent capacitance provided by the diode pixel circuit during the compensation period and the data writing period.
本发明再提出一种发光二极管像素电路的驱动方法,用以驱动上述的具有第一至第四晶体管的发光二极管像素电路。此驱动方法包括:于重置期间中,使第一操作电源提供第一电位,并导通第一晶体管、第二晶体管与第三晶体管,且同时提供参考电位至第一晶体管的第一端;于补偿期间中,使第一操作电源提供第二电位,此第二电位大于前述的第一电位,并导通第一晶体管与第二晶体管,且同时关闭第三晶体管,并提供参考电位至第一晶体管的第一端;于数据写入期间中,使第一操作电源提供第二电位,并导通第一晶体管与第三晶体管,以及关闭第二晶体管,其中第一晶体管与第三晶体管并不同时导通,且第一晶体管的导通时间先于第三晶体管的导通时间,并在第一晶体管导通时提供数据电位至第一晶体管的第一端;以及,于发光期间中,使第一操作电源提供第二电位,并关闭第一晶体管,以及导通第二晶体管与第三晶体管,并提供参考电位至第一晶体管的第一端。其中,重置期间先于补偿期间,补偿期间先于数据写入期间,数据写入期间先于发光期间。The present invention further proposes a driving method of an LED pixel circuit, which is used to drive the above LED pixel circuit with the first to fourth transistors. The driving method includes: during the reset period, causing the first operating power supply to provide a first potential, and turn on the first transistor, the second transistor and the third transistor, and simultaneously provide a reference potential to the first terminal of the first transistor; During the compensation period, the first operating power supply provides a second potential, the second potential is greater than the aforementioned first potential, the first transistor and the second transistor are turned on, and the third transistor is turned off at the same time, and a reference potential is provided to the first transistor. The first end of a transistor; during the data writing period, the first operating power supply provides the second potential, and turns on the first transistor and the third transistor, and turns off the second transistor, wherein the first transistor and the third transistor are parallel Not conducting at the same time, and the conduction time of the first transistor is earlier than the conduction time of the third transistor, and providing a data potential to the first terminal of the first transistor when the first transistor is turned on; and, during the light-emitting period, The first operating power supply provides the second potential, turns off the first transistor, turns on the second transistor and the third transistor, and provides a reference potential to the first terminal of the first transistor. Wherein, the reset period is prior to the compensation period, the compensation period is prior to the data writing period, and the data writing period is prior to the light emitting period.
本发明又再提出一种发光二极管像素电路的驱动方法,用以驱动上述的具有第一至第五晶体管的发光二极管像素电路,此驱动方法包括:于重置期间中,导通第一晶体管、第三晶体管与第五晶体管,同时提供参考电位至第一晶体管的第一端;于补偿期间中,导通第一晶体管与第二晶体管,同时关闭第三晶体管与第五晶体管,并提供参考电位至第一晶体管的第一端;于数据写入期间中,导通第一晶体管与第三晶体管,以及关闭第二晶体管与第五晶体管,其中第一晶体管与第三晶体管并不同时导通,且第一晶体管的导通时间先于第三晶体管的导通时间,并在第一晶体管导通时提供数据电位至第一晶体管的第一端;以及,于发光期间中,关闭第一晶体管与第五晶体管,并导通第二晶体管与第三晶体管,以及提供参考电位至第一晶体管的第一端。其中,重置期间先于补偿期间,补偿期间先于数据写入期间,数据写入期间先于发光期间。The present invention further proposes a driving method of a light emitting diode pixel circuit, which is used to drive the above light emitting diode pixel circuit with the first to fifth transistors. The driving method includes: during the reset period, turning on the first transistor, The third transistor and the fifth transistor simultaneously provide a reference potential to the first terminal of the first transistor; during the compensation period, the first transistor and the second transistor are turned on, and the third transistor and the fifth transistor are simultaneously turned off, and a reference potential is provided To the first end of the first transistor; during the data writing period, turn on the first transistor and the third transistor, and turn off the second transistor and the fifth transistor, wherein the first transistor and the third transistor are not turned on at the same time, And the turn-on time of the first transistor is earlier than the turn-on time of the third transistor, and when the first transistor is turned on, the data potential is provided to the first end of the first transistor; and, during the light-emitting period, the first transistor and the first transistor are turned off The fifth transistor turns on the second transistor and the third transistor, and provides a reference potential to the first terminal of the first transistor. Wherein, the reset period is prior to the compensation period, the compensation period is prior to the data writing period, and the data writing period is prior to the light emitting period.
在本发明的发光二极管像素电路的电路架构中,采用例如是由二个电容与一个晶体管所构成的电容模块来电性耦接于驱动晶体管的控制端与源极端之间,并利用此晶体管来决定是否让上述二个电容皆电性耦接于驱动晶体管的控制端与源极端之间,或是仅让其中一个电容电性耦接于驱动晶体管的控制端与源极端之间,藉以在发光二极管像素电路的不同操作期间中改变电性耦接于驱动晶体管的控制端与源极端之间的等效电容的容值大小。据此,只要在重置期间与发光期间中导通此晶体管而使得上述二个电容并联,并在其余二个期间中关闭此晶体管,那么本发明的发光二极管像素电路便可避免发生公知技术中的发光二极管的发光电流减少,以及补偿速度变慢等问题。In the circuit structure of the light-emitting diode pixel circuit of the present invention, for example, a capacitor module composed of two capacitors and a transistor is used to electrically couple between the control terminal and the source terminal of the driving transistor, and the transistor is used to determine Whether the above two capacitors are electrically coupled between the control terminal and the source terminal of the driving transistor, or only one of the capacitors is electrically coupled between the control terminal and the source terminal of the driving transistor, so that the light emitting diode During different operation periods of the pixel circuit, the capacitance value of the equivalent capacitance electrically coupled between the control terminal and the source terminal of the driving transistor is changed. Accordingly, as long as the transistor is turned on during the reset period and the light-emitting period so that the above-mentioned two capacitors are connected in parallel, and the transistor is turned off during the remaining two periods, then the light-emitting diode pixel circuit of the present invention can avoid the problem of the conventional technology. The light-emitting current of the light-emitting diode is reduced, and the compensation speed is slowed down.
附图说明Description of drawings
图1所绘示为本发明一实施例的发光二极管像素电路的电路架构图;FIG. 1 shows a circuit structure diagram of an LED pixel circuit according to an embodiment of the present invention;
图2所绘示为图1所示的发光二极管像素电路的其中一种信号时序图;FIG. 2 is one signal timing diagram of the LED pixel circuit shown in FIG. 1;
图3所绘示为本发明另一实施例的发光二极管像素电路的电路架构图;FIG. 3 is a circuit structure diagram of an LED pixel circuit according to another embodiment of the present invention;
图4所绘示为图3所示的发光二极管像素电路的其中一种信号时序图;FIG. 4 is one signal timing diagram of the LED pixel circuit shown in FIG. 3;
图5为本发明的其中一个发光二极管像素电路的其中一个操作流程;FIG. 5 is one of the operation procedures of one of the LED pixel circuits of the present invention;
图6为本发明的另一个发光二极管像素电路的其中一个操作流程。FIG. 6 is an operation flow of another LED pixel circuit of the present invention.
[主要组件附图标记说明][Description of main component reference signs]
100、200:发光二极管像素驱动电路100, 200: Light-emitting diode pixel drive circuit
11、12、13、14、15:晶体管11, 12, 13, 14, 15: Transistors
C1、C2、C3:电容C1, C2, C3: capacitance
20:发光二极管20: LED
110、120、130、140、150:控制端110, 120, 130, 140, 150: control terminal
111、121、131、141、151、C11、C21、C31、201:第一端111, 121, 131, 141, 151, C11, C21, C31, 201: first end
112、122、132、142、152、C12、C22、C32、202:第二端112, 122, 132, 142, 152, C12, C22, C32, 202: second end
Scan、EM、Reset1、Reset2:控制信号Scan, EM, Reset1, Reset2: control signal
Data:数据信号Vdata:数据电位Vref:参考电位Data: data signal Vdata: data potential Vref: reference potential
Vsus:预设电位OVDD、:操作电源Vsus: preset potential OVDD, : Operating power
OVDDH、OVDDL、H、L:电位OVDDH, OVDDL, H, L: potential
G、S:节点G, S: node
t:预设时间t: preset time
501、502、503、504、601、602、603、604:步骤501, 502, 503, 504, 601, 602, 603, 604: steps
具体实施方式detailed description
图1所绘示为本发明一实施例的发光二极管像素电路的电路架构图。如图1所示,发光二极管像素电路100包括晶体管11、晶体管12、晶体管13、晶体管14(用以作为驱动晶体管)、电容C1、电容C2,以及发光二极管20。此外,在此例中,以C3来表示发光二极管20本身固有的等效电容。另外,在此例中,电容C2的电容值大于电容C1的电容值,且电容C1与C2二个加起来的电容值等于前述公知技术中,电性耦接于驱动晶体管的控制端与源极端之间的等效电容于容值增加后的电容值Ct。晶体管11具有控制端110、第一端111以及第二端112。晶体管11的控制端110电性耦接于控制信号Scan,以藉由控制信号Scan导通或是关闭晶体管11。晶体管11的第一端111用以接收数据信号Data,此数据信号Data可以提供数据电位Vdata或是参考电位Vref至晶体管11的第一端111。FIG. 1 is a circuit structure diagram of an LED pixel circuit according to an embodiment of the present invention. As shown in FIG. 1 , the LED pixel circuit 100 includes a transistor 11 , a transistor 12 , a transistor 13 , a transistor 14 (used as a driving transistor), a capacitor C1 , a capacitor C2 , and a LED 20 . In addition, in this example, C3 represents the inherent equivalent capacitance of the light emitting diode 20 itself. In addition, in this example, the capacitance value of the capacitor C2 is greater than the capacitance value of the capacitor C1, and the combined capacitance value of the capacitors C1 and C2 is equal to that electrically coupled to the control terminal and the source terminal of the driving transistor in the prior art. The equivalent capacitance between is the capacitance value Ct after the capacitance value is increased. The transistor 11 has a control terminal 110 , a first terminal 111 and a second terminal 112 . The control terminal 110 of the transistor 11 is electrically coupled to the control signal Scan, so that the transistor 11 is turned on or off by the control signal Scan. The first terminal 111 of the transistor 11 is used to receive the data signal Data, and the data signal Data can provide a data potential Vdata or a reference potential Vref to the first terminal 111 of the transistor 11 .
晶体管12具有控制端120、第一端121、以及第二端122。晶体管12的控制端120电性耦接于控制信号EM,以藉由控制信号EM导通或是关闭晶体管12。晶体管12的第一端121电性耦接于操作电源OVDD。晶体管13具有控制端130、第一端131、以及第二端132。晶体管13的控制端130电性耦接于控制信号Reset1,以藉由控制信号Reset1导通或是关闭晶体管13。晶体管14具有控制端140、第一端141、以及第二端142。晶体管14的第一端141电性耦接于晶体管12的第二端122,且晶体管14的第二端142电性耦接于晶体管13的第二端132,而晶体管14的控制端140电性耦接于晶体管11的第二端112。The transistor 12 has a control terminal 120 , a first terminal 121 , and a second terminal 122 . The control terminal 120 of the transistor 12 is electrically coupled to the control signal EM, so that the transistor 12 is turned on or off by the control signal EM. The first end 121 of the transistor 12 is electrically coupled to the operating power supply OVDD. The transistor 13 has a control terminal 130 , a first terminal 131 , and a second terminal 132 . The control terminal 130 of the transistor 13 is electrically coupled to the control signal Reset1, so that the transistor 13 is turned on or off by the control signal Reset1. The transistor 14 has a control terminal 140 , a first terminal 141 , and a second terminal 142 . The first terminal 141 of the transistor 14 is electrically coupled to the second terminal 122 of the transistor 12, and the second terminal 142 of the transistor 14 is electrically coupled to the second terminal 132 of the transistor 13, and the control terminal 140 of the transistor 14 is electrically coupled Coupled to the second terminal 112 of the transistor 11 .
电容C1具有第一端C11及第二端C12。电容C1的第一端C11电性耦接于晶体管14的控制端140,且电容C1的第二端C12与晶体管14的第二端142以及晶体管13的第二端132共同电性耦接。电容C2具有第一端C21及第二端C22。电容C2的第一端C21与晶体管11的第二端112以及电容C1的第一端C11共同电性耦接,且电容C2的第二端C22电性耦接于晶体管13的第一端131。发光二极管20具有第一端201以及第二端202。发光二极管20的第一端201电性耦接于晶体管14的第二端142,且发光二极管20的第二端202电性耦接于操作电源OVSS。The capacitor C1 has a first terminal C11 and a second terminal C12. The first terminal C11 of the capacitor C1 is electrically coupled to the control terminal 140 of the transistor 14 , and the second terminal C12 of the capacitor C1 is electrically coupled to the second terminal 142 of the transistor 14 and the second terminal 132 of the transistor 13 . The capacitor C2 has a first terminal C21 and a second terminal C22. The first terminal C21 of the capacitor C2 is electrically coupled to the second terminal 112 of the transistor 11 and the first terminal C11 of the capacitor C1 , and the second terminal C22 of the capacitor C2 is electrically coupled to the first terminal 131 of the transistor 13 . The LED 20 has a first end 201 and a second end 202 . The first terminal 201 of the LED 20 is electrically coupled to the second terminal 142 of the transistor 14 , and the second terminal 202 of the LED 20 is electrically coupled to the operating power supply OVSS.
图2所绘示为图1所示的发光二极管像素电路的其中一种信号时序图。如图2所示,图1的发光二极管像素电路100可依序运作于重置期间、补偿期间、数据写入期间、以及发光期间,其中各信号可以具有高电平H及低电平L两种状态,高电平H施加于N型晶体管的栅极时,可以使得N型晶体管导通,但高电平H施加于P型晶体管的栅极时,则会使得P型晶体管关闭;反之,低电平L施加于N型晶体管的栅极时,会使得N型晶体管关闭,而低电平L施加于P型晶体管的栅极时,则可以使得P型晶体管导通。高电平H可以例如等于电位OVDDH,而低电平L可以例如等于电位OVDDL。请共同参照图1及图2,发光二极管像素电路100的晶体管11用以于重置期间、补偿期间以及数据写入期间时导通,且晶体管11的第一端111于数据写入期间时接收数据信号Data所提供的数据电位Vdata,并于重置期间、补偿期间以及发光期间时接收数据信号Data所提供的参考电位Vref。晶体管12用以于重置期间、补偿期间以及发光期间时导通,且晶体管12的第一端121于重置期间时接收操作电源OVDD所提供的电位OVDDL,而晶体管12的第一端121于补偿期间、数据写入期间及发光期间时接收操作电源OVDD所提供的电位OVDDH,且电位OVDDL小于电位OVDDH。晶体管13用以于重置期间、数据写入期间以及发光期间时导通。特别一提的是,于数据写入期间中,晶体管13及晶体管11的导通时间可为部分重叠或不重叠(在图2中不重叠),且晶体管13的导通时间晚于晶体管11的导通时间。此外,由于操作电源OVDD在重置期间当中提供电位OVDDL,因此使得节点S上的电位会为OVDDL,此时电容C1以及C2会透过节点S进行放电以重置发光二极管像素电路100。FIG. 2 is a signal timing diagram of one of the LED pixel circuits shown in FIG. 1 . As shown in FIG. 2 , the light-emitting diode pixel circuit 100 in FIG. 1 can operate in sequence during the reset period, the compensation period, the data writing period, and the light-emitting period, wherein each signal can have a high level H and a low level L. In this state, when a high level H is applied to the gate of the N-type transistor, the N-type transistor can be turned on, but when a high level H is applied to the gate of the P-type transistor, the P-type transistor will be turned off; otherwise, When the low level L is applied to the gate of the N-type transistor, the N-type transistor will be turned off, and when the low level L is applied to the gate of the P-type transistor, the P-type transistor will be turned on. The high level H may be equal to the potential OVDDH, for example, and the low level L may be equal to the potential OVDDL, for example. Please refer to FIG. 1 and FIG. 2 together. The transistor 11 of the light-emitting diode pixel circuit 100 is used to conduct during the reset period, the compensation period, and the data writing period, and the first terminal 111 of the transistor 11 receives during the data writing period. The data potential Vdata provided by the data signal Data receives the reference potential Vref provided by the data signal Data during the reset period, the compensation period and the light emitting period. The transistor 12 is used to turn on during the reset period, the compensation period and the light-emitting period, and the first terminal 121 of the transistor 12 receives the potential OVDDL provided by the operating power supply OVDD during the reset period, and the first terminal 121 of the transistor 12 is in the reset period. The potential OVDDH provided by the operation power supply OVDD is received during the compensation period, the data writing period and the light emitting period, and the potential OVDDL is lower than the potential OVDDH. The transistor 13 is turned on during the reset period, the data writing period and the light emitting period. In particular, during the data writing period, the conduction times of the transistor 13 and the transistor 11 may partially overlap or not overlap (in FIG. 2 ), and the conduction time of the transistor 13 is later than that of the transistor 11. on-time. In addition, since the operating power supply OVDD provides the potential OVDDL during the reset period, the potential on the node S will be OVDDL. At this time, the capacitors C1 and C2 will discharge through the node S to reset the LED pixel circuit 100 .
以图2所示为例,详细而言,当发光二极管像素电路100运作于重置期间时,晶体管11、晶体管12以及晶体管13会分别被控制信号Scan、控制信号EM以及控制信号Reset1所导通,且此时晶体管11的第一端111接收数据信号Data所提供的参考电位Vref,晶体管12的第一端121接收操作电源OVDD所提供的电位OVDDL,所以此时节点G的电位Vg在理想情况下会等于Vref,而节点S的电位Vs在理想情况下会等于OVDDL。接着,当发光二极管像素电路100运作于补偿期间时,晶体管11仍然维持导通状态,且晶体管11的第一端111持续接收数据信号Data所提供的参考电位Vref,而晶体管12亦仍然维持导通状态,但是晶体管12的第一端此时接收的是操作电源OVDD所提供的电位OVDDH,至于晶体管13于此期间则是被关闭,所以此时节点G的电位Vg仍然是Vref,而节点S的电位Vs则会由电位OVDDL的电平持续上升至等于或者实质上等于Vref-Vth,其中Vth为晶体管14的临界电压值(Threshold Voltage)。由于电容C1与C2二个加起来的电容值等于前述公知技术中,电性耦接于驱动晶体管的控制端与源极端之间的等效电容于容值增加后的电容值Ct,且在此时,整个发光二极管像素电路100仅需对电容C1与C3进行充电,而不需对电容C2进行充电,因此可加速补偿的速度。Taking FIG. 2 as an example, in detail, when the LED pixel circuit 100 is operating in the reset period, the transistor 11, the transistor 12 and the transistor 13 will be turned on by the control signal Scan, the control signal EM and the control signal Reset1 respectively. , and at this time, the first terminal 111 of the transistor 11 receives the reference potential Vref provided by the data signal Data, and the first terminal 121 of the transistor 12 receives the potential OVDDL provided by the operating power supply OVDD, so the potential Vg of the node G at this time is ideally will be equal to Vref, and the potential Vs of node S will be equal to OVDDL under ideal conditions. Next, when the LED pixel circuit 100 is operating in the compensation period, the transistor 11 is still turned on, and the first terminal 111 of the transistor 11 continues to receive the reference potential Vref provided by the data signal Data, and the transistor 12 is still turned on. state, but the first terminal of the transistor 12 receives the potential OVDDH provided by the operating power supply OVDD at this time, and the transistor 13 is turned off during this period, so the potential Vg of the node G is still Vref at this time, and the potential of the node S The potential Vs will continue to rise from the level of the potential OVDDL to be equal to or substantially equal to Vref−Vth, wherein Vth is a threshold voltage (Threshold Voltage) of the transistor 14 . Since the combined capacitance of the capacitors C1 and C2 is equal to the capacitance Ct of the equivalent capacitance electrically coupled between the control terminal and the source terminal of the driving transistor in the aforementioned known technology after the capacitance value is increased, and here At this time, the entire LED pixel circuit 100 only needs to charge the capacitors C1 and C3 instead of the capacitor C2, so the speed of compensation can be accelerated.
再接着,当发光二极管像素电路100运作于数据写入期间时,晶体管11会在一段预设时间t1之后被关闭,而在晶体管11被关闭之前,晶体管11的第一端111会接收数据信号Data所提供的数据电位Vdata。此外,在数据写入期间时,晶体管12会被关闭,而晶体管13会在上述的预设时间t1之后被导通(例如在进入数据写入期间t2后导通,即晶体管13及晶体管11的导通时间为不重叠),所以此时节点G的电位Vg在理想情况下会等于Vdata,而节点S的电位透过电容耦合则会变成Vref-Vth+a(Vdata-Vret),因为节点G由Vref电压电平转变为Vdata电压电平时,晶体管13为关闭状态,所以a为C1/(C1+C3)。Next, when the LED pixel circuit 100 is operating in the data writing period, the transistor 11 will be turned off after a preset time t1, and before the transistor 11 is turned off, the first terminal 111 of the transistor 11 will receive the data signal Data The provided data potential Vdata. In addition, during the data writing period, the transistor 12 will be turned off, and the transistor 13 will be turned on after the above-mentioned preset time t1 (for example, it will be turned on after entering the data writing period t2, that is, the transistor 13 and the transistor 11 The conduction time is non-overlapping), so the potential Vg of the node G at this time will be equal to Vdata under ideal conditions, and the potential of the node S will become Vref-Vth+a (Vdata-Vret) through capacitive coupling, because the node When G changes from the voltage level of Vref to the voltage level of Vdata, the transistor 13 is turned off, so a is C1/(C1+C3).
由上述可知,由于电容C1的电容值小于公知技术中原本电性耦接于驱动晶体管的控制端与源极端之间的等效电容于容值增加后的电容值Ct,因此在发光二极管像素电路100自补偿期间进入数据写入期间时,由节点G耦合至节点S的电压会变小,这样便拉大了节点G与节点S之间的压差。如此一来,通过晶体管14的电流量便会增加,进而可以提高流过发光二极管20的发光电流。It can be seen from the above that since the capacitance value of the capacitor C1 is smaller than the capacitance value Ct of the equivalent capacitance originally electrically coupled between the control terminal and the source terminal of the driving transistor in the known technology after the capacitance value is increased, the light-emitting diode pixel circuit When the 100 self-compensation period enters the data writing period, the voltage coupled from the node G to the node S will decrease, thus increasing the voltage difference between the node G and the node S. In this way, the amount of current passing through the transistor 14 will increase, thereby increasing the light-emitting current flowing through the light-emitting diode 20 .
最后,当发光二极管像素电路100运作于发光期间时,晶体管11维持关闭,晶体管12以及晶体管13则维持导通,且晶体管12持续接收操作电源OVDD所提供的电位OVDDH。此时,节点S的电位变化量会耦合至节点G,而其耦合量可用(C1+C2)/(C1+C2+Cp)式来计算,其中Cp(图未示)为与节点G相关的的寄生电容值。由上式可知,由于电容C1与C2的电容值加起来等于前述公知技术中,电性耦接于驱动晶体管的控制端与源极端之间的等效电容于容值增加后的电容值Ct,因此,这样的做法同样可以降低寄生电容效应。Finally, when the LED pixel circuit 100 is operating in the light-emitting period, the transistor 11 remains turned off, the transistors 12 and 13 remain turned on, and the transistor 12 continues to receive the potential OVDDH provided by the operating power supply OVDD. At this time, the potential change of node S will be coupled to node G, and the coupling amount can be calculated by the formula (C1+C2)/(C1+C2+Cp), where Cp (not shown) is related to node G the parasitic capacitance value. It can be seen from the above formula that since the sum of the capacitance values of the capacitors C1 and C2 is equal to the capacitance value Ct after the increase of the equivalent capacitance electrically coupled between the control terminal and the source terminal of the driving transistor in the aforementioned known technology, Therefore, such an approach can also reduce the parasitic capacitance effect.
在另一个例子的数据写入期间中,控制信号Scan由高电平(high)转态至低电平(low)的时间可以是晚于控制信号Reset1由低电平转态至高电平的时间,以使得晶体管13及晶体管11的导通时间为部分重叠,进而避免节点G在这二个控制信号的转态过程中因呈现浮接状态而受到电容C1与C2所耦合的电压的影响而改变其电平。In another example of the data writing period, the time when the control signal Scan transitions from high level (high) to low level (low) may be later than the time when the control signal Reset1 transitions from low level to high level , so that the conduction times of the transistor 13 and the transistor 11 are partially overlapped, thereby preventing the node G from changing due to being in a floating state due to the influence of the voltage coupled by the capacitors C1 and C2 during the transition process of the two control signals its level.
当然,尽管在图1所示的实施例中,电容C3表示发光二极管20本身固有的等效电容,然而在发光二极管20本身固有的等效电容的电容值不足的情况下,设计者自可在发光二极管20旁并联一个实体电容,使得发光二极管20的第一端201与第二端202之间的等效电容值可为发光二极管20本身固有的等效电容与并联的电容的电容值总合。Of course, although in the embodiment shown in FIG. 1 , the capacitor C3 represents the inherent equivalent capacitance of the light emitting diode 20 itself, but in the case of insufficient capacitance value of the inherent equivalent capacitance of the light emitting diode 20 itself, the designer can freely A physical capacitor is connected in parallel next to the light emitting diode 20, so that the equivalent capacitance between the first end 201 and the second end 202 of the light emitting diode 20 can be the sum of the inherent equivalent capacitance of the light emitting diode 20 itself and the capacitance of the parallel capacitor. .
图3所绘示为本发明另一实施例的发光二极管像素电路的电路架构图。在图3中,与图1中的标号相同者代表相同的组件或信号。如图3所示,发光二极管像素电路200与图1中的发光二极管像素电路100的电路架构大致相同,差异仅在于发光二极管像素电路200更包括一个晶体管15。晶体管15具有控制端150、第一端151以及第二端152,且晶体管15的控制端150接收控制信号Reset2,晶体管15的第一端151电性耦接于一个预设电位Vsus(其电位大小与电位OVDDL相同或约略相等),而晶体管15的第二端152电性耦接于晶体管13的第一端131。FIG. 3 is a circuit structure diagram of an LED pixel circuit according to another embodiment of the present invention. In FIG. 3, the same reference numerals as those in FIG. 1 represent the same components or signals. As shown in FIG. 3 , the circuit structure of the LED pixel circuit 200 is substantially the same as that of the LED pixel circuit 100 in FIG. 1 , the only difference being that the LED pixel circuit 200 further includes a transistor 15 . The transistor 15 has a control terminal 150, a first terminal 151 and a second terminal 152, and the control terminal 150 of the transistor 15 receives the control signal Reset2, and the first terminal 151 of the transistor 15 is electrically coupled to a preset potential Vsus (its potential magnitude same or approximately equal to the potential OVDDL), and the second terminal 152 of the transistor 15 is electrically coupled to the first terminal 131 of the transistor 13 .
图4所绘示为图3所示的发光二极管像素电路的其中一种信号时序图。如图4所示,发光二极管像素电路200亦是依序运作于重置期间、补偿期间、数据写入期间以及发光期间。发光二极管像素电路200之中的晶体管11用以于重置期间、补偿期间及数据写入期间时导通,且晶体管11的第一端111于数据写入期间时接收数据信号Data所提供的数据电位Vdata,并于重置期间、补偿期间以及发光期间时接收数据信号Data所提供的参考电位Vref。发光二极管像素电路200之中的晶体管12用以于补偿期间及发光期间时导通。发光二极管像素电路200之中的晶体管13用以于重置期间、数据写入期间以及发光期间时导通。其中,于数据写入期间中,发光二极管像素电路200之中的晶体管13以及晶体管11的导通时间亦可为部分重叠或不重叠(在图4中不重叠,可设计为重叠的原因亦如先前所述),且晶体管13的导通时间晚于晶体管11的导通时间。而发光二极管像素电路200之中的晶体管15用以于重置期间时导通,且晶体管15的第一端151于重置期间时接收预设电位Vsus,预设电位Vsus可以例如具有电位OVDDL。此外,由于在重置期间提供预设电位Vsus至电容C1的其中一端以及电容C2的其中一端,因此此时电容C1以及C2会进行放电以重置发光二极管像素电路200。FIG. 4 is a signal timing diagram of one of the LED pixel circuits shown in FIG. 3 . As shown in FIG. 4 , the LED pixel circuit 200 also operates in the reset period, the compensation period, the data writing period and the light emitting period in sequence. The transistor 11 in the LED pixel circuit 200 is used to conduct during the reset period, the compensation period and the data writing period, and the first terminal 111 of the transistor 11 receives the data provided by the data signal Data during the data writing period. potential Vdata, and receive the reference potential Vref provided by the data signal Data during the reset period, the compensation period and the light-emitting period. The transistor 12 in the LED pixel circuit 200 is turned on during the compensation period and the light-emitting period. The transistor 13 in the LED pixel circuit 200 is turned on during the reset period, the data writing period and the light emitting period. Wherein, during the data writing period, the turn-on time of the transistor 13 and the transistor 11 in the LED pixel circuit 200 can also be partially overlapped or not overlapped (in FIG. previously described), and the turn-on time of transistor 13 is later than the turn-on time of transistor 11 . The transistor 15 in the LED pixel circuit 200 is turned on during the reset period, and the first terminal 151 of the transistor 15 receives the preset potential Vsus during the reset period. The preset potential Vsus may have a potential OVDDL, for example. In addition, since the preset potential Vsus is provided to one terminal of the capacitor C1 and one terminal of the capacitor C2 during the reset period, the capacitors C1 and C2 are discharged to reset the LED pixel circuit 200 at this time.
虽然在先前的叙述当中,电容C1、电容C2以及晶体管13均为各自独立的组件,但是也可以将此三者视为一个电容模块。此电容模块用以在晶体管14的控制端140与晶体管14的第二端142之间提供一个等效电容,且此电容模块在发光二极管像素电路处于重置期间以及发光期间时所提供的等效电容的容值大于发光二极管像素电路处于补偿期间以及数据写入期间时所提供的等效电容的容值。当然,上述的电容模块的实现方式仅是用以举例,并非用以限制本发明。Although in the previous description, the capacitor C1 , the capacitor C2 and the transistor 13 are all independent components, they can also be regarded as a capacitor module. The capacitance module is used to provide an equivalent capacitance between the control terminal 140 of the transistor 14 and the second terminal 142 of the transistor 14, and the equivalent capacitance provided by the capacitance module is during the reset period and the light-emitting period of the LED pixel circuit. The capacitance value of the capacitor is greater than the capacitance value of the equivalent capacitance provided when the LED pixel circuit is in the compensation period and the data writing period. Of course, the implementation of the above-mentioned capacitor module is only used as an example, and is not intended to limit the present invention.
图5为本发明一实施例的发光二极管像素电路的驱动方法流程图。透过上述的叙述,可以将发光二极管像素电路100的驱动方法归纳出如图5所示的步骤501~504。FIG. 5 is a flow chart of a driving method of an LED pixel circuit according to an embodiment of the present invention. Through the above description, the driving method of the LED pixel circuit 100 can be summarized into steps 501 - 504 as shown in FIG. 5 .
步骤501:于重置期间中,使操作电源OVDD提供电位OVDDL,并导通晶体管11、晶体管12以及晶体管13,同时提供参考电位Vref至晶体管11的第一端111。步骤502:于补偿期间中,使操作电源OVDD提供电位OVDDH,电位OVDDH大于电位OVDDL,并导通晶体管11与晶体管12,同时关闭晶体管13,并提供参考电位Vref至晶体管11的第一端111。步骤503:于数据写入期间中,使操作电源OVDD提供电位OVDDH,并导通晶体管11与晶体管13,以及关闭晶体管12,其中晶体管11与晶体管13的导通时间为部分重叠或不重叠,且晶体管11的导通时间先于与晶体管13的导通时间,并在晶体管11导通时提供数据电位Vdata至晶体管11的第一端111。步骤504:于发光期间中,使操作电源OVDD提供电位OVDDH,并关闭晶体管11,以及导通晶体管12与晶体管13,并提供参考电位Vref至晶体管11的第一端111。在上述的步骤501~504之中,重置期间先于补偿期间,补偿期间先于数据写入期间,数据写入期间先于发光期间。Step 501 : During the reset period, make the operating power supply OVDD provide the potential OVDDL, turn on the transistor 11 , the transistor 12 and the transistor 13 , and provide the reference potential Vref to the first terminal 111 of the transistor 11 . Step 502: During the compensation period, make the operating power supply OVDD provide a potential OVDDH, the potential OVDDH is greater than the potential OVDDL, turn on the transistor 11 and the transistor 12, turn off the transistor 13, and provide the reference potential Vref to the first terminal 111 of the transistor 11. Step 503: During the data writing period, make the operating power supply OVDD provide a potential OVDDH, turn on the transistor 11 and the transistor 13, and turn off the transistor 12, wherein the turn-on time of the transistor 11 and the transistor 13 is partially overlapped or not overlapped, and The turn-on time of the transistor 11 is earlier than the turn-on time of the transistor 13 , and provides the data potential Vdata to the first terminal 111 of the transistor 11 when the transistor 11 is turned on. Step 504 : During the light-emitting period, make the operating power supply OVDD provide the potential OVDDH, turn off the transistor 11 , turn on the transistor 12 and the transistor 13 , and provide the reference potential Vref to the first terminal 111 of the transistor 11 . In the above steps 501-504, the reset period is prior to the compensation period, the compensation period is prior to the data writing period, and the data writing period is prior to the light emitting period.
图6为本发明一实施例的发光二极管像素电路的驱动方法流程图。透过上述的叙述,可以将发光二极管像素电路200的驱动方法归纳出如图6所示的步骤601~604。FIG. 6 is a flow chart of a driving method of an LED pixel circuit according to an embodiment of the present invention. Through the above description, the driving method of the LED pixel circuit 200 can be summarized into steps 601 - 604 as shown in FIG. 6 .
步骤601:于重置期间中,导通晶体管11、晶体管13与晶体管15,同时提供参考电位Vref至晶体管11的第一端111。步骤602:于补偿期间中,导通晶体管11与晶体管12,同时关闭晶体管13与晶体管15,并提供参考电位Vref至晶体管11的第一端111。步骤603:于数据写入期间中,导通晶体管11与晶体管13,以及关闭晶体管12与晶体管15,其中晶体管11与晶体管13的导通时间为部分重叠或不重叠,且晶体管11的导通时间先于晶体管13的导通时间,并在晶体管11导通时提供数据电位Vdata至晶体管11的第一端111。步骤604:于发光期间中,关闭晶体管11与晶体管15,并导通晶体管12与晶体管13,以及提供参考电位Vref至晶体管11的第一端111。在上述的步骤601~604之中,重置期间先于补偿期间,补偿期间先于数据写入期间,数据写入期间先于发光期间。Step 601 : During the reset period, turn on the transistor 11 , the transistor 13 and the transistor 15 , and provide the reference potential Vref to the first terminal 111 of the transistor 11 at the same time. Step 602 : During the compensation period, turn on the transistor 11 and the transistor 12 , turn off the transistor 13 and the transistor 15 at the same time, and provide the reference potential Vref to the first terminal 111 of the transistor 11 . Step 603: During the data writing period, turn on the transistor 11 and the transistor 13, and turn off the transistor 12 and the transistor 15, wherein the turn-on time of the transistor 11 and the transistor 13 is partially overlapped or non-overlapping, and the turn-on time of the transistor 11 The data potential Vdata is provided to the first terminal 111 of the transistor 11 prior to the turn-on time of the transistor 13 and when the transistor 11 is turned on. Step 604 : During the light-emitting period, turn off the transistor 11 and the transistor 15 , turn on the transistor 12 and the transistor 13 , and provide the reference potential Vref to the first terminal 111 of the transistor 11 . In the above steps 601-604, the reset period is prior to the compensation period, the compensation period is prior to the data writing period, and the data writing period is prior to the light emitting period.
综上所述,在本发明的发光二极管像素电路的电路架构中,采用例如是由二个电容与一个晶体管所构成的电容模块来电性耦接于驱动晶体管的控制端与源极端之间,并利用此晶体管来决定是否让上述二个电容皆电性耦接于驱动晶体管的控制端与源极端之间,或是仅让其中一个电容电性耦接于驱动晶体管的控制端与源极端之间,藉以在发光二极管像素电路的不同操作期间中改变电性耦接于驱动晶体管的控制端与源极端之间的等效电容的容值大小。据此,只要在重置期间与发光期间中导通此晶体管而使得上述二个电容并联,并在其余二个期间中关闭此晶体管,那么本发明的发光二极管像素电路便可避免发生公知技术中之发光二极管的发光电流减少,以及补偿速度变慢等问题。To sum up, in the circuit structure of the light-emitting diode pixel circuit of the present invention, for example, a capacitor module composed of two capacitors and a transistor is used to electrically couple between the control terminal and the source terminal of the driving transistor, and Use this transistor to decide whether to make the above two capacitors electrically coupled between the control terminal and the source terminal of the drive transistor, or to allow only one of the capacitors to be electrically coupled between the control terminal and the source terminal of the drive transistor , so as to change the capacitance value of the equivalent capacitance electrically coupled between the control terminal and the source terminal of the driving transistor during different operation periods of the LED pixel circuit. Accordingly, as long as the transistor is turned on during the reset period and the light-emitting period so that the above-mentioned two capacitors are connected in parallel, and the transistor is turned off during the remaining two periods, then the light-emitting diode pixel circuit of the present invention can avoid the problem of the conventional technology. The light-emitting current of the light-emitting diode is reduced, and the compensation speed is slowed down.
虽然本发明已以较佳实施例揭露如上,然其并非用以限定本发明,任何熟习此技艺者,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,因此本发明的保护范围当视后附之权利要求所界定者为准。Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of the invention shall prevail as defined by the appended claims.
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CN108877649B (en) * | 2017-05-12 | 2020-07-24 | 京东方科技集团股份有限公司 | Pixel circuit and driving method thereof, and display panel |
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CN115665566B (en) * | 2019-03-28 | 2025-05-23 | 群创光电股份有限公司 | Electronic device |
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TWI731697B (en) * | 2020-05-26 | 2021-06-21 | 友達光電股份有限公司 | Pixel driving circuit |
TWI754478B (en) * | 2020-06-10 | 2022-02-01 | 友達光電股份有限公司 | Pixel circuit |
TWI738426B (en) * | 2020-07-20 | 2021-09-01 | 友達光電股份有限公司 | Pixel circuit and pixel circuit driving method |
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