CN104142594A - Thin film transistor substrate and display device - Google Patents
Thin film transistor substrate and display device Download PDFInfo
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- CN104142594A CN104142594A CN201310172418.6A CN201310172418A CN104142594A CN 104142594 A CN104142594 A CN 104142594A CN 201310172418 A CN201310172418 A CN 201310172418A CN 104142594 A CN104142594 A CN 104142594A
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- 239000010409 thin film Substances 0.000 title claims abstract description 73
- 239000000758 substrate Substances 0.000 title claims abstract description 45
- 238000010586 diagram Methods 0.000 description 26
- 239000004973 liquid crystal related substance Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910003437 indium oxide Inorganic materials 0.000 description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- 239000011701 zinc Substances 0.000 description 2
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- YSRUGFMGLKANGO-UHFFFAOYSA-N zinc hafnium(4+) indium(3+) oxygen(2-) Chemical compound [O-2].[Zn+2].[In+3].[Hf+4] YSRUGFMGLKANGO-UHFFFAOYSA-N 0.000 description 1
- RNWHGQJWIACOKP-UHFFFAOYSA-N zinc;oxygen(2-) Chemical compound [O-2].[Zn+2] RNWHGQJWIACOKP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Geometry (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
A thin film transistor substrate includes a substrate, a plurality of pixel electrodes, a gate layer, an active layer, a first source layer, a second source layer, and a drain layer. The pixel electrodes are arranged on the substrate. The gate layer is disposed on the substrate. The active layer is disposed opposite to the gate layer. The first source layer and the second source layer are respectively in contact with the active layer. The drain layer is in contact with the active layer and is electrically connected with one of the plurality of pixel electrodes. The gate layer, the active layer, the first source layer and the drain layer form a first transistor, the gate layer, the active layer, the second source layer and the drain layer form a second transistor, and the first source layer and the second source layer are electrically insulated when the first transistor and the second transistor are closed. The invention also discloses a display device with the thin film transistor substrate. The capacitance is reduced by the circuit layout mode, the element layout efficiency of unit area is improved, and further the delay and the deformation of signals are reduced.
Description
Technical field
The invention relates to a kind of thin film transistor base plate and there is the display device of this thin film transistor base plate.
Background technology
Along with scientific and technological progress, display device has been used in various fields widely, especially liquid crystal indicator, because having that build is frivolous, low power consumption and the advantageous characteristic such as radiationless, gradually replaced conventional cathode ray tube display device, and be applied in the electronic product of numerous species for example mobile phone, portable multimedia device, notebook computer, LCD TV and liquid crystal screen etc.
Generally speaking, display device is to comprise a display panel and a driver module.Driver module has scan driving circuit and a data drive circuit.Scan drive circuit is to be electrically connected to display panel by multi-strip scanning line, and data drive circuit is to be electrically connected to display panel by many data lines.In addition, display panel has a plurality of pixels, and these data lines and these sweep traces are to be to be crisscross arranged to form these pel arrays.When scan drive circuit output one scan signal makes sweep trace conducting, data drive circuit is sent to the pixel electrode of pixel by a data-signal of the every one-row pixels of correspondence by data line, so that display panel display frame.
The ON time (being sweep time) of the sweep signal of sweep trace output is mainly that quantity and the display frequency by sweep trace decides.Yet, stray capacitance due to the pel array on display panel, be for example the cross-line (cross over) of data line, the stray capacitance of switching transistor (Cgd for example, Cgs, and the loaded impedance of pixel may cause a desirable sweep signal waveform (for example square wave) to postpone and distortion forms another waveform Csd etc.).The problem that the phenomenon (being RC distortion) of this kind of signal delay and distortion especially causes when the display device of large scale, high-res and solid (3D) may be more serious, for example, may cause the missampling of pixel and display panel cannot normally be shown.Wherein, if will reduce delay and the distortion of signal, reducing impedance (R) and minimizing electric capacity (C) is necessary means.Except improving aspect of circuit design, the improved efficiency in circuit practical layout (layout), also can reach identical effect.
The flow process of general circuit layout is first equivalent electrical circuit to be finished, then the mode that is converted to layout drawing represents, finally with actual procedure for producing, makes.But identical equivalent electrical circuit but has unlimited multiple layout type to realize, therefore the lifting in circuit layout efficiency is also very important link in design.
Therefore, how to propose a kind of thin film transistor base plate and there is the display device of this thin film transistor base plate, can reduce by the mode of road layout its electric capacity, promote component placement's efficiency of unit area, and then delay and the distortion of the signal of reduction display device, become one of important topic.
Summary of the invention
Object of the present invention can reduce electric capacity by the mode of circuit layout for providing a kind of, promotes component placement's efficiency of unit area, and then reduces the delay of signal and the thin film transistor base plate of distortion and display device.
For reaching above-mentioned purpose, according to a kind of thin film transistor base plate of the present invention, comprise a substrate, a plurality of pixel electrode, a grid layer, an active layers, one first source layer, one second source layer and a drain electrode layer.Described a plurality of pixel electrode is arranged on substrate.Grid layer is arranged on substrate.Active layers and grid layer are oppositely arranged.The first source layer and the second source layer contact with active layers respectively.Drain electrode layer contacts with active layers, and is electrically connected to one of them of described a plurality of pixel electrodes.Grid layer, active layers, the first source layer and drain electrode layer are to form a first transistor, grid layer, active layers, the second source layer and drain electrode layer are to form a transistor seconds, when the first transistor and transistor seconds are closed, the first source layer and the second source layer are to be electrically insulated.
For reaching above-mentioned purpose, according to a kind of display device of the present invention, comprise a thin film transistor base plate, thin film transistor base plate has a plurality of pixel electrodes of a substrate, a grid layer, an active layers, one first source layer, one second source layer and a drain electrode layer.Described a plurality of pixel electrode is arranged on substrate.Grid layer is arranged on substrate.Active layers and grid layer are oppositely arranged.The first source layer and the second source layer contact with active layers respectively.Drain electrode layer contacts with active layers, and is electrically connected to one of them of described a plurality of pixel electrodes.Grid layer, active layers, the first source layer and drain electrode layer are to form a first transistor, grid layer, active layers, the second source layer and drain electrode layer are to form a transistor seconds, when the first transistor and transistor seconds are closed, the first source layer and the second source layer are to be electrically insulated.
In one embodiment, grid layer has a first area, and active layers has a second area, and on the projecting direction of thin film transistor base plate, first area and second area are to overlap.
In one embodiment, the size of first area is greater than the size of second area.
In one embodiment, the first source layer and the second source layer are to be adjacent to drain electrode layer.
In one embodiment, thin film transistor base plate more comprises one the 3rd source layer, and it is arranged on substrate, and contacts with active layers, and grid layer, active layers, the 3rd source layer and drain electrode layer are to form one the 3rd transistor.
In one embodiment, when the first transistor, transistor seconds and the 3rd transistor are closed, the first source layer, the second source layer and the 3rd source layer are to be electrically insulated.
In one embodiment, thin film transistor base plate more comprises another drain electrode layer, and it is arranged on substrate, and contacts with active layers, and grid layer, active layers, the first source layer and another drain electrode layer are to form one the 3rd transistor.
From the above, in thin film transistor base plate of the present invention and display device, grid layer and active layers are oppositely arranged, and the first source layer and the second source layer contact with active layers respectively, drain electrode layer contacts with active layers, and is electrically connected to one of them of described a plurality of pixel electrodes.In addition, grid layer, active layers, the first source layer and drain electrode layer are to form a first transistor, and grid layer, active layers, the second source layer and drain electrode layer are to form a transistor seconds.In addition,, when the first transistor and transistor seconds are closed, the first source layer and the second source layer are to be electrically insulated.Because the present invention will have the different thin-film transistor elements of same drain layer, mode by layout integrates active layers, therefore can reduce the area of the first transistor and the formed active layers of transistor seconds, and then reduce the overlapping area between grid layer and active layers and reduce the size of electric capacity.Therefore, by the present invention, the display device that can make thin film transistor base plate and have this thin film transistor base plate reduces its parasitic capacitance, promotes component placement's efficiency of unit area, and then promotes the driving force of transistor unit area and reduce delay and the distortion of signal.
Accompanying drawing explanation
Figure 1A is the schematic diagram of the circuit that has on the thin film transistor base plate of one embodiment of the invention.
Figure 1B is in the circuit of Figure 1A, known a kind of circuit layout schematic diagram.
Fig. 1 C is in the circuit of Figure 1A, the schematic diagram of the circuit layout of preferred embodiment of the present invention.
Fig. 2 A and Fig. 2 B are respectively in the circuit of Figure 1A, another schematic diagram of the circuit layout of preferred embodiment of the present invention.
Fig. 3 A is that another that have on thin film transistor base plate of the present invention implemented the schematic diagram of the circuit of aspect.
Fig. 3 B is in the circuit of Fig. 3 A, known a kind of circuit layout schematic diagram.
Fig. 3 C is in the circuit of Fig. 3 A, another schematic diagram of the circuit layout of preferred embodiment of the present invention.
Fig. 4 A is that another that have on thin film transistor base plate of the present invention implemented the schematic diagram of the circuit of aspect.
Fig. 4 B is in the circuit of Fig. 4 A, known a kind of circuit layout schematic diagram.
Fig. 4 C is in the circuit of Fig. 4 A, another schematic diagram of the circuit layout of preferred embodiment of the present invention.
Fig. 5 A is that another that have on thin film transistor base plate of the present invention implemented the schematic diagram of the circuit of aspect.
Fig. 5 B is in the circuit of Fig. 5 A, known a kind of circuit layout schematic diagram.
Fig. 5 C is in the circuit of Fig. 5 A, another schematic diagram of the circuit layout of preferred embodiment of the present invention.
Drawing reference numeral:
1,1a, 1b, 1c: circuit
A: active layers
A1: the first active layers
A2: the second active layers
A3: the 3rd active layers
A4: the 4th active layers
D, D1: drain electrode layer
G: grid layer
S1: the first source layer
S2: the second source layer
S3: the 3rd source layer
S4: the 4th source layer
T1: the first transistor
T2: transistor seconds
T3: the 3rd transistor
T4: the 4th transistor
Z1: first area
Z2: second area
Z3: the 3rd region
Z4: the 4th region
Z5: the 5th region
Z6: the 6th region.
Embodiment
Hereinafter with reference to correlative type, illustrate according to the thin film transistor base plate of preferred embodiment of the present invention and there is the display device of this thin film transistor base plate, wherein identical element is illustrated the reference marks with identical.
Below please refer to relevant indicators, with relatively and circuit layout of the present invention mode and known techniques difference be described.Wherein, the present invention will have the different thin-film transistor elements of same drain layer, and the mode by layout integrates active layers, and then reduces the size of electric capacity, to promote the component placement's efficiency under unit area.In addition, be the display device that circuit layout of the present invention mode and concept is applied to thin film transistor base plate and there is this thin film transistor base plate.What pay special attention to is, circuit below the present invention is a kind of giving an example, mainly that its concept is applied in the circuit layout of thin film transistor base plate and display device, reduce by this stray capacitance of thin film transistor base plate and display device, component placement's efficiency of lifting unit area, and then reduce delay and the distortion of signal.
Please respectively with reference to shown in Figure 1A to Fig. 1 C, wherein, Figure 1A is the schematic diagram of the circuit 1 that has on the thin film transistor base plate of one embodiment of the invention, Figure 1B is in the circuit 1 of Figure 1A, known a kind of circuit layout schematic diagram, and in the circuit 1 that Fig. 1 C is Figure 1A, the schematic diagram of the circuit layout of preferred embodiment of the present invention.
As shown in Figure 1A, circuit 1 comprises a first transistor T1 and a transistor seconds T2, and the first transistor T1 and transistor seconds T2 are respectively a thin film transistor (TFT), and is arranged on substrate (figure does not show).Wherein, the grid of the first transistor T1 and transistor seconds T2 is to be electrically connected to, and the drain electrode of the first transistor T1 and transistor seconds T2 is also electrically connected to.Therefore, while making the first transistor T1 and transistor seconds T2 conducting when grid input signal, the signal of the source electrode of the first transistor T1 can be sent to drain electrode, and the signal of the source electrode of transistor seconds T2 also can be sent to drain electrode.
In addition, shown in Fig. 1 C, thin film transistor base plate of the present invention comprises a substrate (figure does not show), a plurality of pixel electrode (figure does not show), a grid layer G, an active layers A, one first source layer S1, one second source layer S2 and a drain electrode layer D.
A plurality of pixel electrodes are arranged on substrate, and grid layer G is also arranged on substrate.Wherein, the material of grid layer G is for example the single or multiple lift structure that metal (for example aluminium, copper, silver, molybdenum, titanium) or its alloy form.Part drives the wire of signal in order to transmission, can use the structure with grid same layer and same processing procedure, is electrical connected each other, for example sweep trace (scan line).
Active layers A and grid layer G are oppositely arranged.On the implementation, active layers A can be semi-conductor layer, and such as but not limited to comprising monoxide semiconductor.Aforesaid oxide semiconductor comprises oxide, and oxide comprise indium, zinc, gallium and hafnium at least one of them, or other material.Wherein, oxide semiconductor is for example and without limitation to indium oxide gallium zinc, indium oxide hafnium zinc, zinc paste or indium oxide.
The first source layer S1 and the second source layer S2 contact with active layers A respectively, and drain electrode layer D also contacts with active layers A.Wherein, between the first source layer S1 and drain electrode layer D, there is an interval, and also there is an interval between the second source layer S2 and drain electrode layer D.In this, grid layer G, active layers A, the first source layer S1 and drain electrode layer D form the first transistor T1, and grid layer G, active layers A, the second source layer S2 and drain electrode layer D form transistor seconds T2.The present invention does not limit the first transistor T1 and transistor seconds T2 for the transistor of grid (top gate) on grid (bottom gate) or once.In the present embodiment, be that to take grid be example, active layers A is positioned on grid layer G.Wherein, in the active layers A of the first transistor T1, not during conducting, the first source layer S1 is electrically separated with drain electrode layer D.In addition, in the active layers A of transistor seconds T2, not during conducting, the second source layer S2 is also electrically separated with drain electrode layer D.
The first source layer S1 and the second source layer S2 are adjacent to drain electrode layer D.In other words, the first source layer S1 or the second source layer S2 can be positioned at the close position on upside, downside, left side or the right side of drain electrode layer D.In this, be that to take the arranged on left and right sides that the first source layer S1 and the second source layer S2 be positioned at drain electrode layer D be example.In addition, the first transistor T1 and transistor seconds T2 also can comprise respectively dielectric layer, insulation course, protective seam or other rete (figure does not show).Wherein, the material of the first source layer S1, the second source layer S2 and drain electrode layer D can be respectively the single or multiple lift structure that metal (for example aluminium, copper, silver, molybdenum, titanium) or its alloy form.Part drives the wire of signal in order to transmission, can use the structure with layer and same processing procedure, for example data line (data line) with the first source layer S1, the second source layer S2 and drain electrode layer D.
In addition, please refer to shown in Figure 1B, in known layout, because the grid of the first transistor T1 is electrically connected to the grid of transistor seconds T2, therefore the first transistor T1 and transistor seconds T2 have one deck grid layer G jointly.In addition, because the drain electrode of the first transistor T1 is electrically connected to the drain electrode of transistor seconds T2, therefore the first transistor T1 and transistor seconds T2 also have one deck drain electrode layer D jointly, but the one first active layers A1 of the first transistor T1 and the one second active layers A2 of transistor seconds T2 are separated from one another and be not connected.
But, shown in Fig. 1 C, in circuit layout of the present invention, the first transistor T1 and transistor seconds T2 have grid layer G jointly, the first transistor T1 and transistor seconds T2 also have drain electrode layer D jointly, but the first transistor T1 and transistor seconds T2 also have the active layers A of same layer.Wherein, on the projecting direction of thin film transistor base plate, active layers A and grid layer G overlap and arrange.Particularly, the present invention, in the processing procedure of active layers that forms the first transistor T1 and transistor seconds T2, is the active layers A that forms a region, and the active layers using this active layers A while as the first transistor T1 and transistor seconds T2.Therefore, the present invention will have the different thin-film transistor elements of same drain layer, and the mode by circuit layout integrates active layers, and then reduces the size of electric capacity, promotes by this component placement's efficiency under unit area.
In addition, in Fig. 1 C, the first transistor T1 and transistor seconds T2 close and during not conducting when input signal (grid G not), the first source layer S1 and the second source layer S2 be each other electrically absolutely from.In addition, drain electrode layer D of the present invention is one of them of these pixel electrodes that is electrically connected to thin film transistor base plate.In addition, grid layer G has a first area Z1, active layers A has a second area Z2, on the projecting direction of thin film transistor base plate, (overlook in direction), first area Z1 and second area Z2 overlap, and the size of first area Z1 (area) is the size (area) that is greater than second area Z2.
Please compare shown in Figure 1B and Fig. 1 C, in the layout of known Figure 1B, the area of the first active layers A1 and the second active layers A2 is 392 microns altogether
2, in the layout of Fig. 1 C of the present invention, the area of the second area Z2 that active layers A has only has 308 microns
2, than known 21.4% the layout area that reduced.Owing to can forming an electric capacity between two-layer conductive film layer, therefore, if can reduce the area of certain one deck conductive film layer, just can reduce overlapping area between the two, and then reduce stray capacitance and promote component placement's efficiency of unit area, the driving force of transistor unit area be can promote by this and delay and the distortion of the signal of display device reduced.Therefore, by the layout type of Fig. 1 C, the display device that can make thin film transistor base plate of the present invention and have this thin film transistor base plate reduces its stray capacitance, promotes component placement's efficiency of unit area, and then reduces delay and the distortion of signal.
In addition, please, respectively with reference to shown in Fig. 2 A and Fig. 2 B, it is respectively in the circuit 1 of Figure 1A, another schematic diagram of the circuit layout of preferred embodiment of the present invention.
As shown in Figure 2 A, different be main from Fig. 1 C, the first source layer S1 of Fig. 1 C and the second source layer S2 lay respectively at the arranged on left and right sides of drain electrode layer D, but in the layout of Fig. 2 A, the first source layer S1 and the second source layer S2 lay respectively at the right side of drain electrode layer D, and are upper right side and lower right side.In addition the area of the second area Z2 that, the active layers A of the present embodiment has only has 330 microns
2, than known 15.82% the active layers layout area that reduced of Figure 1B.
In addition, as shown in Figure 2 B, different be main from Fig. 2 A, the first source layer S1 of Fig. 2 B and the second source layer S2 lay respectively at upper left side and the lower right side of drain electrode layer D.In addition, the area of the second area Z2 that the active layers A of the present embodiment has only has 336 microns
2, than known 14.29% the active layers layout area that reduced.
In addition, the circuit layout of Fig. 2 A and Fig. 2 B can, with reference to above-mentioned Fig. 1 C, repeat no more.
In addition, please refer to shown in Fig. 3 A, Fig. 3 B and Fig. 3 C, wherein, Fig. 3 A is that another that have on thin film transistor base plate of the present invention implemented the schematic diagram of the circuit 1a of aspect, Fig. 3 B is in the circuit 1a of Fig. 3 A, known a kind of circuit layout schematic diagram, and Fig. 3 C is in the circuit 1a of Fig. 3 A, another schematic diagram of the circuit layout of preferred embodiment of the present invention.
Different be main from the circuit 1 of Figure 1A, the circuit 1a of Fig. 3 A more comprises one the 3rd transistor T 3, the grid of the 3rd transistor T 3 is electrically connected to the grid of the first transistor T1 and transistor seconds T2, and the source electrode of the 3rd transistor T 3 is electrically connected to the source electrode of the first transistor T1.
Therefore,, in the known layout of Fig. 3 B, grid layer G, one the 3rd active layers A3, one first source layer S1 and another drain electrode layer D1 form the 3rd transistor T 3.Wherein, the first transistor T1, transistor seconds T2 and the 3rd transistor T 3 have one deck grid layer G jointly, the first transistor T1 and transistor seconds T2 have one deck drain electrode layer D jointly, but the drain electrode layer D of the drain electrode layer D1 of the 3rd transistor T 3 and the first transistor T1 and transistor seconds T2 is separated and be not connected.In addition, first of the first transistor T1 the 3rd active layers A3 is initiatively separated from one another and do not connect.In addition, the 3rd active layers A3 and grid layer G overlap and arrange.
In the layout of the present invention of Fig. 3 C, grid layer G, active layers A, the first source layer S1 and drain electrode layer D1 form the 3rd transistor T 3, and the first transistor T1, transistor seconds T2 and the 3rd transistor T 3 are to have same layer active layers A.Particularly, the present invention is in the processing procedure of active layers that forms the first transistor T1, transistor seconds T2 and the 3rd transistor T 3, the active layers A that forms a region, and the active layers using this active layers A while as the first transistor T1, transistor seconds T2 and the 3rd transistor T 3.
The area summation of the first active layers A1 of known Fig. 3 B, the second active layers A2 and the 3rd active layers A3 is 539 microns
2, and in the layout of Fig. 3 C, the area of one the 4th region Z4 that active layers A has is 484 microns
2, therefore, comparable known Fig. 3 B has reduced by 10.2% active layers layout area.
In addition, please refer to shown in Fig. 4 A, Fig. 4 B and Fig. 4 C, wherein, Fig. 4 A is that another that have on thin film transistor base plate of the present invention implemented the schematic diagram of the circuit 1b of aspect, Fig. 4 B is in the circuit 1b of Fig. 4 A, known a kind of circuit layout schematic diagram, and Fig. 4 C is in the circuit 1b of Fig. 4 A, another schematic diagram of the circuit layout of preferred embodiment of the present invention.
Different be main from the circuit 1 of Figure 1A, the circuit 1b of Fig. 4 A more comprises that one the 3rd transistor T 3, the three transistor Ts 3 are arranged on substrate.Wherein, the grid of the 3rd transistor T 3 is electrically connected to the grid of the first transistor T1 and the grid of transistor seconds T2, and the drain electrode of the 3rd transistor T 3 is electrically connected to the drain electrode of the first transistor T1 and the drain electrode of transistor seconds T2.
In the known layout of Fig. 4 B, due to the grid of the first transistor T1, the grid of the grid of transistor seconds T2 and the 3rd transistor T 3 be electrically connected to, therefore the first transistor T1, transistor seconds T2 and the 3rd transistor T 3 have one deck grid layer G jointly.In addition, due to the drain electrode of the first transistor T1, the drain electrode of the drain electrode of transistor seconds T2 and the 3rd transistor T 3 be electrically connected to, therefore the first transistor T1, transistor seconds T2 and the 3rd transistor T 3 also have one deck drain electrode layer D jointly, but one the 3rd active layers A3 of the second active layers A2 of the first active layers A1, the transistor seconds T2 of the first transistor T1 and the 3rd transistor T 3 is separated from one another and do not connect.
But, in the layout of the present invention of Fig. 4 C, the first transistor T1, transistor seconds T2 and the 3rd transistor T 3 are jointly to have grid layer G, the first transistor T1, transistor seconds T2 and the 3rd transistor T 3 also have drain electrode layer D jointly, and the first transistor T1, transistor seconds T2 and the 3rd transistor T 3 also have the active layers A of same layer.Wherein, on the projecting direction of thin film transistor base plate, active layers A and grid layer G overlap and arrange.In addition, the drain electrode layer D of the first transistor T1, transistor seconds T2 and the 3rd transistor T 3 is one of them of these pixel electrodes of being electrically connected to thin film transistor base plate (figure does not show).In addition, when the first transistor T1, transistor seconds T2 and the 3rd transistor T 3 not conducting, the first source layer S1, the second source layer S2 and the 3rd source layer S3 are electrical isolation each other.In addition, grid layer G has one the 3rd region Z3, and active layers A has one the 4th region Z4, and on the projecting direction of thin film transistor base plate, the 3rd region Z3 and the 4th region Z4 overlap, and the size of the 3rd region Z3 is the size that is greater than the 4th region E4.
In addition, the area summation of the first active layers A1 of Fig. 4 B, the second active layers A2 and the 3rd active layers A3 is 588 microns
2.In the layout of Fig. 4 C, the area of the 4th region Z4 of active layers A is 426 microns
2, therefore, comparable known 27.55% the active layers layout area that reduced.
In addition, please refer to shown in Fig. 5 A, Fig. 5 B and Fig. 5 C, wherein, Fig. 5 A is that another that have on thin film transistor base plate of the present invention implemented the schematic diagram of the circuit 1c of aspect, Fig. 5 B is in the circuit 1c of Fig. 5 A, known a kind of circuit layout schematic diagram, and Fig. 5 C is in the circuit 1c of Fig. 5 A, another schematic diagram of the circuit layout of preferred embodiment of the present invention.
From the circuit 1b of Fig. 4 A different being initiatively, the circuit 1c of Fig. 5 A more comprises that one the 4th transistor T 4, the four transistor Ts 4 are arranged on substrate.Wherein, the grid of the 4th transistor T 4 is electrically connected to the grid of the grid of the first transistor T1, the grid of transistor seconds T2 and the 3rd transistor T 3, and the drain electrode of the 4th transistor T 4 is electrically connected to the drain electrode of the drain electrode of the first transistor T1, the drain electrode of transistor seconds T2 and the 3rd transistor T 3.
In the known layout of Fig. 5 B, the first transistor T1, transistor seconds T2, the 3rd transistor T 3 and the 4th transistor T 4 have one deck grid layer G jointly.In addition, the first transistor T1, transistor seconds T2, the 3rd transistor T 3 and the 4th transistor T 4 also have one deck drain electrode layer D jointly, but the second active layers A2 of the first active layers A1, the transistor seconds T2 of the first transistor T1 is, one the 4th active layers A4 of the 3rd active layers A3 of the 3rd transistor T 3 and the 4th transistor T 4 is separated from one another and do not connect.
But, in the layout of the present invention of Fig. 5 C, the first transistor T1, transistor seconds T2, the 3rd transistor T 3 and the 4th transistor T 4 have grid layer G jointly, the first transistor T1, transistor seconds T2, the 3rd transistor T 3 and the 4th transistor T 4 also have drain electrode layer D jointly, and the first transistor T1, transistor seconds T2, the 3rd transistor T 3 and the 4th transistor T 4 also have the active layers A of same layer.Wherein, on the projecting direction of thin film transistor base plate, active layers A and grid layer G overlap and arrange.In addition, the drain electrode layer D of the first transistor T1, transistor seconds T2, the 3rd transistor T 3 and the 4th transistor T 4 is one of them of these pixel electrodes of being electrically connected to thin film transistor base plate (figure does not show).In addition, when the first transistor T1, transistor seconds T2, the 3rd transistor T 3 and the 4th transistor T 4 not conducting, the first source layer S1, the second source layer S2, the 3rd source layer S3 and the 4th source layer S4 are electrical isolation each other.In addition, grid layer G has one the 5th region Z5, and active layers A has one the 6th region Z6, and on the projecting direction of thin film transistor base plate, the 5th region Z5 and the 6th region Z6 overlap, and the size of the 5th region Z5 is the size that is greater than the 6th region E6.
In addition, the area summation of the first active layers A1 of Fig. 5 B, the second active layers A2, the 3rd active layers A3 and the 4th active layers A4 is 784 microns
2, in the layout of Fig. 4 C, the area of the 6th region Z6 of active layers A is 528 microns
2, than known 32.65% the active layers layout area that reduced of Fig. 5 B.
In addition, display device of the present invention has above-mentioned thin film transistor base plate, and the mode of the circuit layout of thin film transistor base plate can, with reference to above-mentioned, repeat no more.Wherein, display device can be a liquid crystal indicator or an organic light emitting diode display device.Take liquid crystal indicator as example, and except thin film transistor base plate, liquid crystal indicator more can comprise a subtend substrate, a liquid crystal layer and a backlight module.Subtend substrate is relative with thin film transistor base plate and establish, and liquid crystal layer is folded between thin film transistor base plate and subtend substrate.In addition, backlight module is arranged at thin film transistor base plate away from a side of subtend substrate.
What last was carried is, the present invention will have the different thin-film transistor elements of same drain layer, mode by layout integrates active layers, and then the size of minimizing electric capacity, to promote the component placement's efficiency under unit area, therefore, do not limit the display device of only having above-mentioned circuit to come across thin film transistor base plate and thering is this thin film transistor base plate, as long as meet the display device that the circuit of this concept and layout type thereof all can be covered by thin film transistor base plate of the present invention and have this thin film transistor base plate.
In sum, in thin film transistor base plate of the present invention and display device, grid layer and active layers are oppositely arranged, and the first source layer and the second source layer contact with active layers respectively, drain electrode layer contacts with active layers, and is electrically connected to one of them of these pixel electrodes.In addition, grid layer, active layers, the first source layer and drain electrode layer are to form a first transistor, and grid layer, active layers, the second source layer and drain electrode layer are to form a transistor seconds.In addition,, when the first transistor and transistor seconds are closed, the first source layer and the second source layer are to be electrically insulated.Because the present invention will have the different thin-film transistor elements of same drain layer, mode by layout integrates active layers, therefore can reduce the area of the first transistor and the formed active layers of transistor seconds, and then reduce the overlapping area between grid layer and active layers and reduce the size of electric capacity.Therefore, by the present invention, the display device that can make thin film transistor base plate and have this thin film transistor base plate reduces its parasitic capacitance, promotes component placement's efficiency of unit area, and then promotes the driving force of transistor unit area and reduce delay and the distortion of signal.
The foregoing is only illustrative, but not be restricted person.Anyly do not depart from spirit of the present invention and category, and the equivalent modifications that it is carried out or change all should be contained in claim.
Claims (10)
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| CN107300816B (en) | 2021-04-16 |
| CN104142594B (en) | 2017-06-06 |
| CN107300816A (en) | 2017-10-27 |
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