CN108461504B - Layout structure of transistor, pixel driving circuit, array substrate and display device - Google Patents
Layout structure of transistor, pixel driving circuit, array substrate and display device Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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- H—ELECTRICITY
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract
本发明公开了一种晶体管的版图结构、像素驱动电路、阵列基板和显示装置，该版图结构包括电路节点以及与电路节点连接的有源层；有源层包括第一有源层、第二有源层以及第三有源层；与第一有源层相连的第一源极，与第二有源层相连的漏极，与第三有源层相连的第二源极；分别与第一有源层、第二有源层和第三有源层对应的第一栅极、第二栅极和第三栅极；第一栅极、第二栅极以及第三栅极组成的栅极图案位于电路节点和有源层的上方。本发明实施例，三个晶体管的栅极组成同一个图形，两个晶体管的漏极和第三个晶体管的源极连接在一起形成的电路节点位于栅极图形之下，通过这种设计可以缩小三个晶体管的版图面积，降低版图设计难度，提高应用范围。
The invention discloses a layout structure of a transistor, a pixel driving circuit, an array substrate and a display device. The layout structure includes a circuit node and an active layer connected to the circuit node; the active layer includes a first active layer, a second active layer and a second active layer. an active layer and a third active layer; a first source electrode connected to the first active layer, a drain electrode connected to the second active layer, and a second source electrode connected to the third active layer; respectively connected to the first source electrode The first gate, the second gate and the third gate corresponding to the active layer, the second active layer and the third active layer; the gate composed of the first gate, the second gate and the third gate Patterns are placed over circuit nodes and active layers. In the embodiment of the present invention, the gates of the three transistors form the same pattern, and the circuit node formed by connecting the drains of the two transistors and the source of the third transistor together is located under the gate pattern. The layout area of the three transistors reduces the difficulty of layout design and increases the scope of application.
Description
Technical Field
The invention relates to the technical field of display, in particular to a layout structure of a transistor, a pixel driving circuit, an array substrate and a display device.
Background
An Active Matrix/Organic Light Emitting Diode (AMOLED) display is one of the hot spots in the field of display research. Compared with a liquid crystal display, an Organic Light Emitting Diode (OLED) has the advantages of low energy consumption, low production cost, self-luminescence, wide viewing angle, fast response speed, and the like.
In the process of implementing the invention, the inventor finds that the prior art has the following problems: for an AMOLED display product, the number of driving thin film transistors in a pixel driving circuit is large, the occupied area or space in layout design is large, and the product design with high pixel density (Pixels Per Inc, PPI) is influenced.
Disclosure of Invention
The invention mainly aims to provide a layout structure of a transistor, a pixel driving circuit, an array substrate and a display device, and aims to solve the problems in the prior art.
In order to achieve the above object, a first aspect of an embodiment of the present invention provides a layout structure of a transistor, where the layout structure includes a circuit node and an active layer connected to the circuit node; the active layer includes a first active layer, a second active layer, and a third active layer;
a first source electrode connected to the first active layer, a drain electrode connected to the second active layer, and a second source electrode connected to the third active layer;
a first gate electrode, a second gate electrode, and a third gate electrode corresponding to the first active layer, the second active layer, and the third active layer, respectively; and a gate pattern composed of the first gate electrode, the second gate electrode and the third gate electrode is positioned above the circuit node and the active layer.
With reference to the first aspect of the embodiment of the present invention, in a first implementation manner of the first aspect of the embodiment of the present invention, the first active layer and the third active layer form an inverted "U" shaped structure; the second active layer forms an inverted 'L' shaped structure.
With reference to the first aspect of the embodiments, in a second implementation manner of the first aspect of the embodiments, the first active layer and the second active layer constitute
A type structure; the third active layer forms an inverted 'L' shaped structure.
With reference to the first aspect of the embodiment of the present invention, in a third implementation manner of the first aspect of the embodiment of the present invention, the first active layer and the second active layer form an "n" type structure; the third active layer forms an inverted 'L' shaped structure.
With reference to the first aspect of the embodiment of the present invention, in a fourth implementation manner of the first aspect of the embodiment of the present invention, a gate pattern formed by the first gate, the second gate, and the third gate is square or polygonal.
In combination with the fourth implementation manner of the first aspect of the embodiment of the present invention, the square shape includes a square or a rectangle.
Further, to achieve the above object, a second aspect of embodiments of the present invention provides a pixel driving circuit including a first driving transistor, a second driving transistor, and a first switching transistor; the layout structure formed by the first driving transistor, the second driving transistor and the first switch transistor is the layout structure.
In combination with the second aspect of the embodiment of the present invention, in the first implementation manner of the second aspect of the embodiment of the present invention, the width-to-length ratio W1/L1 of the first driving transistor, the width-to-length ratio W2/L2 of the second driving transistor, and the width-to-length ratio W3/L3 of the first switching transistor satisfy the following relationships:
w1 ═ W2 ═ W3, L1/L2 ═ 1, L3< L2; or
W1 ═ W2 ═ W3, L1/L2>1, L3< L2; or
W1 ═ W2 ═ W3, L1/L2<1, L3< L2; or
W1 ═ W2< W3, L1/L2 ═ 1 or L1/L2>1 or L1/L2<1, L3< L2; or
W1 ═ W2> W3, L1/L2 ═ 1 or L1/L2>1 or L1/L2<1, L3< L2.
In addition, to achieve the above object, a third aspect of the embodiments of the present invention provides an array substrate, including the above pixel driving circuit.
In order to achieve the above object, a fourth aspect of the embodiments of the invention provides a display device, which includes the array substrate.
According to the layout structure of the transistors, the pixel driving circuit, the array substrate and the display device, the grids of the three transistors form the same graph, and the drain electrodes of the two transistors and the source electrode of the third transistor are connected together to form a circuit node which is positioned below the grid graph.
Drawings
Fig. 1 is a schematic diagram of a layout structure of a transistor according to an embodiment of the present invention;
fig. 2 is another schematic diagram of a layout structure of a transistor according to an embodiment of the present invention;
fig. 3 is another schematic diagram of the layout structure of the transistor according to the embodiment of the present invention;
fig. 4 is a schematic structural diagram of a pixel driving circuit using a layout structure of a transistor according to an embodiment of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Embodiments of the invention will now be described with reference to the accompanying drawings, in the following description, suffixes such as "module", "part", or "unit" used to denote elements are used only for facilitating the description of the invention, and are not particularly meaningful in themselves.
The switching transistor and the driving transistor used in all the embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics, and since the source and the drain of the switching transistor used herein are symmetrical, the source and the drain may be interchanged. In the embodiment of the present invention, in order to distinguish two poles of the transistor except for the gate, one of the two poles is referred to as a source, and the other pole is referred to as a drain. In the form of the drawing, the control terminal of the transistor is defined as a gate, the first terminal is defined as a source, and the second terminal is defined as a drain. In addition, the switching transistor used in the embodiment of the present invention includes two types, i.e., a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level and turned off when the gate is at a high level, and the N-type switching transistor is turned on when the gate is at a high level and turned off when the gate is at a low level.
It should be noted that, in the drawings, all of the switching transistors and the driving transistors of the pixel driving circuit are P-channel transistors, and those skilled in the art can easily find that the pixel driving circuit provided by the present invention can be easily changed into a pixel driving circuit that is all N-channel transistors.
As shown in fig. 1, a first embodiment of the present invention proposes a layout structure of a transistor, which includes a circuit node 10 and an active layer connected to the circuit node 10.
In the present embodiment, the active layers include a first active layer 21, a second active layer 22, and a third active layer 23.
Referring to fig. 1, in one possible embodiment, the first active layer 21 and the third active layer 23 form an inverted "U" shape; the second active layer 22 constitutes an inverted "L" type structure.
Referring to fig. 2, in another possible embodiment, the first active layer 21 and the second active layer 22 are formed
A type structure; the third active layer 23 constitutes an inverted "L" type structure.
Referring to fig. 3, in another possible embodiment, the first active layer 21 and the second active layer 22 form an "n" type structure; the third active layer 23 constitutes an inverted "L" type structure.
Connected to the first active layer 21 is a first source electrode 31, connected to the second active layer 22 is a drain electrode 32, and connected to the third active layer 23 is a second source electrode 33.
Further includes first, second, and third gate electrodes (not shown) corresponding to the first, second, and third active layers 21, 22, and 23, respectively; a gate pattern 40 of the first gate, the second gate, and the third gate is positioned above the circuit node 10 and the active layer.
Referring to fig. 1-3, in the present embodiment, the gate pattern 40 is substantially square, such as square or rectangle; the grid pattern can also be a polygon, namely a planar graph formed by sequentially connecting more than four line segments end to end.
Referring to fig. 1 again, the active layer covered by the gate pattern 40 is a channel region, the active layer 211 (shown by a dashed line) of the first active layer 21 covered by the gate pattern 40 is a first channel, the active layer 221 (shown by a dashed line) of the second active layer 22 covered by the gate pattern 40 is a second channel, and the active layer 231 (shown by a dashed line) of the third active layer 23 covered by the gate pattern 40 is a third channel.
The first source electrode 31, the first active layer 21 and the circuit node 10 may form a channel through which a current flows; the second source electrode 33, the third active layer 23 and the circuit node 10 may form a channel through which a current flows; the circuit node 10, the second active layer 22, and the drain electrode 32 may form a channel through which current flows. Therefore, the layout structure is equivalent to a layout composed of three transistors, namely: wherein the drains of the two transistors and the source of the third transistor are connected together to form a circuit node, and the gates of the three transistors are connected together.
It should be noted that the layout structure of the transistor provided in the embodiment of the present invention is not only suitable for a transistor with a bottom gate structure, but also suitable for a transistor with a top gate structure.
The manufacturing process of the transistors with the top gate structure and the bottom gate structure is different. The top gate structure manufacturing process flow is as follows:
s1: depositing a buffer layer and an active layer and patterning the active layer;
s2: depositing a grid insulating layer and a grid metal layer and patterning the grid metal layer;
s3: transistor source drain P+And (4) doping.
The manufacturing process flow of the bottom gate structure is as follows:
s10, depositing a buffer layer and a gate metal layer and patterning the gate metal layer;
s11, depositing a gate insulating layer and an active layer and patterning the active layer;
s12, coating and patterning the doping barrier layer, and forming a TFT source and drain electrode P+Doping;
and S13, stripping the gate barrier layer.
According to the layout structure of the transistor, the layout structure of the transistor is equivalent to the fact that the grids of the three transistors form the same graph, and the circuit node formed by connecting the drains of the two transistors and the source of the third transistor is located below the grid graph.
A second embodiment of the present invention provides a pixel driving circuit including a first driving transistor, a second driving transistor, and a first switching transistor; the layout structure formed by the first driving transistor, the second driving transistor and the first switch transistor is the layout structure.
In the present embodiment, the width-to-length ratio W1/L1 of the first driving transistor, the width-to-length ratio W2/L2 of the second driving transistor, and the width-to-length ratio W3/L3 of the first switching transistor satisfy the following relationships:
w1 ═ W2 ═ W3, L1/L2 ═ 1, L3< L2; or
W1 ═ W2 ═ W3, L1/L2>1, L3< L2; or
W1 ═ W2 ═ W3, L1/L2<1, L3< L2; or
W1 ═ W2< W3, L1/L2 ═ 1 or L1/L2>1 or L1/L2<1, L3< L2; or
W1 ═ W2> W3, L1/L2 ═ 1 or L1/L2>1 or L1/L2<1, L3< L2.
It should be noted that the aspect ratio W1/L1 of the first driving transistor, the aspect ratio W2/L2 of the second driving transistor, and the aspect ratio W3/L3 of the first switching transistor are not limited to the above-mentioned cases, and the aspect ratio designs of the pixel driving circuit according to the embodiment of the present invention are all within the protection scope of the present patent.
As an example, please see fig. 4, the pixel driving circuit of fig. 4 includes a first driving transistor D1, a second driving transistor D2, and a fourth switching transistor T4 (shown by a dashed box). A second terminal (drain) of the first driving transistor D1, a second terminal (drain) of the fourth switching transistor T4, and a first terminal (source) of the second driving transistor D2 are connected together to form a circuit node; the gates of the first driving transistor D1, the second driving transistor D2 and the fourth switching transistor T4 are connected together, and the layout structure thereof is designed as described above.
According to the pixel driving circuit provided by the embodiment of the invention, the grids of the three transistors form the same graph, and the circuit node formed by connecting the drains of the two transistors and the source of the third transistor is positioned below the grid graph.
The present invention further provides an array substrate, comprising:
data signal lines extending along the columns;
a plurality of control signal lines and driving signal lines extending along the rows;
a plurality of pixels arranged in a matrix at intersections of the data signal lines and the control signal lines;
the pixel includes the pixel driving circuit described above.
According to the array substrate provided by the embodiment of the invention, the gates of the three transistors form the same pattern, and the circuit node formed by connecting the drains of the two transistors and the source of the third transistor is positioned below the gate pattern.
The present invention further provides a display device comprising: the array substrate is provided. In addition, the display device can also be electronic paper, a mobile phone, a television, a digital photo frame and other display equipment.
According to the display device provided by the embodiment of the invention, the grids of the three transistors form the same graph, and the drain electrodes of the two transistors and the source electrode of the third transistor are connected together to form a circuit node which is positioned below the grid graph.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A layout structure of a transistor is characterized in that the layout structure comprises a circuit node and an active layer connected with the circuit node; the active layer includes a first active layer, a second active layer, and a third active layer;
a first source electrode connected to the first active layer, a drain electrode connected to the second active layer, and a second source electrode connected to the third active layer;
a first gate electrode, a second gate electrode, and a third gate electrode corresponding to the first active layer, the second active layer, and the third active layer, respectively; a gate pattern composed of the first gate electrode, the second gate electrode, and the third gate electrode is located above the circuit node and the active layer;
wherein the circuit node is connected to the first active layer and the third active layer as a drain and to the second active layer as a source.
2. The layout structure of a transistor according to claim 1, wherein the first active layer and the third active layer constitute an inverted "U" shaped structure; the second active layer forms an inverted 'L' shaped structure.
3. A transistor layout structure as claimed in claim 1, wherein said first active layer and said second active layer constitute
A type structure; the third active layer forms an inverted 'L' shaped structure.
4. The layout structure of a transistor according to claim 1, wherein the first active layer and the second active layer constitute an "n" type structure; the third active layer forms an inverted 'L' shaped structure.
5. The transistor layout structure of claim 1, wherein a gate pattern formed by the first gate, the second gate, and the third gate is square or polygonal.
6. A transistor layout structure as claimed in claim 5, wherein said square shape comprises a square or a rectangle.
7. A pixel driving circuit, comprising a first driving transistor, a second driving transistor, and a first switching transistor; the layout structure formed by the first driving transistor, the second driving transistor and the first switching transistor is the layout structure according to any one of claims 1 to 5.
8. The pixel driving circuit according to claim 7, wherein the width-to-length ratio W1/L1 of the first driving transistor, the width-to-length ratio W2/L2 of the second driving transistor, and the width-to-length ratio W3/L3 of the first switching transistor satisfy the following relationships:
w1 ═ W2 ═ W3, L1/L2 ═ 1, L3< L2; or
W1 ═ W2 ═ W3, L1/L2>1, L3< L2; or
W1 ═ W2 ═ W3, L1/L2<1, L3< L2; or
W1 ═ W2< W3, L1/L2 ═ 1 or L1/L2>1 or L1/L2<1, L3< L2; or
W1 ═ W2> W3, L1/L2 ═ 1 or L1/L2>1 or L1/L2<1, L3< L2.
9. An array substrate comprising the pixel driving circuit according to any one of claims 7 to 8.
10. A display device comprising the array substrate according to claim 9.
Priority Applications (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710095713.4A CN108461504B (en) | 2017-02-22 | 2017-02-22 | Layout structure of transistor, pixel driving circuit, array substrate and display device |
| PCT/CN2018/076788 WO2018153336A1 (en) | 2017-02-22 | 2018-02-14 | Pixel driving circuit and driving method thereof, and layout structure of transistor |
| TW107105392A TWI649739B (en) | 2017-02-22 | 2018-02-14 | Pixel driving circuit, driving method and layout structure of transistor |
| EP18757819.0A EP3588480B1 (en) | 2017-02-22 | 2018-02-14 | Pixel driving circuit and driving method thereof, and layout structure of transistor |
| KR1020197019778A KR102209416B1 (en) | 2017-02-22 | 2018-02-14 | Pixel driving circuit, driving method thereof, and layout structure of transistor |
| TW107141318A TWI696990B (en) | 2017-02-22 | 2018-02-14 | Pixel driving circuit, driving method and layout structure of transistor |
| US16/324,549 US10692432B2 (en) | 2017-02-22 | 2018-02-14 | Pixel driving circuit and driving method thereof, and layout structure of transistor |
| JP2019537159A JP7198206B2 (en) | 2017-02-22 | 2018-02-14 | PIXEL DRIVE CIRCUIT, DRIVING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE |
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| CN201710095713.4A CN108461504B (en) | 2017-02-22 | 2017-02-22 | Layout structure of transistor, pixel driving circuit, array substrate and display device |
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| CN111383580B (en) * | 2018-12-29 | 2021-06-08 | 上海和辉光电股份有限公司 | Pixel compensation circuit layout structure and virtual reality display device |
| CN110085677B (en) * | 2019-03-18 | 2022-04-12 | 昆山国显光电有限公司 | Driving transistor, array substrate and display panel |
| CN110412800B (en) * | 2019-07-25 | 2021-02-26 | 深圳市华星光电半导体显示技术有限公司 | Pixel structure and display panel adopting same |
| CN110491334B (en) * | 2019-08-30 | 2021-07-23 | 上海中航光电子有限公司 | Pixel circuit, driving method of pixel circuit, display panel and display device |
| US11751450B2 (en) | 2020-08-31 | 2023-09-05 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display panel and display device |
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| CN201893343U (en) * | 2010-12-15 | 2011-07-06 | 四川虹视显示技术有限公司 | TFT structure for cross-shaped grid of pixel circuit of organic luminescent device |
| CN104142594A (en) * | 2013-05-10 | 2014-11-12 | 群创光电股份有限公司 | Thin film transistor substrate and display device |
| CN103915510A (en) * | 2014-03-27 | 2014-07-09 | 京东方科技集团股份有限公司 | Multi-gate thin-film transistor, array substrate and display device |
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