CN104103507A - Manufacturing technology of synchronously etching floating gate - Google Patents

Abstract

The invention provides a manufacturing process for synchronous etching of floating gates, comprising: sequentially oxidizing a working area to generate a tunnel oxide layer and depositing and doping polysilicon; depositing a protective layer on the doped polysilicon; Set the pattern to etch the doped polysilicon to form a shallow insulating trench; deposit a first oxide film on the surface of the shallow insulating trench; oxidize the first oxide film at high temperature to form a second oxide film; Filling the insulating trench with oxide; using chemical mechanical planarization to remove the oxide beyond the protective layer in the shallow insulating trench; removing the protective layer; etching the oxide according to a second preset pattern. The invention is used to optimize the design process, simplify the manufacturing process and save the manufacturing cost.

Description

A Manufacturing Process of Simultaneously Etching Floating Gates

technical field

The invention relates to the technical field of semiconductors, in particular to a process for synchronously etching floating gates.

Background technique

The previous and current NOR flash memory (NOR Flash) all use the self-aligned floating gate manufacturing process (Self-align Poly Process) to make the floating gate (Floating Gate), the method of this self-aligned floating gate manufacturing process There are three major disadvantages:

First, in the self-aligned floating gate manufacturing process, it is necessary to use chemical mechanical planarization to grind away a certain amount of polysilicon (Poly CMP), so that the floating gate polysilicon (Floating gate poly) shallow insulation trench oxide (STI Oxide) ) are exposed, thereby self-aligning to form a floating gate. The Poly CMP manufacturing process is a process in which the flatness of the thickness from the center of the wafer to the edge cannot be well controlled. If the height of the floating gate at the center of the wafer is different from that at the edge of the wafer, the manufactured There are deviations in the electrical characteristics of the flash memory unit (Flash Cell), which affects the quality of the product and the consistency of the electrical characteristics.

Second, referring to the schematic structural diagram of a floating gate manufactured by a self-alignment process shown in Figure 1, the floating gate made by a self-aligned floating gate manufacturing process is to protrude out of the working area (Active Area, referred to as AA), That is, a larger floating gate will be placed on the smaller working area, which will inevitably cause some edge parts of the larger floating gate to be supported by the working area below, so that the tunnel oxide layer (Tunneloxide) is in the center of the working area Normal, but since the tunnel oxide layer will become thinner at the rounded corners beyond the range of the working area, the requirements for the rounded corners of the working area will be stricter, otherwise leakage will easily occur.

Third, also referring to Figure 1, the interface between the floating gate and the shallow insulating trench (STI) made by the self-aligned floating gate manufacturing process, and then the memory cell open etching (Cell Open Etch) needs to remove a part of the shallow The oxide (STI Oxide) in the insulation trench, but the structure with small holes and large holes will cause certain difficulties to the subsequent open etching process of the unit.

Therefore, one of the problems urgently needed to be solved by those skilled in the art is to propose a manufacturing process for simultaneously etching floating gates, so as to optimize the design process, simplify the manufacturing process, and save manufacturing costs.

Contents of the invention

The technical problem to be solved by the present invention is to provide a manufacturing process for synchronous etching of floating gates, which is used to optimize the design process, simplify the manufacturing process, and save manufacturing costs.

In order to solve the above problems, the present invention discloses a manufacturing process for simultaneously etching floating gates, including:

Sequentially oxidize the working area to generate a tunnel oxide layer and deposit polysilicon and doping;

depositing a protective layer on the doped polysilicon;

Etching the doped polysilicon according to a first preset pattern to form shallow insulating trenches;

Depositing a first oxide film on the surface of the shallow insulation trench;

Oxidizing the first oxide film at high temperature to form a second oxide film;

Filling the shallow insulation trench with oxide;

removing the oxide beyond the protection layer in the shallow insulation trench by chemical mechanical planarization;

removing said protective layer;

The oxide is etched according to a second preset pattern.

Preferably, before the step of etching the doped polysilicon according to the first preset pattern to form shallow insulation trenches, and before the step of etching the oxide according to the second preset pattern ,Also includes:

Depositing amorphous carbon and an anti-reflection layer sequentially on the protective layer, and covering photoresist on the amorphous carbon and anti-reflection layer;

A preset pattern is photolithographically etched on the photoresist.

Preferably, after the step of etching the doped polysilicon according to the first preset pattern to form shallow insulation trenches, and after the step of etching the oxide according to the second preset pattern ,Also includes:

The photoresist is removed by a dry method and a wet method in sequence.

Preferably, the step of etching the oxide according to the second preset pattern is:

The oxide is etched according to the second predetermined pattern by using dry method and wet method sequentially.

Preferably, after the step of filling the shallow insulating trench with oxide, further include:

uniform distribution of the oxide;

The step of uniformly distributing the oxide comprises:

raising the temperature of the oxide to a preset temperature;

Return the temperature of the oxide to normal temperature.

Preferably, the step of depositing polysilicon and doping includes:

depositing polysilicon on the working area, and cleaning the surface of the polysilicon after deposition;

The polysilicon is doped with impurities.

Preferably, after the step of sequentially oxidizing the working area to generate a tunnel oxide layer and depositing and doping polysilicon, it further includes:

uniformly distributing said doped polysilicon;

The step of uniformly distributing the doped polysilicon includes:

raising the temperature of the doped polysilicon to a preset temperature;

Return the temperature of the doped polysilicon to normal temperature.

Preferably, after the step of etching the doped polysilicon according to the first preset pattern to form shallow insulating trenches, further comprising:

Cleaning the surface of the shallow insulation trench.

Preferably, the side section of the shallow insulation trench is wide at the top and narrow at the bottom.

Compared with the prior art, the present invention includes the following advantages:

First of all, by using one-step etching of the floating gate and the working area, the floating gate is aligned with the edge of the working area, avoiding the wafer center-to-edge thickness that may be caused by the chemical-mechanical planarization process that grinds away a certain amount of crystalline silicon. The problem of unevenness has optimized the manufacturing process of the floating gate. Secondly, since the floating gate is etched by one-step etching of the floating gate and the working area, and the cross-sectional structure of the etched shallow insulating trench is wide at the top and narrow at the bottom, it is easy to perform subsequent open etching of the memory cell. Thirdly, because the present invention adopts an excellent manufacturing sequence, the manufacturing process is simpler, the manufacturing process is simplified, and the manufacturing cost is saved.

Description of drawings

Fig. 1 is a structural schematic diagram of a floating gate fabricated by a self-alignment process;

Fig. 2 is a flow chart of steps of a manufacturing process embodiment of a synchronous etching floating gate of the present invention;

Fig. 3 is a cross-sectional view of a manufacturing process 1-5 of a floating gate of the present invention;

Fig. 4 is a cross-sectional view of a manufacturing process 6-11 of a floating gate of the present invention;

5 is a sectional view of a manufacturing process 12-13 of a floating gate of the present invention;

FIG. 6 is a cross-sectional view of a manufacturing process 14 of a floating gate of the present invention;

7 is a cross-sectional view of a manufacturing process 15-16 of a floating gate of the present invention;

FIG. 8 is a cross-sectional view of a manufacturing process 17 of a floating gate of the present invention;

FIG. 9 is a cross-sectional view of a manufacturing process 18 of a floating gate of the present invention;

FIG. 10 is a cross-sectional view of a manufacturing process 19-23 of a floating gate according to the present invention.

Detailed ways

In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

One of the core concepts of the embodiments of the present invention is to adopt an excellent process sequence, and to align the floating gate with the edge of the working area by one-step etching of the floating gate and the working area, avoiding the need for multiple chemical mechanical planarization The problem of uneven thickness from the center to the edge of the wafer that may be caused by the manufacturing process of dropping a certain amount of crystalline silicon optimizes the manufacturing process of the floating gate.

Referring to FIG. 2 , it shows a flow chart of steps of a manufacturing process embodiment of a simultaneous etching floating gate of the present invention, which may specifically include the following steps:

Step 101, sequentially oxidizing the working area to generate a tunnel oxide layer and depositing polysilicon and doping;

In a preferred embodiment of the present invention, the steps of sequentially oxidizing the working area to generate a tunnel oxide layer and depositing polysilicon and doping may specifically include the following sub-steps:

Sub-step S11, forming a tunnel oxide layer and depositing polysilicon on the working area, and cleaning the surface of the polysilicon after deposition;

Sub-step S12, doping the polysilicon with impurities.

In a preferred embodiment of the present invention, after step 101, the following steps may also be included:

uniformly distributing said doped polysilicon;

Wherein, the step of uniformly distributing the doped polysilicon may include the following sub-steps:

Sub-step S21, raising the temperature of the doped polysilicon to a preset temperature;

Sub-step S21, returning the temperature of the doped polysilicon to normal temperature.

Step 102, depositing a protective layer on the doped polysilicon;

Referring to the cross-sectional view of a floating gate manufacturing process 1-5 shown in Figure 3, firstly, the tunnel oxide layer (Tunnel oxide) is sequentially oxidized on the working area and polysilicon (FG POLY) is deposited and doped, wherein, the doped The final polysilicon has better conductivity, and then a protective layer (FGHM) is deposited on the doped polysilicon, which can be used to protect the polysilicon. Preferably, after the polysilicon is deposited, the surface of the deposited polysilicon can be cleaned to remove dirt and avoid affecting the electrical characteristics of the manufactured floating gate, and then the polysilicon can be doped with impurities.

After the polysilicon is deposited and doped, the doped polysilicon can be raised to a predetermined temperature, so that the impurities can be evenly distributed in the polysilicon. After the temperature is raised for a period of time, the temperature of the doped polysilicon is returned to normal temperature.

Step 103, etching the doped polysilicon according to the first preset pattern to form shallow insulating trenches;

In a preferred embodiment of the present invention, before the step 103, the following steps may also be included:

Depositing amorphous carbon and an anti-reflection layer sequentially on the protective layer, and covering photoresist on the amorphous carbon and anti-reflection layer;

A preset pattern is photolithographically etched on the photoresist.

In a preferred embodiment of the present invention, after the step 103, the following steps may also be included:

The photoresist is removed by a dry method and a wet method in sequence.

Referring to the cross-sectional view of a floating gate manufacturing process 6-11 shown in Figure 4, on the basis of depositing polysilicon and doping, and depositing a protective layer, sequentially deposit amorphous carbon and an anti-reflection layer, and then cover A layer of photoresist, photoetching the first preset pattern on the photoresist, and then etching the polysilicon according to the first preset pattern to form a shallow insulation trench. After the etching is completed, the dry method and the The photoresist is wet removed. Preferably, the side section of the shallow insulation trench formed by etching is wide at the top and narrow at the bottom, which is beneficial for filling and etching the oxide in subsequent processes.

Step 104, depositing a first oxide film on the surface of the shallow insulation trench;

Referring to the cross-sectional view of a floating gate manufacturing process 12-13 of the present invention shown in FIG. 5, after the shallow insulating trench is formed by etching, preferably, the surface of the shallow insulating trench can also be cleaned to remove dirt. Then deposit a first oxide film (HARP) on the surface of the shallow insulation trench to improve the stability of the manufactured floating gate.

Step 105, high temperature oxidation of the first oxide film to form a second oxide film;

Referring to the cross-sectional view of a floating gate manufacturing process 14 of the present invention shown in FIG. 6, the first oxide film that has been deposited on the surface of the shallow insulation trench can be oxidized at a high temperature to form a second oxide film. Preferably, during the high temperature oxidation process, the frizz of the oxide film can be removed, and the electrical characteristics of the manufactured floating gate can be stabilized.

Step 106, filling oxide in the shallow insulation trench;

In a preferred embodiment of the present invention, after the step 106, the following steps may also be included:

uniform distribution of the oxide;

The step of uniformly distributing the oxide may include the following sub-steps:

raising the temperature of the oxide to a preset temperature;

Return the temperature of the oxide to normal temperature.

Referring to FIG. 7 , which is a cross-sectional view of a floating gate manufacturing process 15-16 of the present invention, the shallow insulating trench where the second oxide film is formed is filled with oxide (HARP). After filling the oxide, it can also be raised to a certain preset temperature for the oxide so that the oxide can be evenly distributed. After the temperature has been raised for a period of time, the temperature of the oxide is returned to normal temperature.

Step 107, using chemical mechanical planarization to remove the oxide beyond the protection layer in the shallow insulation trench;

Referring to the cross-sectional view of a floating gate manufacturing process 17 of the present invention shown in FIG. 8, in practice, the filled oxide may exceed the part that needs to be filled. Therefore, after filling the oxide, you can use Chemical mechanical planarization removes oxide beyond the protective layer in the shallow isolation trenches.

Step 108, removing the protective layer;

Referring to FIG. 9 , which is a cross-sectional view of a floating gate manufacturing process 18 of the present invention, after removing the oxide in the shallow insulating trench beyond the protection layer, the protection layer is removed.

Step 109, etching the oxide according to a second preset pattern.

In a preferred embodiment of the present invention, the step 109 may include the following sub-steps:

In sub-step S61, the oxide is etched according to the second preset pattern by using dry method and wet method in sequence.

In a preferred embodiment of the present invention, before the step 109, the following steps may also be included:

Depositing amorphous carbon and an anti-reflection layer sequentially on the protective layer, and covering photoresist on the amorphous carbon and anti-reflection layer;

A preset pattern is photolithographically etched on the photoresist.

Referring to the cross-sectional view of a floating gate manufacturing process 19-23 of the present invention shown in FIG. A layer of photoresist is covered on the carbon and the anti-reflection layer, and a second preset pattern is photoetched on the photoresist, and then the oxide is etched according to the preset pattern by using dry method and wet method in sequence.

In order for those skilled in the art to further understand the embodiment of the present invention, a specific example is used to illustrate the process flow of the present invention for manufacturing the floating gate, and the specific steps are as follows:

1. FG POLY1 DEP (floating gate polysilicon deposition);

2. FG POLY1 DEP SCRUBBER (cleaning after floating gate polysilicon deposition);

3. FG POLY1 IMP (floating gate polysilicon doping);

4. FG POLY1 IMP ANNEAL (floating gate polysilicon doping annealing, wherein, annealing is to raise polysilicon and doping to a certain temperature for a period of time, and then return to the original temperature);

5. FG POLY1 HM DEP (floating gate polysilicon protection layer deposition);

6. FG POLY1 AC DEP (floating gate polysilicon amorphous carbon deposition);

7. FG POLY1 DARK DEP (floating gate polysilicon anti-reflection layer deposition);

8. STI PHOTO (shallow insulation trench photoresist lithography);

9. STI TRENCH ETCH (Shallow Insulation Trench Etching);

10. STI TRENCH ETCH ASHER (dry photoresist removal);

11. STI TRENCH ETCH WET STRIP (wet method to remove photoresist);

12. STI PRE HARP DEP CLN (cleaning before filling shallow insulation trench oxide);

13. STI HARP DEP (Shallow Insulation Trench Oxide Film Deposition);

14. STI OXIDATION (shallow insulation trench high temperature oxidation);

15. STI HARP DEP (shallow insulation trench oxide filling);

16. RTA (annealing, wherein, annealing is to raise the oxide to a certain temperature for a period of time, and then return to the original temperature);

17. STI OXIDE CMP (Shallow Insulation Trench Oxide Chemical Mechanical Planarization);

18. STI HM REMOVAL (removal of floating gate protective layer);

19. COPEN PHOTO (Oxide Photoresist Photolithography in Shallow Insulation Trench);

20. COPEN DRY ETCH (dry etching of oxide in shallow insulation trench);

21. COPEN WET ETCH (wet etching of oxide in shallow insulation trench);

22. COPEN ASHER (dry photoresist removal);

23. COPEN WET STRIP (wet method to remove photoresist).

It should be noted that, for the method embodiment, for the sake of simple description, it is expressed as a series of action combinations, but those skilled in the art should know that the application is not limited by the described action sequence, because according to this application, certain steps may be performed in another order or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by this application.

Each embodiment in this specification is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same and similar parts of each embodiment can be referred to each other.

The manufacturing process of a synchronous etching floating gate provided by the present invention has been introduced in detail above. In this paper, specific examples are used to illustrate the principle and implementation mode of the present invention. The description of the above embodiments is only used to help understanding The method of the present invention and its core idea; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation and scope of application. In summary, the content of this specification should not be construed as a limitation of the invention.

Claims (9)

1. A manufacturing process for synchronously etching floating gates, characterized in that, comprising: Sequentially oxidize the working area to generate a tunnel oxide layer and deposit polysilicon and doping; depositing a protective layer on the doped polysilicon; Etching the doped polysilicon according to a first preset pattern to form shallow insulating trenches; Depositing a first oxide film on the surface of the shallow insulation trench; Oxidizing the first oxide film at high temperature to form a second oxide film; Filling the shallow insulation trench with oxide; removing the oxide beyond the protection layer in the shallow insulation trench by chemical mechanical planarization; removing said protective layer; The oxide is etched according to a second preset pattern. 2. The method according to claim 1, characterized in that, before the step of etching the doped polysilicon according to the first preset pattern to form shallow insulation trenches, and after the step of etching the doped polysilicon according to the second preset pattern Before the step of patterning and etching the oxide, it also includes: Depositing amorphous carbon and an anti-reflection layer sequentially on the protective layer, and covering photoresist on the amorphous carbon and anti-reflection layer; A preset pattern is photolithographically etched on the photoresist. 3. The method according to claim 1 or 2, characterized in that, after the step of etching the doped polysilicon to form a shallow insulating trench according to the first preset pattern, and after the step of etching the doped polysilicon according to the first preset pattern, After the step of etching the oxide with the second preset pattern, it also includes: The photoresist is removed by a dry method and a wet method in sequence. 4. The method according to claim 1 or 2, wherein the step of etching the oxide according to the second preset pattern is: The oxide is etched according to the second predetermined pattern by using dry method and wet method sequentially. 5. The method according to claim 1, characterized in that, after the step of filling the shallow insulating trench with oxide, further comprising: uniform distribution of the oxide; The step of uniformly distributing the oxide comprises: raising the temperature of the oxide to a preset temperature; Return the temperature of the oxide to normal temperature. 6. The method according to claim 1, wherein the step of depositing polysilicon and doping comprises: depositing polysilicon on the working area, and cleaning the surface of the polysilicon after deposition; The polysilicon is doped with impurities. 7. The method according to claim 1 or 6, further comprising: uniformly distributing said doped polysilicon; The step of uniformly distributing the doped polysilicon includes: raising the temperature of the doped polysilicon to a preset temperature; Return the temperature of the doped polysilicon to normal temperature. 8. The method according to claim 1, further comprising: after the step of etching the doped polysilicon according to the first preset pattern to form a shallow insulating trench Cleaning the surface of the shallow insulation trench. 9 . The method according to claim 1 , wherein the side section of the shallow insulation trench is wide at the top and narrow at the bottom.