CN114334971A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present invention relates to a semiconductor device comprising: a substrate on which a selection switch transistor is formed; the first dielectric layer is positioned on the substrate and covers the selective switch transistor; the capacitor is positioned on the upper surface of the first dielectric layer and comprises a lower electrode, a capacitor dielectric layer and an upper electrode, the capacitor dielectric layer covers the upper surface and the side surface of the lower electrode, the upper electrode covers the upper surface and the side surface of the capacitor dielectric layer, and the lower electrode is electrically connected with the drain electrode of the selective switch transistor; the second dielectric layer is positioned on the upper surface of the first dielectric layer and covers the capacitor; the metal layer is positioned on the upper surface of the second dielectric layer; the metal layer at least comprises a plate line which is electrically connected with the capacitor. Because the area of the capacitor comprises the upper surface and the side surface of the lower electrode, compared with the traditional capacitor, the area of the capacitor with the side surface of the lower electrode is increased, and the advantage that the capacitor with a large enough area is still maintained under the condition that the area of the semiconductor device is reduced is realized.

Description

Semiconductor device and method of making the same

technical field

The present invention relates to the field of semiconductors, in particular to a semiconductor device and a preparation method thereof.

Background technique

A conventional 1T1C (1 transistor, 1 capacitor) memory cell requires one transistor and one capacitor, and the capacitor is generally a planar capacitor. As integrated circuits shrink along Moore's Law, conventional 1T1C memory cells will encounter the problem of not being able to shrink. This is because in the case of continuous shrinking, especially to the technology nodes below the 0.13μm standard CMOS manufacturing process, with the need for capacitance Continuously shrinking the area, the capacitance value of the planar capacitor will decrease in the same proportion as the area shrinks. The charge that can be stored by the capacitor that is too small is limited, and the amount of charge stored by the capacitor is greatly reduced, which reduces the performance of the memory cell in actual work, and even Difficulty reading. In order to maintain a sufficiently large capacitance in the case of unit scaling, it is necessary to maintain a large capacitance structure, which is contrary to the development direction of the continuous shrinking of integrated circuits.

SUMMARY OF THE INVENTION

Based on this, it is necessary to address the above problems to provide a semiconductor device and a manufacturing method thereof, which have the advantage of maintaining a sufficiently large capacitance even when the area of the semiconductor device is reduced.

A semiconductor device, comprising:

a substrate, on which a selection switch transistor is formed;

a first dielectric layer, located on the substrate, and covering the selection switch transistor;

A capacitor, located on the upper surface of the first dielectric layer, includes a lower electrode, a capacitor dielectric layer and an upper electrode, the capacitor dielectric layer covers the upper surface and side surfaces of the lower electrode, and the upper electrode covers the capacitor dielectric layer The upper surface and the side surface of the lower electrode are electrically connected to the drain of the selection switch transistor;

The second dielectric layer is located on the upper surface of the first dielectric layer and covers the capacitor, and the capacitor is located inside the second dielectric layer;

The metal layer is located on the upper surface of the second dielectric layer; the metal layer at least includes a plate wire, and the plate wire is electrically connected to the capacitor.

In one embodiment, a first conductive plug is formed in the first dielectric layer, one end of the first conductive plug is electrically connected to the lower electrode, and the other end is connected to the drain of the selection switch transistor electrical connection;

A second conductive plug is formed in the second dielectric layer, one end of the second conductive plug is electrically connected to the upper electrode, and the other end is electrically connected to the plate wire.

In one embodiment, the capacitance extends from above the drain to above the gate of the select switch transistor.

In one embodiment, the capacitor dielectric layer includes a zirconium-doped hafnium oxide thin film layer; the molar ratio of zirconium, hafnium and oxygen in the capacitor dielectric layer is 0.3:0.3:0.5˜0.7:0.7:2.5.

In one of the embodiments, the cross section of the lower electrode is trapezoidal;

The capacitive dielectric layer includes a first part and a second part, the first part covers the upper surface and the side surface of the lower electrode, the second part is located between the upper electrode and the first dielectric layer, and the second part is located between the upper electrode and the first dielectric layer. The second part is integrally arranged with the first part.

The present application also provides a method for preparing a semiconductor device, comprising:

providing a substrate, and forming a selection switch transistor on the substrate;

forming a first dielectric layer on the upper surface of the substrate, the first dielectric layer covering the selection switch transistor;

A capacitor is formed on the upper surface of the first dielectric layer, the capacitor includes a lower electrode, a capacitor dielectric layer and an upper electrode, the capacitor dielectric layer covers the upper surface and side surfaces of the lower electrode, and the upper electrode covers the the upper surface and the side surface of the capacitive dielectric layer, the lower electrode is electrically connected to the drain of the selection switch transistor;

A second dielectric layer is formed on the upper surface of the first dielectric layer, the second dielectric layer covers the capacitor, and the capacitor is located inside the second dielectric layer;

A metal layer is formed on the upper surface of the second dielectric layer, the metal layer at least includes a plate line, and the plate line is electrically connected to the capacitor.

In one embodiment, forming a capacitor on the upper surface of the first dielectric layer includes:

forming a lower electrode on the upper surface of the first dielectric layer;

forming a capacitor dielectric material layer on the upper surface of the lower electrode, the side surface of the lower electrode and the upper surface of the first dielectric layer;

forming an upper electrode material layer on the surface of the capacitor dielectric material layer;

removing the upper electrode material layer located on the upper surface of the first dielectric layer and the capacitor dielectric material layer located on the upper surface of the first dielectric layer, and the remaining capacitors located on the upper surface and side surfaces of the lower electrode The dielectric material layer is the capacitor dielectric layer, and the upper electrode material layer remaining on the upper surface and the side surface of the capacitor dielectric layer is the upper electrode.

In one embodiment, after the capacitor is formed and before the second dielectric layer is formed, a step of annealing the obtained structure is further included.

In one embodiment, the temperature of the annealing treatment ranges from 450°C to 750°C.

In one embodiment, before the capacitor is formed on the upper surface of the first quality layer, the method further includes:

forming a first interconnection through hole in the first dielectric layer, and the first interconnection through hole exposes the drain of the selection switch transistor;

A first conductive plug is formed in the first interconnection via.

In one embodiment, before forming the metal layer on the upper surface of the second dielectric layer, the method further includes:

forming a second interconnect via hole in the second dielectric layer, and the second interconnect via hole exposes the upper electrode;

A second conductive plug is formed in the second interconnection via.

The semiconductor device of the present application and its preparation method have the following beneficial effects:

Since the area of the capacitor includes both the upper surface and the side surface of the lower electrode, compared with the traditional capacitor, the area of the capacitor where the side surface of the lower electrode is located is larger, and the capacitor is formed on the upper surface of the first dielectric layer instead of being recessed downward. Entering into the first dielectric layer is easier in process control, and reduces the possibility of high instability of the grown capacitor structure due to the difficult control of the corner position and topography of the trench structure during the process of forming the capacitor. Since the increase of the area of the side of the capacitor has very little change in the overall area of the semiconductor device, it is possible to increase the area of the capacitor by increasing the area of the side of the lower electrode, so that the area of the semiconductor device can still be maintained adequately. advantage of large capacitors.

Description of drawings

1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

2 is a schematic cross-sectional structure diagram of a semiconductor device display substrate in an embodiment of the present invention;

3 is a schematic cross-sectional structure diagram of a semiconductor device after a first dielectric layer is formed in an embodiment of the present invention;

4 is a schematic cross-sectional structure diagram of a semiconductor device after forming a first interconnection via in an embodiment of the present invention;

5 is a schematic cross-sectional structure diagram of a semiconductor device after forming a first conductive plug in an embodiment of the present invention;

6 is a schematic cross-sectional structure diagram of a semiconductor device after forming a lower electrode in an embodiment of the present invention;

7 is a schematic cross-sectional structure diagram of a semiconductor device after a capacitor dielectric material layer is formed in an embodiment of the present invention;

8 is a schematic cross-sectional structure diagram of a semiconductor device after forming an upper electrode material layer in an embodiment of the present invention;

9 is a schematic diagram of a cross-sectional structure of a semiconductor device after a capacitor is formed in an embodiment of the present invention;

10 is a schematic cross-sectional structure diagram of a semiconductor device after forming a second dielectric layer in an embodiment of the present invention;

FIG. 11 is a schematic cross-sectional structure diagram of a semiconductor device after a metal layer is formed in an embodiment of the present invention.

Reference numerals: 10, substrate; 11, selection switch transistor; 111, gate electrode; 112, source electrode; 113, drain electrode; 12, first dielectric layer; 13, first interconnect via hole; 14, first conductive plug; 15, first contact hole; 16, first contact plug; 17, second contact hole; 18, second contact plug; 19, capacitor; 191, lower electrode; 1921, capacitor dielectric material layer; 192 , capacitor dielectric layer; 1931, upper electrode material layer; 193, upper electrode; 20, second dielectric layer; 21, second conductive plug; 22, third contact plug; 23, fourth contact plug; 24, Metal layer; 241, plate wire; 242, first metal connection layer; 243, second metal connection layer; 25, shallow trench isolation structure.

Detailed ways

In order to facilitate understanding of the present invention, the present invention will be described more fully hereinafter with reference to the related drawings. Preferred embodiments of the invention are shown in the accompanying drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only, and are not intended to limit the present invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. is based on the drawings shown in the drawings. The method or positional relationship is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention .

A conventional 1T1C (1 transistor, 1 capacitor) memory cell requires one transistor and one capacitor, and the capacitor is generally a planar capacitor. As integrated circuits shrink along Moore's Law, conventional 1T1C memory cells will encounter the problem of not being able to shrink. This is because in the case of continuous shrinking, especially to the technology nodes below the 0.13μm standard CMOS manufacturing process, with the need for capacitance Continuously shrinking the area, the capacitance value of the planar capacitor will decrease in the same proportion as the area shrinks. The charge that can be stored by the capacitor that is too small is limited, and the amount of charge stored by the capacitor is greatly reduced, which reduces the performance of the memory cell in actual work, and even Difficulty reading. In order to maintain a sufficiently large capacitance in the case of unit scaling, it is necessary to maintain a large capacitance structure, which is contrary to the development direction of the continuous shrinking of integrated circuits.

In order to solve the above-mentioned technical problems, the present invention provides a preparation method of a semiconductor device, comprising:

Step S10: providing a substrate 10, and forming a selection switch transistor 11 on the substrate 10, as shown in FIG. 2;

Step S20 : forming a first dielectric layer 12 on the upper surface of the substrate 10 , and the first dielectric layer 12 covers the selection switch transistor 11 , as shown in FIG. 3 ;

Step S30 : forming a capacitor 19 on the upper surface of the first dielectric layer 12 , the capacitor 19 includes a lower electrode 191 , a capacitor dielectric layer 192 and an upper electrode 193 , the capacitor dielectric layer 192 covers the upper surface and side surfaces of the lower electrode 191 , and the upper electrode 193 covers On the upper surface and the side surface of the capacitive dielectric layer 192, the lower electrode 191 is electrically connected to the drain electrode 113 of the selection switch transistor 11, as shown in FIG. 9;

Step S40 : forming a second dielectric layer 20 on the upper surface of the first dielectric layer 12 , the second dielectric layer 20 covers the capacitor 19 , and the capacitor 19 is located inside the second dielectric layer 20 , as shown in FIG. 10 ;

Step S50 : forming a metal layer 24 on the upper surface of the second dielectric layer 20 , the metal layer 24 at least includes a plate wire 241 , and the plate wire 241 is electrically connected to the capacitor 19 , as shown in FIG. 11 .

Through the above steps, since the area of the capacitor includes both the upper surface and the side surface of the lower electrode 191, the area of the capacitor 19 where the side surface of the lower electrode 191 is located is larger than that of the conventional capacitor, and the capacitor 19 is formed on the first dielectric layer. The upper surface of 12 is not recessed downward into the first dielectric layer 12 , which is easier to process control, and reduces the inability of the grown capacitor structure due to the difficult control of the corner position and morphology of the trench structure in the process of forming the capacitor 19 . The possibility of higher stability. Since the increase in the area of the side of the lower electrode 191 is very weak to the overall area of the semiconductor device, the capacitance area of the capacitor 19 can be increased by increasing the area of the side of the lower electrode 191, thereby reducing the area of the semiconductor device. case still maintains the advantage of a sufficiently large capacitance.

In an optional embodiment, for step S10, specifically, the material of the substrate 10 may be silicon, germanium, gallium arsenide, indium phosphide or gallium nitride, etc., that is, the substrate 10 may be a silicon substrate, a germanium substrate, Gallium arsenide substrate, indium phosphide substrate or gallium nitride substrate, etc. In this embodiment, the substrate 10 may be a silicon substrate. A selection switch transistor 11 is formed on the substrate 10. The selection switch transistor 11 includes a gate electrode 111, a source electrode 112 and a drain electrode 113. The source electrode 112 and the drain electrode 113 are formed in the substrate 10, and the gate electrode 111 is formed on the upper surface of the substrate 10. And the source electrode 112 and the drain electrode 113 are located on both sides of the gate electrode 111 .

In an optional embodiment, a shallow trench isolation structure 25 is further formed in the substrate 10 for isolating several spaced active regions in the substrate 10, and the selection switch transistor 11 is located in the active region.

In an optional embodiment, for step S20, specifically, a first dielectric material layer is deposited on the upper surface of the substrate 10 through a deposition process, and the first dielectric material layer is obtained after planarization treatment, and the first dielectric layer 12 is obtained. The thickness of a dielectric layer 12 is greater than the thickness of the gate electrode 111 of the selection switch transistor 11 , and completely covers the selection switch transistor 11 .

In an optional embodiment, after step S20 and before step S30, it further includes a step of forming a first conductive plug 14 in the first dielectric layer 12, as shown in FIG. 4 and FIG. A first interconnection through hole 13 is formed in the first dielectric layer 12 by an etching process, and the first interconnection through hole 13 exposes the drain electrode 113 of the selection switch transistor 11; A conductive plug 14, the first conductive plug 14 is in direct contact with the drain 113 of the selection switch transistor 11 and is electrically connected.

In an optional embodiment, the first contact holes 15 and the second contact holes 17 are also formed in the first dielectric layer 12 while the first interconnect via holes 13 are formed in the first dielectric layer 12 . The hole 15 exposes the source electrode 112 of the selection switch transistor 11 , and the second contact hole 17 exposes the substrate 10 ; while the first conductive plug 14 is formed in the first interconnection through hole 13 , the first conductive plug 14 is also formed in the first contact hole 15 A first contact plug 16 is formed, and a second contact plug 18 is formed in the second contact hole 17 . The materials of the first conductive plug 14 , the first contact plug 16 and the second contact plug 18 may be metals such as copper or tungsten.

In an optional embodiment, for step S30, specifically, the following steps are included:

Step S301 : forming a lower electrode 191 on the upper surface of the first dielectric layer 12 , as shown in FIG. 6 ;

Step S302 : forming a capacitor dielectric material layer 1921 on the upper surface of the lower electrode 191 , the side surface of the lower electrode 191 and the upper surface of the first dielectric layer 12 , as shown in FIG. 7 ;

Step S303 : forming an upper electrode material layer 1931 on the surface of the capacitor dielectric material layer 1921 , as shown in FIG. 8 ;

Step S304 : remove the upper electrode material layer 1931 located on the upper surface of the first dielectric layer 12 and the capacitive dielectric material layer 1921 located on the upper surface of the first dielectric layer 12 , and the remaining capacitive dielectric material layer 1921 located on the upper surface and side surfaces of the lower electrode 191 That is, the capacitor dielectric layer 192 , and the remaining upper electrode material layer 1931 located on the upper surface and the side surface of the capacitor dielectric layer 192 is the upper electrode 193 , as shown in FIG. 9 .

Specifically, first, a sacrificial layer is formed on the upper surface of the first dielectric layer 12 , the position and shape of the lower electrode 191 are defined by etching the sacrificial layer, the lower electrode 191 is formed based on the etched sacrificial layer, and the sacrificial layer is removed and retained The material of the electrode 191 and the lower electrode 191 may be titanium nitride. The lower electrode 191 is in direct contact with the first conductive plug 14 and is electrically connected, and the lower electrode 191 of the capacitor 19 is electrically connected to the drain 113 of the selection switch transistor 11 through the first conductive plug 14 . The thickness of the lower electrode 191 may be determined by the deposition or etching process level. The thicker the lower electrode 191 is, the larger the area of the capacitor 19 of the capacitor 19 is. In an optional embodiment, the cross section of the lower electrode 191 is trapezoidal, and in another optional embodiment, the cross section of the lower electrode 191 is rectangular. The capacitor dielectric material layer 1921 is formed by an atomic layer deposition process, and the material of the capacitor dielectric layer 192 can be a high-K dielectric constant ferroelectric thin film doped with hafnium oxide. In an optional embodiment, the molar ratio of zirconium, hafnium and oxygen in the capacitor dielectric layer 192 is 0.3:0.3:0.5˜0.7:0.7:2.5. The upper electrode material layer 1931 is also formed by an atomic layer deposition process, and the material of the upper electrode 193 layer can be titanium nitride.

The structure of the capacitor 19 is convex. In an optional embodiment, the cross section of the lower electrode 191 is a trapezoid, and the area of the side of the lower electrode 191 in contact with the first dielectric layer 12 is larger than that of the lower electrode 191 away from the first dielectric layer. 12 the area of one side. The capacitive dielectric layer 192 includes a first part and a second part, the first part covers the upper surface and the side surface of the lower electrode 191 , the second part is located in the circumferential direction of the lower electrode 191 , and the second part is located between the upper electrode 193 and the first dielectric layer 12 . the second part is integrally arranged with the first part. The capacitor 19 is located inside the second dielectric layer 20 after the second dielectric layer 20 is formed. Compared with forming the capacitor 19 inside the first dielectric layer 12, the part of forming a trench in the capacitor 19 is reduced, thereby avoiding the formation of trenches. When the shape of the trench corner is not easy to control, as the size of the device continues to decrease, the irregularity of the trench shape will lead to the enhancement of the local electric field, which will affect the breakdown stability of the capacitor structure. Making the capacitor 19 a protruding structure formed on the upper surface of the first dielectric layer 19 can effectively reduce the occurrence of such problems.

In an optional embodiment, after step S30 and before step S40, a step of annealing the obtained structure is further included, the purpose of which is to activate the ferroelectric properties of the doped hafnium oxide. In an optional embodiment, the temperature of the annealing treatment ranges from 450°C to 750°C, which may be 450°C, 600°C or 750°C.

For step S40, specifically, the second dielectric material layer is formed by high-density plasma chemical vapor deposition of oxide, and the material of the second dielectric material layer may be insulating materials such as silicon dioxide, silicon oxynitride, and silicon nitride. The second dielectric material layer is planarized to form a second dielectric layer 20 . The thickness of the second dielectric layer 20 is greater than that of the capacitor 19 and completely covers the capacitor 19 .

In an optional embodiment, after the step S40 and before the step S50, it further includes the step of forming the second conductive plug 21 in the second dielectric layer 20. A second interconnection via hole is formed in the two dielectric layers 20, and the second interconnection via hole exposes the upper electrode 193; a second conductive plug 21 is formed in the second interconnection via hole, and the second conductive plug 21 and the upper electrode 193 are formed Direct contact and make electrical connections.

In another optional embodiment, while the second interconnect via hole is formed in the second dielectric layer 20 , the third contact hole and the fourth contact hole are also formed in the second dielectric layer 20 . The third contact hole exposes the first contact plug 16 , and the fourth contact hole exposes the second contact plug 18 . The second conductive plug 21 is formed in the second interconnection hole, and the third contact plug 22 is also formed in the third contact hole, and the fourth contact plug 23 is formed in the fourth contact hole; The plug 22 is electrically connected to the first contact plug 16 , and the fourth contact plug 23 is electrically connected to the second contact plug 18 . In an optional embodiment, the materials of the second conductive plug 21 , the third contact plug 22 and the fourth contact plug 23 may all be metal tungsten.

For step S50 , an imaged mask layer is formed on the upper surface of the second dielectric layer 20 , and a metal layer 24 is formed on the upper surface of the second dielectric layer 20 based on the patterned mask layer. The metal layer 24 at least includes a plate wire 241, and the plate wire 241 is in direct contact with the second conductive plug 21, and an electrical connection is formed therebetween. Since the second conductive plug 21 is electrically connected to the upper electrode 193 of the capacitor 19 , the plate line 241 is electrically connected to the upper electrode 193 of the capacitor 19 , and the lower electrode 191 of the capacitor 19 is connected to the selection switch transistor 11 through the first conductive plug 14 The drain 113 is electrically connected. The metal layer 24 further includes a first metal connection layer 242 and a second metal connection layer 243, the first metal connection layer 242 is in direct contact with the third contact plug 22 and is electrically connected, and the second metal connection layer 243 is in direct contact with the fourth contact plug 22. The plug 23 is in direct contact and makes electrical connection.

As shown in FIG. 11 , the present application further provides a semiconductor device, comprising: a substrate 10 on which a selection switch transistor 11 is formed; a first dielectric layer 12 located on the substrate 10 and covering the selection switch transistor 11 ; a capacitor 19 , located on the upper surface of the first dielectric layer 12, including the lower electrode 191, the capacitor dielectric layer 192 and the upper electrode 193, the capacitor dielectric layer 192 covers the upper surface and side surfaces of the lower electrode 191, and the upper electrode 193 covers the upper surface of the capacitor dielectric layer 192 and the side, the lower electrode 191 is electrically connected to the drain 113 of the selection switch transistor 11; the second dielectric layer 20 is located on the upper surface of the first dielectric layer 12 and covers the capacitor 19, and the capacitor 19 is located inside the second dielectric layer 20; the metal The layer 24 is located on the upper surface of the second dielectric layer 20 ; the metal layer 24 at least includes a plate wire 241 , and the plate wire 241 is electrically connected to the capacitor 19 .

Specifically, for the substrate 10, in an optional embodiment, the material of the substrate 10 may be silicon, germanium, gallium arsenide, indium phosphide or gallium nitride, etc., that is, the substrate 10 may be a silicon substrate 10, a germanium substrate 10. A gallium arsenide substrate 10, an indium phosphide substrate 10 or a gallium nitride substrate 10, and the like. In this embodiment, the substrate 10 may be a silicon substrate 10 . A selection switch transistor 11 is formed on the substrate 10. The selection switch transistor 11 includes a gate electrode 111, a source electrode 112 and a drain electrode 113. The source electrode 112 and the drain electrode 113 are formed in the substrate 10, and the gate electrode 111 is formed on the upper surface of the substrate 10. And the source electrode 112 and the drain electrode 113 are located on both sides of the gate electrode 111 .

In an optional embodiment, the first dielectric layer 12 is formed on the upper surface of the substrate 10 by a deposition process. The thickness of the first dielectric layer 12 is greater than the thickness of the gate 111 of the selection switch transistor 11 and completely covers the selection switch. Transistor 11. The first dielectric layer 12 includes a first conductive plug 14, one end of the first conductive plug 14 is in direct contact with the drain 113 of the selection switch transistor 11 and is electrically connected, and the other end of the lower electrode 191 of the capacitor 19 is in direct contact and realizes electrical connection. electrical connection. In an optional embodiment, a first contact plug 16 and a second contact plug 18 are further formed in the first dielectric layer 12 , and one end of the first contact plug 16 is electrically connected to the source electrode 112 of the selection switch transistor 11 . For connection, one end of the second contact plug 18 is in direct contact with the substrate 10 . The materials of the first conductive plug 14 , the first contact plug 16 and the second contact plug 18 may be metals such as copper or tungsten.

In an optional embodiment, the material of the lower electrode 191 may be titanium nitride. The lower electrode 191 is in direct contact with the first conductive plug 14 and is electrically connected, and the lower electrode 191 of the capacitor 19 is electrically connected to the drain 113 of the selection switch transistor 11 through the first conductive plug 14 . The thickness of the lower electrode 191 may be determined by the deposition or etching process level. The thicker the lower electrode 191 is, the larger the area of the capacitor 19 of the capacitor 19 is. In an optional embodiment, the cross section of the lower electrode 191 is trapezoidal, and in another optional embodiment, the cross section of the lower electrode 191 is rectangular. The capacitor dielectric material layer 1921 is formed by an atomic layer deposition process, and the material of the capacitor dielectric layer 192 can be a high-K dielectric constant ferroelectric thin film doped with hafnium oxide. In an optional embodiment, the molar ratio of zirconium, hafnium and oxygen in the capacitor dielectric layer 192 is 0.3:0.3:0.5˜0.7:0.7:2.5. The upper electrode material layer 1931 is also formed by an atomic layer deposition process, and the material of the upper electrode 193 layer can be titanium nitride. In an alternative embodiment, the capacitor 19 extends from above the drain 113 to above the gate 111 of the select switch transistor 11 .

The structure of the capacitor 19 is upwardly convex. In an optional embodiment, the cross section of the lower electrode 191 is a trapezoid, and the area of the side of the lower electrode 191 in contact with the first dielectric layer 12 is larger than that of the lower electrode 191 away from the first dielectric. The area of one side of layer 12 . The capacitive dielectric layer 192 includes a first part and a second part, the first part covers the upper surface and the side surface of the lower electrode 191 , the second part is located in the circumferential direction of the lower electrode 191 , and the second part is located between the upper electrode 193 and the first dielectric layer 12 . the second part is integrally arranged with the first part. The capacitor 19 is located inside the second dielectric layer 20 after the second dielectric layer 20 is formed. Compared with forming the capacitor 19 inside the first dielectric layer 12, the part of forming a trench in the capacitor 19 is reduced, thereby avoiding the formation of trenches. When the shape of the trench corner is not easy to control, as the size of the device continues to decrease, the irregularity of the trench shape will lead to the enhancement of the local electric field, which will affect the breakdown stability of the capacitor structure. Making the capacitor 19 a protruding structure formed on the upper surface of the first dielectric layer 19 can effectively reduce the occurrence of such problems.

In an optional embodiment, the material of the second dielectric layer 20 may be insulating materials such as silicon dioxide, silicon oxynitride, and silicon nitride. The thickness of the second dielectric layer 20 is larger than that of the capacitor 19 , and completely covers the capacitor 19 . In an optional embodiment, the second dielectric layer 20 further includes a second conductive plug 21, one end of the second conductive plug 21 is in direct contact with the upper electrode 193 of the capacitor 19 and is electrically connected, and the other end is connected to the metal The plate wires 241 of layer 24 are in direct contact and make electrical connections. In an optional embodiment, the materials of the second conductive plug 21 , the third contact plug 22 and the fourth contact plug 23 may all be metal tungsten.

In an optional embodiment, the metal layer 24 includes a plate wire 241 , a first metal connection layer 242 and a second metal connection layer 243 . The plate wire 241 is in direct contact with the second conductive plug 21, and an electrical connection is formed therebetween. Since the second conductive plug 21 is electrically connected to the upper electrode 193 of the capacitor 19 , the plate line 241 is electrically connected to the upper electrode 193 of the capacitor 19 , and the lower electrode 191 of the capacitor 19 is connected to the selection switch transistor 11 through the first conductive plug 14 The drain 113 is electrically connected. The metal layer 24 further includes a first metal connection layer 242 and a second metal connection layer 243, the first metal connection layer 242 is in direct contact with the third contact plug 22 and is electrically connected, and the second metal connection layer 243 is in direct contact with the fourth contact plug 22. The plug 23 is in direct contact and makes electrical connection.

In the above-mentioned semiconductor device, since the area of the capacitor includes the upper surface and the side surface of the lower electrode 191 at the same time, compared with the traditional capacitor, the area of the capacitor where the side surface of the lower electrode 191 is located is larger, and the area of the side surface of the lower electrode 191 is increased. The change in the overall area of the semiconductor device is very weak, so the capacitance area of the capacitor 19 can be increased by increasing the area of the side of the lower electrode 191, so as to maintain a sufficiently large capacitance even when the area of the semiconductor device is reduced. advantage. And its manufacturing process is fully compatible with the standard CMOS process, the manufacturing process is mature, and it is mass-produced.

The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity, all possible combinations of the technical features in the above-described embodiments are not described. However, as long as there is no contradiction between the combinations of these technical features, All should be regarded as the scope described in this specification.

The above-mentioned embodiments only represent several embodiments of the present invention, and the descriptions thereof are more specific and detailed, but should not be construed as a limitation on the scope of the invention patent. It should be pointed out that for those skilled in the art, without departing from the concept of the present invention, several modifications and improvements can be made, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention should be subject to the appended claims.

Claims (11)

1. A semiconductor device, comprising:

a substrate on which a selection switch transistor is formed;

the first dielectric layer is positioned on the substrate and covers the selection switch transistor;

the capacitor is positioned on the upper surface of the first dielectric layer and comprises a lower electrode, a capacitor dielectric layer and an upper electrode, the capacitor dielectric layer covers the upper surface and the side surface of the lower electrode, the upper electrode covers the upper surface and the side surface of the capacitor dielectric layer, and the lower electrode is electrically connected with the drain electrode of the selective switch transistor;

the second dielectric layer is positioned on the upper surface of the first dielectric layer and covers the capacitor, and the capacitor is positioned in the second dielectric layer;

the metal layer is positioned on the upper surface of the second dielectric layer; the metal layer at least comprises a plate line, and the plate line is electrically connected with the capacitor.

2. The semiconductor device according to claim 1, wherein a first conductive plug is formed in the first dielectric layer, one end of the first conductive plug is electrically connected to the lower electrode, and the other end of the first conductive plug is electrically connected to a drain of the selection switch transistor;

and a second conductive plug is formed in the second dielectric layer, one end of the second conductive plug is electrically connected with the upper electrode, and the other end of the second conductive plug is electrically connected with the plate line.

3. The semiconductor device according to claim 1, wherein the capacitor extends from above the drain to above a gate of the selection switch transistor.

4. The semiconductor device of claim 1, wherein the capacitance dielectric layer comprises a zirconium-doped hafnium oxide thin film layer; the molar ratio of zirconium to hafnium to oxygen in the capacitor dielectric layer is 0.3:0.3: 0.5-0.7: 0.7: 2.5.

5. The semiconductor device according to claim 1, wherein a cross section of the lower electrode is trapezoidal;

the capacitor dielectric layer comprises a first part and a second part, the first part covers the upper surface and the side face of the lower electrode, the second part is located between the upper electrode and the first dielectric layer, and the second part and the first part are integrally arranged.

6. A method of manufacturing a semiconductor device, comprising:

providing a substrate, and forming a selection switch transistor on the substrate;

forming a first dielectric layer on the upper surface of the substrate, wherein the first dielectric layer covers the selection switch transistor;

forming a capacitor on the upper surface of the first dielectric layer, wherein the capacitor comprises a lower electrode, a capacitor dielectric layer and an upper electrode, the capacitor dielectric layer covers the upper surface and the side surface of the lower electrode, the upper electrode covers the upper surface and the side surface of the capacitor dielectric layer, and the lower electrode is electrically connected with the drain electrode of the selective switch transistor;

forming a second dielectric layer on the upper surface of the first dielectric layer, wherein the second dielectric layer covers the capacitor, and the capacitor is positioned in the second dielectric layer;

and forming a metal layer on the upper surface of the second dielectric layer, wherein the metal layer at least comprises a plate line, and the plate line is electrically connected with the capacitor.

7. The method of claim 6, wherein forming a capacitor on the top surface of the first dielectric layer comprises:

forming a lower electrode on the upper surface of the first dielectric layer;

forming a capacitance dielectric material layer on the upper surface of the lower electrode, the side surface of the lower electrode and the upper surface of the first dielectric layer;

forming an upper electrode material layer on the surface of the capacitance medium material layer;

and removing the upper electrode material layer positioned on the upper surface of the first dielectric layer and the capacitor dielectric material layer positioned on the upper surface of the first dielectric layer, wherein the capacitor dielectric material layer positioned on the upper surface and the side surface of the lower electrode is reserved as the capacitor dielectric layer, and the upper electrode material layer positioned on the upper surface and the side surface of the capacitor dielectric layer is reserved as the upper electrode.

8. The method of claim 6, further comprising annealing the resulting structure after forming the capacitor and before forming the second dielectric layer.

9. The method for manufacturing a semiconductor device according to claim 6, wherein the temperature of the annealing treatment is 450 to 750 ℃.

10. The method of claim 7, further comprising, before forming a capacitor on the top surface of the first layer:

forming a first interconnection through hole in the first dielectric layer, wherein the first interconnection through hole exposes the drain electrode of the selection switch transistor;

and forming a first conductive plug in the first interconnection through hole.

11. The method of claim 10, further comprising, before forming the metal layer on the top surface of the second dielectric layer:

forming a second interconnection through hole in the second dielectric layer, wherein the second interconnection through hole exposes the upper electrode;

and forming a second conductive plug in the second interconnection through hole.

Images