CN103985636B - 调整多阈值电压的FinFET/三栅极沟道掺杂 - Google Patents
调整多阈值电压的FinFET/三栅极沟道掺杂 Download PDFInfo
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Abstract
控制鳍式场效应晶体管(FinFET)内阈值电压的实施例方法包括：在鳍的中间部分的上方形成虚拟栅极，鳍的中间部分设置在未受虚拟栅极保护的鳍的外部部分之间；去除鳍的外部部分且用外延生长的含硅材料代替鳍的外部部分；在虚拟栅极和外延生长的含硅材料的上方应用旋涂光刻胶，然后去除虚拟栅极的硬掩膜层上方的旋涂光刻胶；蚀刻掉虚拟栅极的硬掩膜和多晶硅，以露出虚拟栅极的栅氧化物，其中，栅氧化物设置在鳍的中间部分的上方；以及穿过设置在鳍的中间部分上方的栅氧化物，将离子注入到鳍的中间部分中。
Description
技术领域
本发明总体上涉及半导体领域，更具体地，涉及调整多阈值电压的FinFET/三栅极沟道掺杂。
背景技术
半导体器件用于大量的电子器件中，例如，电脑、手机等。半导体器件包括集成电路，这些集成电路是通过在半导体晶圆的上方沉积许多类型的薄膜材料和图案化这些薄膜材料以在半导体晶圆上形成集成电路。集成电路包括场效应晶体管(FET)，如金属氧化物半导体(MOS)晶体管。
半导体行业的目标之一是继续缩小单个FET的尺寸和提高单个FET的速度。为实现这些目标，在子32nm的晶体管节点中使用鳍式FET(FinFETs)或多栅极晶体管。FinFETs不仅提高了面密度，而且增强了沟道的栅极控制。
通过使用常规沟道掺杂方法(如，用离子注入和退火)，在22nm的节点几何尺寸的FinFET技术可实行多阈值电压(Vth)。
当鳍形成前使用常规的离子注入时，我们所要面对的挑战之一是，鳍形成之后，由于相对薄的鳍(例如，宽为10nm-15nm和高为30nm-50nm)和大的面容比(至少是部分原因)，使得在后续的工艺步骤中会出现掺杂物损耗。掺杂物损耗可能导致随机掺杂扰动(RDF)，这直接影响了阈值电压可控性。随机掺杂扰动也可能是鳍的宽度/高度发生变化而导致的结果，这样会引起鳍的面容比的变化。
对于块体硅(Si)而言，控制FinFET中的多阈值电压的另一种方法是在形成鳍之后进行离子注入。但是，这种集成方法所要面临的挑战之一是，离子注入之后，需要进行退火步骤以重结晶鳍。对于独立鳍而言，在室温下进行常规离子注入之后，它们是非晶的，用于鳍重结晶的晶种是氧化填充物内部的剩余鳍体。重结晶工艺可能采用高级别的晶格缺陷，这样必然导致鳍内的迁移率退化。
发明内容
为解决上述问题，本发明提供了一种控制鳍式场效应晶体管(FinFET)的阈值电压的方法，包括：在鳍的中间部分的上方形成虚拟栅极，鳍的中间部分设置在鳍的未受虚拟栅极保护的外部部分之间；去除鳍的外部部分并用外延生长的含硅材料代替鳍的外部部分；在虚拟栅极和外延生长的含硅材料的上方涂覆旋涂光刻胶，然后去除虚拟栅极的硬掩膜上方的旋涂光刻胶；蚀刻掉硬掩膜和虚拟栅极的多晶硅，以露出虚拟栅极的栅氧化物，栅氧化物设置在鳍的中间部分的上方；以及穿过设置在鳍的中间部分上方的栅氧化物，将离子注入到鳍的中间部分中。
该方法进一步包括：在注入离子之后，去除剩余的旋涂光刻胶，然后进行退火工艺以重结晶鳍。
该方法进一步包括：在大约25℃到大约600℃之间的温度条件下进行离子注入。
该方法进一步包括：进行退火工艺以重结晶鳍，在离子注入之后立即进行退火工艺。
该方法进一步包括：进行退火工艺以重结晶鳍，当沿着设置在鳍的中间部分上方的栅氧化物设置虚拟隔离件时，进行退火工艺。
该方法进一步包括：进行退火工艺以重结晶鳍，在设置于鳍的中间部分上方的栅氧化物的上方形成保护层之后进行退火工艺。
该方法进一步包括：通过化学下游蚀刻去除虚拟栅极的硬掩膜上方的旋涂光刻胶。
该方法进一步包括：通过干蚀刻、湿蚀刻、化学下游蚀刻、化学氧化去除和它们的组合中的一种工艺，蚀刻掉硬掩膜。
该方法进一步包括：通过干蚀刻、湿蚀刻、化学下游蚀刻和它们的组合中的一种工艺，蚀刻掉虚拟栅极的多晶硅。
该方法进一步包括：在形成虚拟栅极之前，在鳍的中间部分中形成轻掺杂漏极。
其中，外延生长的含硅材料是硅锗(SiGe)。
其中，外延生长的含硅材料是掺杂有碳化物的硅(SiC)、掺杂有磷的硅(SiP)和掺杂有碳和磷的硅(SiCP)中的一种。
此外，还提供了一种控制鳍式场效应晶体管(FinFET)的阈值电压的方法，包括：在鳍的中间部分的上方形成虚拟栅极，鳍的中间部分设置在鳍的未受虚拟栅极保护的外部部分之间；去除鳍的外部部分并用外延生长的含硅材料代替鳍的外部部分；在虚拟栅极和外延生长的含硅材料的上方涂覆旋涂光刻胶，然后去除虚拟栅极的硬掩膜上方的旋涂光刻胶；蚀刻掉硬掩膜和虚拟栅极的多晶硅的一部分，以露出虚拟栅极的栅氧化物并形成多晶硅隔离件，栅氧化物设置在鳍的中间部分的上方；以及穿过设置在鳍的中间部分上方的栅氧化物，将离子注入到鳍的中间部分中。
该方法进一步包括：在大约25℃到大约600℃之间的温度条件下进行离子注入。
该方法进一步包括：进行退火工艺以重结晶鳍，在离子注入之后立即进行退火工艺。
该方法进一步包括：进行退火工艺以重结晶鳍，在去除多晶硅隔离件之前进行退火工艺。
此外，还提供了一种控制鳍式场效应晶体管(FinFET)的阈值电压的方法，包括：在鳍的中间部分的上方形成虚拟栅极；用外延生长的含硅材料代替鳍的未受虚拟栅极保护的外部部分；在虚拟栅极和外延生长的含硅材料的上方涂覆旋涂光刻胶，然后去除虚拟栅极的硬掩膜上方的旋涂光刻胶；蚀刻掉硬掩膜和虚拟栅极的多晶硅，以露出虚拟栅极的栅氧化物，栅氧化物设置在鳍的中间部分的上方；
穿过设置在鳍的中间部分上方的栅氧化物，将离子注入到鳍的中间部分中；以及
进行退火工艺以重结晶鳍。
该方法进一步包括：在注入离子之后，去除剩余的旋涂光刻胶，然后在大约25℃到大约600℃之间的温度条件下进行离子注入。
该方法进一步包括：在离子注入之后，立即进行退火工艺。
该方法进一步包括：在设置于鳍的所述中间部分上方的所述栅氧化物的上方形成虚拟隔离件和保护层中的至少一个之后，进行所述退火工艺。
附图说明
为了更全面地理解实施例及其优势，现将结合附图所进行的描述作为参考，其中：
图1示出了实施例FinFET；
图2A-图2C示出了当露出虚拟栅极的硬掩膜时的图1中所示的实施例FinFET的截面图和顶视图；
图3A-图3C示出了在去除虚拟栅极的硬掩膜之后的图2A-图2C中所示的实施例FinFET的截面图和顶视图；
图4A-图4C示出了去除虚拟栅极的多晶硅之后的图3A-图3C中所示的实施例FinFET的截面图和顶视图；
图5A-图5C示出了离子注入工艺过程中的图4A-图4C中所示的实施例FinFET的截面图和顶视图；
图6A-图6C示出了去除任何剩余旋涂光刻胶之后的图5A-图5C中所示的实施例FinFET的截面图和顶视图；
图7A-图7C示出了进行退火工艺以修补鳍内的残留损伤之后的图6A-图6C中所示的实施例FinFET的截面图和顶视图；
图8A-图8C示出了去除虚拟栅极的多晶硅的一部分以形成隔离件之后的图3A-图3C中所示的实施例FinFET的截面图和顶视图；
图9A-图9C示出了在离子注入工艺过程中的图8A-图8C中所示实施例FinFET的截面图和顶视图；
图10A-图10C示出了去除任意剩余旋涂光刻胶之后的图9A-图9C中所示的实施例FinFET的截面图和顶视图；
图11A-图11C示出了进行退火工艺以修补鳍内残留损伤之后的图10A-图10C中所示的实施例FinFET的截面图和顶视图；
图12A-图12C示出了去除隔离件之后的图11A-图11C中所示的实施例FinFET的截面图和顶面图；
图13示出了在鳍式场效应晶体管(FinFET)中控制阈值电压的方法；
图14示出了在鳍式场效应晶体管(FinFET)中控制阈值电压的方法；以及
图15示出了在鳍式场效应晶体管(FinFET)中控制阈值电压的方法。
除非另有说明，否则不同图中的相应数字和符号常常表示相应的部分。绘制的图只用于清楚地说明实施例的相关方面，因此无需按比例绘制。
具体实施方式
下面，详细讨论本发明各实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式，而不用于限制本发明的范围。
根据具体环境中的实施例来描述本发明，即，FinFET。但是，本发明也可应用于其他集成电路、电子结构等中。
现参见图1，其示出了实施例FinFET10。本文的实施例FinFET10指代且表示双栅极器件和三栅极器件。如图所示，实施例FinFET10包括支撑设置在绝缘体16中的鳍14的衬底12。在一个实施例中，衬底12和鳍14的低部是块体硅或含硅材料。在一个实施例中，绝缘体16是氧化物或表示浅沟道隔离(STI)区。
突出于绝缘体16的表面的鳍14包括位于外部部分20之间的中间部分18。如图1所示，虚拟栅极22保护中间部分18。反之，表示FinFET10的源极和漏极的外部部分20通常不受虚拟栅极22的保护但是邻近虚拟栅极22。
在一个实施例中，最初由块体硅形成的鳍14的外部部分20被去除且由外延生长的含硅材料24代替。在一个实施例中，外延生长的含硅材料24包括用于p型FinFET(亦称pFET)的硅锗(SiGe)。在一个实施例中，外延生长的含硅材料24包括用于n型FinFET(亦称nFET)的重掺杂碳的硅(SiC)、重掺杂磷的硅(SiP)、或两者的组合(SiCP)。
仍参见图1，在虚拟栅极22的对侧上设置隔离件26。如图所示，隔离件26通常沿任何一侧的长度方向靠近虚拟栅极22的侧面。此外，每个隔离件26的一部分越过鳍14的顶部。在一个实施例中，由氮化物或其他合适的隔离件材料形成隔离件26。
图2A-图2B示出了通常分别沿A-A线和B-B线切开的图1中所示的实施例FinFET10的截面图。图2C示出了图1中所示的FinFET10的顶视图。如图2A-图2C共同所示，在一个实施例中，虚拟栅极22包括栅氧化物28、多晶硅层30和硬掩膜层32。如图2B所示，虚拟栅极22的栅氧化物28封装或覆盖鳍14的中间部分18。在一个实施例中，在鳍14中形成轻掺杂漏极且至少部分轻掺杂漏极受虚拟栅极22的栅氧化物28保护。
现参见图2A-图2C，用以提高阈值电压良好控制的沟道掺杂FinFET10的工艺流开始。实际上，旋涂用栅氧化物28包裹鳍14的中间部分18以及用外延生长的含硅材料24(如，硅锗、碳化硅等)代替形成鳍14的外部部分20的块体硅后，应用旋涂光刻胶34。之后，适当地开槽或去除旋涂光刻胶34，以露出图2A中所示的虚拟栅极22的硬掩膜层32。在一个实施例中，通过化学下游蚀刻(CDE)去除硬掩膜32上方的旋涂光刻胶34。
现参见图3A-图3C，露出后，去除图2A-图2C中所示的硬掩膜层32。在一个实施例中，通过蚀刻去除硬掩膜32。在一个实施例中，通过干蚀刻、湿蚀刻、化学下游蚀刻(CDE)、化学氧化去除(COR)和其组合中的一种，蚀刻掉硬掩膜32。通过去除硬掩膜32，露出下层多晶硅层30。
现参见图4A-图4C，去除图2A-图2C所示的硬掩膜32之后，去除多晶硅层30。在一个实施例中，通过干蚀刻、湿蚀刻、化学下游蚀刻(CDE)、和其组合中的一种，去除虚拟栅极22的多晶硅层30。通过去除多晶硅层30，露出保护鳍14的中间部分18的栅氧化物28。
现参见图5A-图5C，去除图4A-图4C中所示的多晶硅层30且露出栅氧化物28之后，进行离子注入36。实际上，穿过设置在鳍14的中间部分18上方的栅氧化物28，将离子注入到鳍14的中间部分18中。在一个实施例中，在温度范围介于大约25℃(如，室温)到大约600℃之间进行离子注入36。在一个实施例中，离子注入36采用n型掺杂物或p型掺杂物。在一个实施例中，离子注入36具有正入射，即，离子束垂直于晶圆表面。在一个实施例中，离子注入36具有角度入射或倾斜入射。实际上，可以使用不同角度将掺杂物原子设置在需要的位置。
由于注入鳍14的中间部分18的离子必须穿过栅氧化物28，所以，可以更准确地控制掺杂物等级或浓度。此外，由于使用后鳍掺杂集成方案，所以掺杂物损耗会更少。换句话说，在离子注入36和通过后栅极集成方案实现完全填充之间存在更少的工艺步骤。
现参见图6A-图6C，离子注入36之后，去除剩余的任意旋涂光刻胶34(参见图5A-图5C)。之后，参见图7A-图7C，进行退火工艺38以修补鳍14内的残留损伤。在一个实施例中，在温度范围介于大约800℃到大约1200℃之间，进行退火工艺38，时间介于大约1微秒(μs)至大约10秒(s)之间。在一个实施例中，离子注入36之后，立即进行退火工艺38，以试图修补鳍14的损伤以及活化掺杂原子。
现参见图8A-图8C，不去除图3A-图3C所示的整个多晶硅层30，而只去除多晶硅层30的一部分，以形成多晶硅隔离件40。如图所示，多晶硅隔离件40靠近栅氧化物28且用于保护鳍14的中间部分18。现参见图9A-图9C，在形成多晶硅隔离件40之后，进行离子注入36。像之前那样，穿过设置在鳍14的中间部分18上方的栅氧化物28，将离子注入到鳍14的中间部分18中。
现参见图10A-图10C，在离子注入36之后，去除剩余的任何旋涂光刻胶34(参见图9A-图9C)。之后，如图11A-图11C所示，进行退火工艺38以修补鳍14内的残留损伤。在一个实施例中，多晶硅隔离件40最小化了退火工艺过程中的掺杂物损耗。例如，在形成多晶硅隔离件40之后，使用具有正入射的离子注入，鳍14和多晶硅隔离件40均掺杂有大约相同的掺杂物浓度。与不使用多晶硅隔离件40相比，在退火工艺过程中，掺杂外的扩散被抑制。因此，允许使用更少的注入剂量，以实现鳍14中的相同掺杂浓度。
接着，如图12A-图12C所示，去除多晶硅隔离件40。在一个实施例中，通过干蚀刻、湿蚀刻、化学下游蚀刻、和其组合中的一种，去除多晶硅隔离件40。
在一个实施例中，在图5A-图5C中所示的离子注入36后，在进行如图7A-图7C中所示的退火工艺38之前，可在栅氧化物28的上方形成虚拟多晶硅层30(例如，如图3A-图3C)，以试图防止鳍14受到残留损伤。在一个实施例中，可能会形成这样的虚拟多晶硅层30，而不会形成多晶硅隔离件40。
现参见图13，其示出了控制FinFET10中阈值电压的实施例方法42。在方框44中，在鳍14的中间部分的上方形成虚拟栅极22。如图1所示，鳍14的中间部分18设置在未受虚拟栅极22保护的鳍的外部部分20之间。在方框46中，鳍14的外部部分20被去除且由外延生长的含硅材料24代替。
在方框48中，在虚拟栅极22和外延生长的含硅材料24的上方应用旋涂光刻胶34，然后去除虚拟栅极22的硬掩膜层32上方的旋涂光刻胶34。在方框50中，蚀刻掉虚拟栅极22的硬掩膜层32和多晶硅层30，以露出虚拟栅极22的栅氧化物28。如图1所示，栅氧化物28设置在鳍14的中间部分18的上方。在方框52中，穿过设置在鳍14的中间部分18上方的栅氧化物28，将离子注入到鳍14的中间部分18中。如上述，离子注入之后，可去除任何剩余的旋涂光刻胶34，并且可进行用于修补鳍内残留损伤的退火工艺。
现参见图14，其示出了控制FinFET10内阈值电压的实施例方法54。在方框56中，在鳍14的中间部分的上方形成虚拟栅极22。如图1所示，鳍14的中间部分18设置在未受虚拟栅极22保护的鳍的外部部分20之间。在方框58中，鳍14的外部部分20被去除且由外延生长的含硅材料24代替。
在方框60中，在虚拟栅极22和外延生长的含硅材料24的上方应用旋涂光刻胶34，然后去除虚拟栅极22的硬掩膜层32上方的旋涂光刻胶34。在方框62中，蚀刻掉虚拟栅极22的硬掩膜层32和多晶硅层30的一部分，以露出虚拟栅极22的栅氧化物28和形成多晶硅隔离件40。如图1所示，栅氧化物28设置在鳍14的中间部分18的上方。在方框64中，穿过设置在鳍14的中间部分18上方的栅氧化物28，将离子注入到鳍14的中间部分18中。如上所述，注入离子之后，可去除任意剩余的旋涂光刻胶34，并且可进行修补鳍14内残留损伤的退火工艺。
现参见图15，其示出了控制FinFET10内阈值电压的实施例方法66。在方框68中，在鳍14的中间部分的上方形成虚拟栅极22。如图1所示，鳍14的中间部分18设置在未受虚拟栅极22保护的鳍的外部部分20之间。在方法70中，鳍14的外部部分20被去除且由外延生长的含硅材料24代替。
在方框72中，在虚拟栅极22和外延生长的含硅材料24的上方应用旋涂光刻胶34，然后去除虚拟栅极22的硬掩膜层32上方的旋涂光刻胶34。在方框74中，蚀刻掉虚拟栅极22的硬掩膜层32和多晶硅层30的一部分，以露出虚拟栅极22的栅氧化物28和形成多晶硅隔离件40。如图1所示，栅氧化物28设置在鳍14的中间部分18的上方。在方框76中，穿过设置在鳍14的中间部分18上方的栅氧化物28，将离子注入到鳍14的中间部分18中。在方框78中，可进行修补鳍14内残留损伤的退火工艺。
综上所述，应该了解，形成本发明中的实施例FinFET10的一个或多个工艺提供了诸多优点。例如，可精确地控制鳍14内的掺杂物等级或浓度。这是因为(至少是部分原因)用栅氧化物28的薄层、虚拟多晶硅隔离件40、和/或新的虚拟多晶硅层(未示出)封装或保护鳍14。并且，使用虚拟多晶硅隔离件40和/或新的虚拟多晶硅层(未示出)可更好地封装或保护鳍14。此外，形成实施例FinFET10的工艺允许用于pFETs的epi-SixGey鳍以及用于nFETs的epi-SixCy、SiP和SiCP鳍保留应力。
控制鳍式场效应晶体管(FinFET)的阈值电压的实施例方法包括：在鳍的中间部分的上方形成虚拟栅极，鳍的中间部分设置在未受虚拟栅极保护的鳍的外部部分之间；去除鳍的外部部分且用外延生长的含硅材料代替鳍的外部部分；在虚拟栅极和外延生长的含硅材料的上方涂覆旋涂光刻胶，然后去除虚拟栅极的硬掩膜层上方的旋涂光刻胶；蚀刻掉虚拟栅极的硬掩膜和多晶硅以露出虚拟栅极的栅氧化物，栅氧化物设置在鳍的中间部分的上方；以及穿过设置在鳍的中间部分的上方的栅氧化层，将离子注入到鳍的中间部分中。
控制鳍式场效应晶体管(FinFET)的阈值电压的实施例方法包括：在鳍的中间部分的上方形成虚拟栅极，鳍的中间部分设置在未受虚拟栅极保护的鳍的外部部分之间；去除鳍的外部部分且用外延生长的含硅材料代替鳍的外部部分；在虚拟栅极和外延生长的含硅材料的上方涂覆旋涂光刻胶，然后去除虚拟栅极的硬掩膜层上方的旋涂光刻胶；蚀刻掉虚拟栅极的硬掩膜层和多晶硅层的一部分以露出虚拟栅极的栅氧化物和形成多晶硅隔离件，其中，栅氧化物设置在鳍的中间部分的上方；以及穿过设置在鳍的中间部分的上方的栅氧化物，将离子注入到鳍的中间部分中。
控制鳍式场效应晶体管(FinFET)内阈值电压的实施例方法包括：在鳍的中间部分的上方形成虚拟栅极；用外延生长的含硅材料代替未受虚拟栅极保护的鳍的外部部分；在虚拟栅极和外延生长的含硅材料的上方涂覆旋涂光刻胶，然后去除虚拟栅极的硬掩膜层上方的旋涂光刻胶；蚀刻掉虚拟栅极的硬掩膜层和多晶硅层以露出虚拟栅极的栅氧化物，栅氧化物设置在鳍的中间部分的上方；穿过设置在鳍的中间部分的上方的栅氧化物，将离子注入到鳍的中间部分中；以及进行退火工艺以使鳍重结晶。
虽然本发明提供了示出的实施例，但是，本说明并不构成限制意义。参考本说明，示出的实施例的不同修改和组合以及其他实施例对本领域的技术人员来说是显而易见的。因此，所附权利要求包括任何这样的修改或实施例。
Claims (18)
1.一种控制鳍式场效应晶体管(FinFET)的阈值电压的方法，包括：
在鳍的中间部分的上方形成虚拟栅极，所述鳍的所述中间部分设置在所述鳍的未受所述虚拟栅极保护的外部部分之间；
去除所述鳍的所述外部部分并用外延生长的含硅材料代替所述鳍的所述外部部分；
在所述虚拟栅极和所述外延生长的含硅材料的上方涂覆旋涂光刻胶，然后去除所述虚拟栅极的硬掩膜上方的所述旋涂光刻胶；
蚀刻掉所述硬掩膜和所述虚拟栅极的多晶硅，以露出所述虚拟栅极的栅氧化物，所述栅氧化物设置在所述鳍的所述中间部分的上方；
穿过设置在所述鳍的所述中间部分上方的所述栅氧化物，将离子注入到所述鳍的所述中间部分中；以及
进行退火工艺以重结晶所述鳍，当沿着设置在所述鳍的所述中间部分上方的所述栅氧化物设置虚拟隔离件时，进行所述退火工艺。
2.根据权利要求1所述的方法，进一步包括：在注入所述离子之后，去除剩余的旋涂光刻胶，然后进行退火工艺以重结晶所述鳍。
3.根据权利要求1所述的方法，进一步包括：在25℃到600℃之间的温度条件下进行离子注入。
4.根据权利要求1所述的方法，进一步包括：进行退火工艺以重结晶所述鳍，在离子注入之后立即进行所述退火工艺。
5.根据权利要求1所述的方法，进一步包括：进行退火工艺以重结晶所述鳍，在设置于所述鳍的所述中间部分上方的所述栅氧化物的上方形成保护层之后进行所述退火工艺。
6.根据权利要求1所述的方法，进一步包括：通过化学下游蚀刻去除所述虚拟栅极的所述硬掩膜上方的所述旋涂光刻胶。
7.根据权利要求1所述的方法，进一步包括：通过干蚀刻、湿蚀刻、化学下游蚀刻、化学氧化去除和它们的组合中的一种工艺，蚀刻掉所述硬掩膜。
8.根据权利要求1所述的方法，进一步包括：通过干蚀刻、湿蚀刻、化学下游蚀刻和它们的组合中的一种工艺，蚀刻掉所述虚拟栅极的所述多晶硅。
9.根据权利要求1所述的方法，进一步包括：在形成所述虚拟栅极之前，在所述鳍的所述中间部分中形成轻掺杂漏极。
10.根据权利要求1所述的方法，其中，所述外延生长的含硅材料是硅锗(SiGe)。
11.根据权利要求1所述的方法，其中，所述外延生长的含硅材料是掺杂有碳化物的硅(SiC)、掺杂有磷的硅(SiP)和掺杂有碳和磷的硅(SiCP)中的一种。
12.一种控制鳍式场效应晶体管(FinFET)的阈值电压的方法，包括：
在鳍的中间部分的上方形成虚拟栅极，所述鳍的所述中间部分设置在所述鳍的未受所述虚拟栅极保护的外部部分之间；
去除所述鳍的所述外部部分并用外延生长的含硅材料代替所述鳍的所述外部部分；
在所述虚拟栅极和所述外延生长的含硅材料的上方涂覆旋涂光刻胶，然后去除所述虚拟栅极的硬掩膜上方的所述旋涂光刻胶；
蚀刻掉所述硬掩膜和所述虚拟栅极的多晶硅的一部分，以露出所述虚拟栅极的栅氧化物并形成多晶硅隔离件，所述栅氧化物设置在所述鳍的所述中间部分的上方；以及
穿过设置在所述鳍的所述中间部分上方的所述栅氧化物，将离子注入到所述鳍的所述中间部分中。
13.根据权利要求12所述的方法，进一步包括：在25℃到600℃之间的温度条件下进行离子注入。
14.根据权利要求12所述的方法，进一步包括：进行退火工艺以重结晶所述鳍，在离子注入之后立即进行所述退火工艺。
15.根据权利要求12所述的方法，进一步包括：进行退火工艺以重结晶所述鳍，在去除所述多晶硅隔离件之前进行所述退火工艺。
16.一种控制鳍式场效应晶体管(FinFET)的阈值电压的方法，包括：
在鳍的中间部分的上方形成虚拟栅极；
用外延生长的含硅材料代替所述鳍的未受所述虚拟栅极保护的外部部分；
在所述虚拟栅极和所述外延生长的含硅材料的上方涂覆旋涂光刻胶，然后去除所述虚拟栅极的硬掩膜上方的所述旋涂光刻胶；
蚀刻掉所述硬掩膜和所述虚拟栅极的多晶硅，以露出所述虚拟栅极的栅氧化物，所述栅氧化物设置在所述鳍的所述中间部分的上方；
穿过设置在所述鳍的所述中间部分上方的所述栅氧化物，将离子注入到所述鳍的所述中间部分中；
在设置于所述鳍的所述中间部分上方的所述栅氧化物的上方形成虚拟隔离件和保护层中的至少一个；以及
进行退火工艺以重结晶所述鳍。
17.根据权利要求16所述的方法，进一步包括：在注入所述离子之后，去除剩余的旋涂光刻胶，其中，在25℃到600℃之间的温度条件下进行所述离子注入。
18.根据权利要求16所述的方法，进一步包括：在离子注入之后，立即进行所述退火工艺。
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| US9685368B2 (en) | 2015-06-26 | 2017-06-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure having an etch stop layer over conductive lines |
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| US9583623B2 (en) | 2015-07-31 | 2017-02-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device including fin structures disposed over buffer structures and manufacturing method thereof |
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| US10032873B2 (en) | 2015-09-15 | 2018-07-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of forming the same |
| DE102016113434B4 (de) | 2015-09-15 | 2020-11-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Halbleitervorrichtung und Verfahren zum Ausbilden von dieser |
| US9647122B2 (en) | 2015-09-15 | 2017-05-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of forming the same |
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| US9960273B2 (en) | 2015-11-16 | 2018-05-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit structure with substrate isolation and un-doped channel |
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| US10490552B2 (en) | 2015-12-29 | 2019-11-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET device having flat-top epitaxial features and method of making the same |
| DE102016119024B4 (de) | 2015-12-29 | 2023-12-21 | Taiwan Semiconductor Manufacturing Co. Ltd. | Verfahren zum Herstellen einer FinFET-Vorrichtung mit epitaktischen Elementen mit flacher Oberseite |
| US9825036B2 (en) | 2016-02-23 | 2017-11-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and method for semiconductor device |
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| US10008414B2 (en) | 2016-06-28 | 2018-06-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | System and method for widening Fin widths for small pitch FinFET devices |
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| US9640540B1 (en) | 2016-07-19 | 2017-05-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and method for an SRAM circuit |
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