CN103928345B - Ion implanting forms the UMOSFET preparation method of N-type heavy doping drift layer table top - Google Patents

Abstract

The invention relates to a method for preparing a UMOSFET device by ion implantation to form an N-type heavily doped drift layer mesa. The N-type drift region is epitaxially grown; the ion implantation forms an N+ well; the N+ well is etched into a mesa; the epitaxially grows a P-epitaxial layer; Grow N+ source region layer; etch into groove; etch to form source region; oxidize to form groove gate; deposit polysilicon; open contact hole: prepare passivation layer, open electrode contact hole; prepare electrode: evaporate metal, prepare electrode. The invention improves the doping concentration of the N-type drift region mesa in the silicon carbide UMOSFET device with the N-type drift layer mesa through the ion implantation and etching process, and reduces the on-resistance of the device.

Description

UMOSFET preparation method for forming N-type heavily doped drift layer mesa by ion implantation

technical field

The invention relates to the technical field of microelectronics, in particular to a method for preparing a silicon carbide UMOSFET device for forming an N-type heavily doped drift layer mesa by ion implantation.

Background technique

The third-generation semiconductor material silicon carbide has excellent physical and chemical properties such as wide band gap, high critical breakdown electric field, high electron saturation drift velocity and high thermal conductivity, and has great potential in high temperature, high pressure and high power semiconductor devices. Advantage.

As a switch, the power MOSFET has a contradictory relationship between its forward conduction resistance and reverse breakdown voltage, while the UMOSFET of the vertical structure eliminates the parasitic accumulation layer resistance and JFET resistance, so the UMOSFET has an advantage compared with the MOSFET of the horizontal structure in this respect. Certain advantages.

UMOSFET itself also has disadvantages. The electric field concentration effect at the corner of the groove gate leads to early breakdown of the device, which reduces the reliability of the device. A SiC UMOSFET device with an N-drift layer mesa that can reduce the electric field at the corner of the trench gate has been invented. The P-epitaxial layer of the device wraps the corner of the trench gate, and the SiC PN junction interface replaces the corner SiO ₂ / The SiC interface is used to withstand the reverse voltage, which improves the reliability of the device.

However, in this scheme, the P-epitaxial layer wraps the corners of the groove gate, which narrows the conductive path at the mesa, and the impurity concentration at the mesa is equal to the concentration of the drift layer, and the doping concentration is low, which is not good for the on-resistance the elements of.

In view of the above-mentioned defects, the author of the present invention has finally obtained this creation through long-term research and practice.

Contents of the invention

The object of the present invention is to provide a UMOSFET preparation method for forming N-type heavily doped drift layer mesa by ion implantation, so as to overcome the above-mentioned technical defects.

In order to achieve the above object, the present invention provides a UMOSFET preparation method for forming an N-type heavily doped drift layer mesa by ion implantation, the specific process is:

Step a, epitaxial growth of N-type drift region: epitaxially grow N on the silicon carbide N+ substrate sample with a thickness of about 12 μm to 25 μm and a nitrogen ion doping concentration of 1×10 ¹⁵ cm ^-3 to 5×10 ¹⁵ cm ^-3 Type drift zone;

Step b, ion implantation to form an N+ well: perform ion implantation in the N-type drift region to form a heavily doped N+ well, the width of the N+ well is 3 μm to 4 μm, the implanted impurities are nitrogen ions, the depth is 0.5 μm, and the doping concentration is 1×10 ¹⁷ cm ⁻³ ;

Step c, etching the N+ well into a mesa: etching the N+ well into a mesa, the height of the mesa is equal to the depth of the N+ well, and the width of the mesa is equal to the width of the well;

Step d, epitaxially growing a P- epitaxial layer: growing a P- epitaxial layer on the N-type drift region and N+ drift layer mesa, with a thickness of 3 μm and an aluminum ion doping concentration of 5×10 ¹⁷ cm ^-3 to 1×10 ¹⁸ cm ^-3 ;

Step e, epitaxially growing an N+ source region layer: growing an N+ source region layer on the P- epitaxial layer with a thickness of 0.5 μm and a doping concentration of 5×10 ¹⁸ cm ⁻³ ;

Step f, etching to form a groove: use ICP etching to form a groove directly above the N-type heavily doped drift layer mesa, with a width of 6 μm and a depth of 3 μm, so that the two bottom corners of the groove are wrapped by the P- epitaxial layer;

Step g, etching to form a source region: using ICP etching to form a source region contact;

Step h, oxidize to form the groove gate: prepare the groove gate dielectric SiO ₂ through a thermal oxidation process, with a thickness of 100 nm.

Step i, depositing polysilicon: depositing a polySi layer on the trench gate dielectric _SiO2 in the trench gate;

Step j, opening a contact hole: preparing a passivation layer, and opening an electrode contact hole;

Step k, preparing electrodes: evaporating metals to prepare electrodes.

Further, in the above step a, the N-type silicon carbide substrate is firstly cleaned by RCA standard, and then epitaxially grown on the entire substrate with a thickness of 12 μm to 25 μm and a nitrogen ion doping concentration of 1×10 ¹⁵ cm ^-3 to 5×10 ¹⁵ cm ^-3 N-drift layer, the process conditions are: temperature 1600 ℃, pressure 100mbar, reaction gas using silane and propane, carrier gas using pure hydrogen, dopant source using liquid nitrogen.

Further, the specific process of the above step b is:

In step b01, a layer of SiO ₂ with a thickness of 0.2 μm is deposited on the entire surface of silicon carbide by low-pressure chemical vapor deposition, and Al with a thickness of 1 μm is deposited as a barrier layer for nitrogen ion implantation. Form the N+ well implantation region, the width of the N+ well implantation region is 3-4 μm;

In step b02, perform nitrogen ion implantation three times at an ambient temperature of 500°C. The implantation energies are 520keV, 300keV, and 150keV respectively, and the corresponding doses are 9.8×10 ¹¹ cm ^-2 , 7×10 ¹¹ cm ^-2 , 4.9×10 ¹¹ cm ^-2 , the injection depth is 0.5μm;

In step b03, standard RCA is used to clean the surface of the silicon carbide, and protect it with a C film after drying. Then ion-activated annealing was performed at 1750° C. in an argon atmosphere for 15 minutes.

Further, in the above step c, the width of the N+ well is 3 μm to 4 μm, the implanted impurities are nitrogen ions, the depth is 0.5 μm, and the doping concentration is 1×10 ¹⁷ cm ^-3 , the process conditions are: implantation temperature 500°C, ion activation The annealing temperature is 1750°C, and the annealing time is 10min.

Further, in the above step d, a P- epitaxial layer is grown on the N-type drift region and the N+ drift layer mesa, with a thickness of 3 μm and an aluminum ion doping concentration of 5×10 ¹⁷ cm ^-3 to 1×10 ¹⁸ cm ^{- 3} ; The N+ well is etched into a mesa, and the height of the mesa is equal to the width of the N+ well. The process conditions are: ICP coil power 850W, source power 100W, and reaction gases SF ₆ and O ₂ are 48 sccm and 12 sccm respectively.

Further, in the above step e, an N-type silicon carbide epitaxial layer with a thickness of 0.5 μm and a nitrogen ion doping concentration of 5×10 ¹⁸ cm ^-3 is grown on the P- epitaxial layer as the N+ source region layer, which The process conditions are as follows: the temperature is 1600°C, the pressure is 100mbar, the reaction gas is silane and propane, the carrier gas is pure hydrogen, and the dopant source is liquid nitrogen.

Further, in the above step f, at first magnetron sputtering a layer The Ti film is used as an ICP etching mask, and then coated with photolithography, and then ICP etching is performed. The width of the etched groove is 6 μm, and the depth is 3 μm. Finally, the glue is removed, the etching mask is removed, and the optical film is cleaned; The conditions are: ICP coil power 850W, source power 100W, reaction gas _SF6 and _O2 are 48sccm and 12sccm, respectively.

Further, in the above step g, at first magnetron sputtering a layer The Ti film is used as an ICP etching mask, and then coated with photolithography, and then ICP is etched to form a contact hole in the source area. Finally, the glue is removed, the etching mask is removed, and it is cleaned into a light sheet; the process conditions are: ICP coil power 850W , source power 100W, reaction gas SF ₆ and O ₂ were 48sccm and 12sccm.

Further, in the above step h, the dry oxygen process is used to prepare the SiO ₂ gate at 1150°C with a thickness of 100nm, and then annealing is performed at 1050°C under N ₂ atmosphere to reduce the surface roughness of the SiO ₂ film.

Further, in the above step i, low-pressure hot-wall chemical vapor deposition is used to grow polySi to fill the trenches, the deposition temperature is 600-650°C, the deposition pressure is 60-80Pa, and the reaction gases are silane and phosphine , the carrier gas is helium, and then glue photolithography, etch the polySi layer to form a polysilicon gate, and finally remove the glue and clean.

Compared with the prior art, the present invention has the beneficial effects that: the present invention improves the doping concentration of the N-type drift region mesa in the silicon carbide UMOSFET device with the N-type drift layer mesa through the ion implantation and etching process, and reduces the The on-resistance of the device; the ion implantation process can precisely control the concentration and depth of implanted ions. In addition, for the base material, ion implantation has no obvious interface, so there is no problem of adhesion cracking and peeling, and ion implantation does not waste materials cut costs.

Description of drawings

Fig. 1 is the structural representation of the silicon carbide UMOSFET device with N-type drift layer mesa of the present invention;

Fig. 2 is a flow chart of the manufacturing process of the silicon carbide UMOSFET device with N-type drift layer mesa according to the present invention.

detailed description

The above and other technical features and advantages of the present invention will be described in more detail below in conjunction with the accompanying drawings.

Please refer to Figure 2, which is a schematic structural diagram of a silicon carbide UMOSFET device with an N-type drift layer mesa according to the present invention, and the specific process is:

Step a, epitaxial growth of N-type drift region: epitaxially grow N on the silicon carbide N+ substrate sample with a thickness of about 12 μm to 25 μm and a nitrogen ion doping concentration of 1×10 ¹⁵ cm ^-3 to 5×10 ¹⁵ cm ^-3 Type drift zone;

Step b, ion implantation to form an N+ well: perform ion implantation in the N-type drift region to form a heavily doped N+ well, the width of the N+ well is 3 μm to 4 μm, the implanted impurities are nitrogen ions, the depth is 0.5 μm, and the doping concentration is 1×10 ¹⁷ cm ⁻³ ;

Step c, etch the N+ well into a mesa: etch the N+ well into a mesa, the height of the mesa is equal to the depth of the N+ well, the width of the N+ well is 3 μm to 4 μm, the implanted impurities are nitrogen ions, the depth is 0.5 μm, and the doping concentration 1×10 ¹⁷ cm ^-3 , and the process conditions are: implantation temperature 500°C, ion activation annealing temperature 1750°C, annealing time 10min.

Step d, epitaxially growing a P- epitaxial layer: growing a P- epitaxial layer on the N-type drift region and N+ drift layer mesa, with a thickness of 3 μm and an aluminum ion doping concentration of 5×10 ¹⁷ cm ^-3 to 1×10 ¹⁸ cm ^-3 ; the N+ well is etched into a mesa, and the height of the mesa is equal to the width of the N+ well. The process conditions are: ICP coil power 850W, source power 100W, reaction gas SF ₆ and O ₂ respectively 48sccm and 12sccm.

Step e, epitaxially growing an N+ source region layer: growing an N+ source region layer on the P- epitaxial layer with a thickness of 0.5 μm and a doping concentration of 5×10 ¹⁸ cm ⁻³ ;

Step f, etching to form a groove: use ICP etching to form a groove directly above the N-type heavily doped drift layer mesa, with a width of 6 μm and a depth of 3 μm, so that the two bottom corners of the groove are wrapped by the P- epitaxial layer;

Step g, etching to form a source region: using ICP etching to form a source region contact;

Step h, oxidize to form the groove gate: prepare the groove gate dielectric SiO ₂ through a thermal oxidation process, with a thickness of 100 nm.

Step i, depositing polysilicon: depositing a polySi layer on the trench gate dielectric _SiO2 in the trench gate;

Step j, opening a contact hole: preparing a passivation layer, and opening an electrode contact hole;

Step k, preparing electrodes: evaporating metals to prepare electrodes.

Each embodiment based on above-mentioned steps, as follows:

Embodiment one:

Step a1, epitaxially growing an N-type drift region, as shown in a in FIG. 2 ;

RCA standard cleaning is performed on the N-type silicon carbide substrate first, and then an N-drift layer with a thickness of 12 μm and a nitrogen ion doping concentration of 1×10 ¹⁵ cm ^-3 is epitaxially grown on the entire substrate. The process conditions are: The temperature is 1600°C, the pressure is 100mbar, the reaction gas is silane and propane, the carrier gas is pure hydrogen, and the dopant source is liquid nitrogen.

Step b1, ion implantation to form an N+ well, as shown in b in Figure 2;

In step b11, a layer of SiO ₂ with a thickness of 0.2 μm is deposited on the entire surface of silicon carbide by low-pressure chemical vapor deposition, and Al with a thickness of 1 μm is deposited as a barrier layer for nitrogen ion implantation. Form the N+ well implantation region, the width of the N+ well implantation region is 3 μm;

In step b12, nitrogen ion implantation was performed three times at an ambient temperature of 500°C. The implantation energies were 520keV, 300keV, and 150keV respectively, and the corresponding doses were 9.8×10 ¹¹ cm ^-2 , 7×10 ¹¹ cm ^-2 , 4.9×10 ¹¹ cm ^-2 , the injection depth is 0.5μm;

In step b13, standard RCA is used to clean the surface of the silicon carbide, and protect it with a C film after drying. Then ion-activated annealing was performed at 1750° C. in an argon atmosphere for 15 minutes.

In step c1, the N+ well is etched into a mesa, as shown in c in FIG. 2 ;

First magnetron sputtering a layer The Ti film is used as an ICP etching mask, and then photolithography is applied to perform ICP etching, and the N+ well is etched into a mesa structure, and the height of the mesa is equal to the depth of the N+ well. Finally, the glue is removed, the etching mask is removed, and it is cleaned into a light sheet. The ICP etching process conditions are: ICP coil power 850W, source power 100W, reaction gas SF ₆ and O ₂ are 48 sccm and 12 sccm respectively.

Step d1, epitaxially growing a P- epitaxial layer, as shown in d in FIG. 2 ;

A P-epitaxial layer with a thickness of 3 μm and an aluminum ion doping concentration of 5×10 ¹⁷ cm ^-3 is grown on the N-type drift region and the heavily doped drift region mesa. The epitaxial growth process conditions are: the temperature is 1600 °C, the pressure is 100mbar, the reaction gas is silane and propane, the carrier gas is pure hydrogen, and the dopant source is trimethylaluminum.

Step e1, epitaxially growing the N+ source region layer, as shown in e in FIG. 2 ;

An N-type silicon carbide epitaxial layer with a thickness of 0.5 μm and a nitrogen ion doping concentration of 5×10 ¹⁸ cm ^-3 is grown on the P- epitaxial layer as the N+ source region layer. The process conditions are: the temperature is 1600°C , the pressure is 100mbar, the reaction gas is silane and propane, the carrier gas is pure hydrogen, and the dopant source is liquid nitrogen.

Step f1, etching into grooves, as shown in f in Figure 2;

First magnetron sputtering a layer The Ti film is used as an ICP etching mask, and then coated with photolithography, and then ICP etching is performed, and the width of the etched groove is 6 μm, and the depth is 3 μm. Finally, the glue is removed, the etching mask is removed, and a light sheet is cleaned. The process conditions are: ICP coil power 850W, source power 100W, reaction gas _SF6 and _O2 are 48sccm and 12sccm respectively.

Step g1, etching to form a source region, as shown in g in FIG. 2;

First magnetron sputtering a layer The Ti film is used as an ICP etching mask, and then photolithography is applied, and ICP etching is performed to form a contact hole in the source region. Finally, the glue is removed, the etching mask is removed, and a light sheet is cleaned. The process conditions are: ICP coil power 850W, source power 100W, reaction gas _SF6 and _O2 are 48sccm and 12sccm respectively.

Step h1, oxidation to form trench gates, as shown in h in FIG. 2 ;

The _SiO2 gate was prepared at 1150°C by dry oxygen process with a thickness of 100nm, and then annealed at 1050°C under _N2 atmosphere to reduce the roughness of the _SiO2 film surface.

Step i1, deposit polysilicon, as shown in i in Figure 2;

Low-pressure hot-wall chemical vapor deposition is used to grow polySi to fill the trenches, the deposition temperature is 600-650°C, the deposition pressure is 60-80Pa, the reaction gases are silane and phosphine, the carrier gas is helium, and then Glue photolithography, etch the polySi layer to form a polysilicon gate, and finally remove the glue and clean.

Step j1, opening a contact hole, as shown in j in Figure 2;

Deposit a layer of field oxygen or Si ₃ N ₄ on the surface of the device, then apply glue for photolithography, etch the passivation layer to open electrode contact holes, and finally remove the glue and clean.

Step k1, preparing electrodes, as shown in k in Figure 2;

E-beam evaporation of Ti/Ni/Au to make the front grid and source electrode, then glue photolithography, metal corrosion to form the front grid, source electrode contact pattern, glue removal, and cleaning.

Evaporate Ti/Ni/Au on the back side to make the back drain electrode, then make the front gate and source electrode, and finally anneal in an Ar atmosphere for 3min at a temperature of 1050°C.

Embodiment two:

Step a2, epitaxially growing an N-type drift region;

RCA standard cleaning is performed on the N-type silicon carbide substrate first, and then an N-drift layer with a thickness of 25 μm and a nitrogen ion doping concentration of 5×10 ¹⁵ cm ^-3 is epitaxially grown on the entire substrate. The process conditions are: The temperature is 1600°C, the pressure is 100mbar, the reaction gas is silane and propane, the carrier gas is pure hydrogen, and the dopant source is liquid nitrogen.

Step b2, ion implantation to form an N+ well;

In step b21, a layer of SiO ₂ with a thickness of 0.2 μm is deposited on the entire silicon carbide surface by low-pressure chemical vapor deposition, and then Al with a thickness of 1 μm is deposited as a barrier layer for nitrogen ion implantation. Form the N+ well implantation region, the width of the N+ well implantation region is 4 μm;

In step b22, perform nitrogen ion implantation three times at an ambient temperature of 500°C. The implantation energies are 520keV, 300keV, and 150keV respectively, and the corresponding doses are 9.8×10 ¹¹ cm ^-2 , 7×10 ¹¹ cm ^-2 , 4.9×10 ¹¹ cm ^-2 , the injection depth is 0.5μm;

In step b23, standard RCA is used to clean the surface of the silicon carbide, and protect it with a C film after drying. Then ion-activated annealing was performed at 1750° C. in an argon atmosphere for 15 minutes.

Step c2 is the same as step c1 of Embodiment 1;

Step d2, epitaxially growing a P- epitaxial layer;

A P-epitaxial layer with a thickness of 3 μm and an aluminum ion doping concentration of 1×10 ¹⁸ cm ^-3 is grown on the N-type drift region and the heavily doped drift region mesa. The epitaxial growth process conditions are: the temperature is 1600 °C, the pressure is 100mbar, the reaction gas is silane and propane, the carrier gas is pure hydrogen, and the dopant source is trimethylaluminum.

Step e2 is the same as step e1 in Embodiment 1.

Step f2 is the same as step f1 in Embodiment 1.

Step g2 is the same as step g1 in Embodiment 1.

Step h2 is the same as step h1 in Embodiment 1.

Step i2 is the same as step i1 in Embodiment 1.

Step j2 is the same as step j1 in Embodiment 1.

Step k2 is the same as step k1 in Embodiment 1.

Embodiment three:

Step a3, epitaxially growing an N-type drift region;

RCA standard cleaning is performed on the N-type silicon carbide substrate first, and then an N-drift layer with a thickness of 20 μm and a nitrogen ion doping concentration of 3×10 ¹⁵ cm ^-3 is epitaxially grown on the entire substrate. The process conditions are: The temperature is 1600°C, the pressure is 100mbar, the reaction gas is silane and propane, the carrier gas is pure hydrogen, and the dopant source is liquid nitrogen.

Step b3, ion implantation to form an N+ well;

In step b31, a layer of SiO ₂ with a thickness of 0.2 μm is deposited on the entire surface of silicon carbide by low-pressure chemical vapor deposition, and then Al with a thickness of 1 μm is deposited as a barrier layer for nitrogen ion implantation. An N+ well implantation region is formed, and the width of the N+ well implantation region is 3.5 μm.

In step b32, perform nitrogen ion implantation three times at an ambient temperature of 500°C. The implantation energies are 520keV, 300keV, and 150keV respectively, and the corresponding doses are 9.8×10 ¹¹ cm ^-2 , 7×10 ¹¹ cm ^-2 , 4.9×10 ¹¹ cm ^-2 , the injection depth is 0.5μm;

In step b33, standard RCA is used to clean the surface of the silicon carbide, and protect it with a C film after drying. Then ion-activated annealing was performed at 1750° C. in an argon atmosphere for 15 minutes.

Step c3 is the same as step c1 in Embodiment 1.

Step d3, epitaxially growing a P- epitaxial layer;

A P-epitaxial layer with a thickness of 3 μm and an aluminum ion doping concentration of 8×10 ¹⁷ cm ^-3 is grown on the N-type drift region and the heavily doped drift region mesa. The epitaxial growth process conditions are: the temperature is 1600 °C, the pressure is 100mbar, the reaction gas is silane and propane, the carrier gas is pure hydrogen, and the dopant source is trimethylaluminum.

Step e3 is the same as step e1 in Embodiment 1.

Step f3 is the same as step f1 in Embodiment 1.

Step g3 is the same as step g1 in Embodiment 1.

Step h3 is the same as step h1 in Embodiment 1.

Step i3 is the same as step i1 in Embodiment 1.

Step j3 is the same as step j1 in Embodiment 1.

Step k3 is the same as step k1 in Embodiment 1.

The above descriptions are only preferred embodiments of the present invention, and are only illustrative rather than restrictive to the present invention. Those skilled in the art understand that many changes, modifications, and even equivalents can be made within the spirit and scope defined by the claims of the invention, but all will fall within the protection scope of the present invention.

Claims (10)

1. ion implanting forms a UMOSFET preparation method for N-type heavy doping drift layer table top, its Being characterised by, this detailed process is:

Step a, epitaxial growth N-type drift region: be at silicon carbide N+substrate print Epitaxial growth thickness 12 μm～25 μm, Nitrogen ion doping content is 1 × 10¹⁵cm^-3～5 × 10¹⁵cm^-3N-type drift region；

Step b, ion implanting forms N+ trap: carries out ion implanting in N-type drift region, is formed heavily doped Miscellaneous N+ trap, N+ trap width is 3 μm～4 μm, and implanted dopant is Nitrogen ion, and the degree of depth is 0.5 μm, Doping content is 1 × 10¹⁷cm^-3；

Step c, N+ trap etching is for table top: N+ trap is etched into a table top, table surface height and N+ trap Deep equality, mesa width is equal with the width of trap；

Step d, epitaxial growth P-epitaxial layer: grow in N-type drift region and N+ drift layer table top Layer P-epitaxial layer, thickness is 3 μm, and Al-doping concentration is 5 × 10¹⁷cm^-3～1 × 10¹⁸cm^-3；

Step e, epitaxial growth N+ source region layer: grow one layer of N+ source region layer, thickness on P-epitaxial layer Being 0.5 μm, doping content is 5 × 10¹⁸cm^-3；

Step f, etches grooving: use ICP etching to be formed directly over N-type heavy doping drift layer table top Groove, width is 6 μm, and the degree of depth is 3 μm, and two base angles of such groove are wrapped up by P-epitaxial layer；

Step g, etching forms source region: use ICP etching to form source contact；

Step h, oxidation forms groove grid: by thermal oxidation technology preparation vessel gate medium SiO₂, thickness is 100nm；

Step i, depositing polysilicon: the groove gate medium SiO in groove grid₂Upper deposit polySi layer；

Step j, opening contact hole: prepare passivation layer, open electrode contact hole；

Step k, prepares electrode: evaporated metal, prepares electrode.

Ion implanting the most according to claim 1 forms N-type heavy doping drift layer table top UMOSFET preparation method, it is characterised in that in above-mentioned steps a, first serves as a contrast the carborundum of N-type Egative film carries out RCA standard cleaning, is then 12 μm～25 μ at whole substrate slice Epitaxial growth thickness M, Nitrogen ion doping content is 1 × 10¹⁵cm^-3～5 × 10¹⁵cm^-3N-drift layer, its process conditions are: Temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas uses silane and propane, and carrier gas is adopted With pure hydrogen, doped source uses liquid nitrogen.

Ion implanting the most according to claim 1 and 2 forms N-type heavy doping drift layer table top UMOSFET preparation method, it is characterised in that the detailed process of above-mentioned steps b is:

Step b01, uses low pressure chemical vapor deposition mode to deposit thick layer at whole silicon carbide Degree is the SiO of 0.2 μm₂, then the Al that deposition thickness is 1 μm is as the barrier layer of N~+ implantation, Forming N+ trap injection region by photoetching and etching, N+ trap injection region width is 3-4 μm；

Step b02, carries out three N~+ implantation, successively Implantation Energies under the environment temperature of 500 DEG C Being respectively 520keV, 300keV, 150keV, corresponding dosage is 9.8 × 10¹¹cm^-2、7×10¹¹cm^-2、 4.9×10¹¹cm^-2, injecting the degree of depth is 0.5 μm；

Step b03, silicon carbide is carried out by standard RCA of employing, does the protection of C film after drying, Then carrying out ion-activated annealing in 1750 DEG C of argon atmospheres, the time is 15min.

Ion implanting the most according to claim 3 forms N-type heavy doping drift layer table top UMOSFET preparation method, it is characterised in that in above-mentioned steps c, N+ trap width is 3 μm～4 μm, Implanted dopant is Nitrogen ion, and the degree of depth is 0.5 μm, and doping content is 1 × 10¹⁷cm^-3, its process conditions For: implantation temperature 500 DEG C, ion-activated annealing temperature 1750 DEG C, annealing time 10min.

Ion implanting the most according to claim 3 forms N-type heavy doping drift layer table top UMOSFET preparation method, it is characterised in that in above-mentioned steps d, drifts about in N-type drift region and N+ Growing one layer of P-epitaxial layer on layer table top, thickness is 3 μm, and Al-doping concentration is 5 × 10¹⁷cm^-3～1 ×10¹⁸cm^-3；N+ trap etching is table top, and the height of table top is equal to N+ trap width, and its process conditions are: ICP coil power 850W, source power 100W, reacting gas SF₆And O₂Be respectively 48sccm and 12sccm。

Ion implanting the most according to claim 3 forms N-type heavy doping drift layer table top UMOSFET preparation method, it is characterised in that in above-mentioned steps e, grows one on P-epitaxial layer Layer thickness is 0.5 μm, and Nitrogen ion doping content is 5 × 10¹⁸cm^-3N-type silicon carbide epitaxial layers, make For N+ source region layer, its process conditions are: temperature is 1600 DEG C, and pressure is 100mbar, reacting gas Using silane and propane, carrier gas uses pure hydrogen, and doped source uses liquid nitrogen.

Ion implanting the most according to claim 6 forms N-type heavy doping drift layer table top UMOSFET preparation method, it is characterised in that in above-mentioned steps f, first magnetron sputtering one layer Ti film as ICP etch mask, then gluing photoetching, carry out ICP etching, etch the width of groove Degree is 6 μm, and the degree of depth is 3 μm, finally removes photoresist, goes etch mask, cleans into mating plate；Process conditions For: ICP coil power 850W, source power 100W, reacting gas SF₆And O₂It is respectively 48sccm And 12sccm.

Ion implanting the most according to claim 6 forms N-type heavy doping drift layer table top UMOSFET preparation method, it is characterised in that in above-mentioned steps g, first magnetron sputtering one layer Ti film as ICP etch mask, then gluing photoetching, carry out ICP etching, form source contact Hole, finally removes photoresist, and goes etch mask, cleans into mating plate；Process conditions are: ICP coil power 850W, Source power 100W, reacting gas SF₆And O₂It is respectively 48sccm and 12sccm.

Ion implanting the most according to claim 8 forms N-type heavy doping drift layer table top UMOSFET preparation method, it is characterised in that in above-mentioned steps h, uses dry oxygen technique 1150 SiO is prepared at DEG C₂Grid, thickness is 100nm, then at 1050 DEG C, N₂Anneal under atmosphere, fall Low SiO₂The roughness of film surface.

Ion implanting the most according to claim 8 forms N-type heavy doping drift layer table top UMOSFET preparation method, it is characterised in that in above-mentioned steps i, uses low pressure hot wall chemical vapour Phase sedimentation growth ploySi fills up groove, and deposition temperature is 600～650 DEG C, and deposit pressure is 60～80Pa, reacting gas is silane and hydrogen phosphide, and carrier gas is helium, then gluing photoetching, carves Erosion ploySi layer, forms polysilicon gate, finally removes photoresist, and cleans.