CN108321213A - The preparation method and its structure of SiC power diode devices - Google Patents

Abstract

The invention relates to a method for preparing a SiC power diode device and its structure. The preparation method comprises: growing a SiC epitaxial layer on a SiC substrate layer, forming a P ⁺ region in the SiC epitaxial layer, and forming the P ⁺ region A TiC alloy layer is grown on the surface of the SiC epitaxial layer to form a Schottky contact, a first copper graphene layer is grown on the TiC alloy layer to form the anode electrode of the device, and a device cathode electrode is formed on the back side of the SiC substrate layer, so as to The preparation of the SiC power diode device is completed. The invention utilizes the contact between the TiC material and SiC to adjust the height of the potential barrier, thereby reducing the height of the Schottky barrier, reducing the turn-on voltage of the SiC power diode device, reducing the leakage current and energy consumption, and increasing the reaction rate. effect on the voltage.

Description

Fabrication method and structure of SiC power diode device

technical field

The invention relates to the technical field of microelectronics, in particular to a preparation method and structure of a SiC power diode device.

Background technique

The third-generation semiconductor material SiC (silicon carbide) has the characteristics of wide band gap, high critical breakdown electric field, high thermal conductivity, high carrier saturation drift velocity, etc. Many countries have invested a lot of money to conduct extensive research on SiC, and have made breakthroughs in SiC crystal growth technology, key device technology, optoelectronic device development, and SiC integrated circuit manufacturing. Improvements in the performance of electronic systems and weaponry, as well as electronic equipment resistant to harsh environments provide new devices.

A Schottky barrier diode is a majority carrier device that utilizes the contact barrier between a metal and a semiconductor. Compared with PN diodes, Schottky diodes have a simpler structure, and the manufacturing process is simpler, so the cost is also lower. Compared with PN diodes, Schottky diode-gated resistance switching memories have certain advantages, and Xiao Teky diodes also perform well in terms of current and response time.

However, due to the wide band gap of SiC, it is difficult to obtain a low Schottky barrier height value, which leads to excessively high Schottky barrier height when SiC is in contact with metal, which affects the turn-on voltage of semiconductor power devices and causes energy consumption. is too big.

Contents of the invention

Therefore, in order to solve the technical defects and deficiencies existing in the prior art, the present invention proposes a method for preparing a SiC power diode device and its structure.

Specifically, a method for preparing a SiC power diode device proposed by an embodiment of the present invention includes:

growing a SiC epitaxial layer on the SiC substrate layer;

forming a P ⁺ region within the SiC epitaxial layer;

growing a TiC alloy layer on the surface of the SiC epitaxial layer forming the P ⁺ region to form a Schottky contact;

growing a first copper graphene layer on the TiC alloy layer to form an anode electrode of the device;

A device cathode electrode is formed on the back side of the SiC substrate layer to complete the preparation of the SiC power diode device.

In one embodiment of the present invention, before forming the P ⁺ region in the SiC epitaxial layer, it further includes:

An ion implantation blocking layer is fabricated on the upper surface of the SiC epitaxial layer.

In one embodiment of the present invention, an ion implantation barrier layer is formed on the upper surface of the SiC epitaxial layer, including:

After performing photolithography and development on the upper surface of the SiC epitaxial layer, using photoresist as a barrier layer, and etching to form an alignment mark;

Overlaying the alignment mark to form a graphic area;

Making a Ni/Au layer on the SiC epitaxial layer with the pattern area by electron beam evaporation, and peeling off the Ni/Au layer to form the ion implantation blocking layer.

In one embodiment of the present invention, forming a P ⁺ region in the SiC epitaxial layer includes:

performing Al ion implantation on the SiC epitaxial layer;

forming a carbon film protection on the upper surface of the SiC epitaxial layer;

Ion activation annealing is performed in an argon atmosphere at a temperature of 1700° C. to 1750° C., and the annealing time is 20 minutes to form the P ⁺ region.

In one embodiment of the present invention, after forming the P ⁺ region in the SiC epitaxial layer, it further includes:

Depositing a layer of _SiO2 isolation medium on the upper surface of the SiC epitaxial layer 104 by using a chemical vapor deposition process;

At a temperature of 800° C., the SiO ₂ isolation dielectric was annealed for 60 minutes in an oxygen atmosphere to form the SiO ₂ isolation dielectric layer.

In one embodiment of the present invention, growing a TiC alloy layer on the surface of the SiC epitaxial layer forming the P ⁺ region to form a Schottky contact includes:

Coating and developing the _SiO2 isolation dielectric layer, and forming a Schottky contact window by photolithography;

depositing the TiC alloy layer on the SiC epitaxial layer by using a chemical vapor deposition process;

Anneal at a temperature of 800° C. to 900° C. for 3 minutes in a nitrogen atmosphere to form a Schottky contact.

In one embodiment of the present invention, growing the first copper graphene layer on the TiC alloy layer forms the anode electrode of the device, comprising:

Sputtering a first Cu metal layer on the TiC alloy layer by using a magnetron sputtering process;

Depositing a graphene layer on the first Cu metal layer by using a chemical vapor deposition process;

Sputtering a second Cu metal layer on the graphene layer by using a magnetron sputtering process;

The device was annealed at a temperature of 500° C. for 30 minutes to prepare the first copper graphene layer to form an anode electrode of the device.

In one embodiment of the present invention, before the cathode electrode of the device is formed on the back of the SiC substrate layer, it includes:

A first metal layer is grown on the back side of the SiC substrate layer to form an ohmic contact. In one embodiment of the present invention, after growing the first metal layer on the back side of the SiC substrate layer to form an ohmic contact, it includes:

Sputtering metal Ag on the lower surface of the first metal layer by using a magnetron sputtering process;

Annealing in a nitrogen atmosphere prepares the second metal layer to form the cathode electrode of the device.

In one embodiment of the present invention, a structure of a SiC power diode device includes: a second metal layer, a first metal layer, a SiC substrate layer, a SiC epitaxial layer, a _SiO2 isolation dielectric layer, and a TiC alloy layer stacked in sequence . The first copper graphene layer, wherein a P+ region is provided in the SiC epitaxial layer, and the SiC power diode device is formed by the method described in any one of claims 1-9.

Embodiments of the present invention have the following advantages:

1. The present invention uses the contact between TiC material and SiC to adjust the height of the barrier, thereby reducing the height of the Schottky barrier, reducing the turn-on voltage of SiC power diode devices, reducing leakage current and energy consumption, and increasing effect of reverse voltage.

2. The present invention uses TiC material as the Schottky contact metal material to increase the SiC epitaxial growth temperature, and enables SiC power diode devices to be applied under high temperature conditions.

3. The present invention adopts the copper-graphene composite material as the anode, which improves the high temperature resistance and electrical conductivity of the SiC device, and improves the heat dissipation performance of the SiC power diode device.

4. The present invention oxidizes the surface of SiC to SiO ₂ isolation medium in O ion atmosphere before depositing SiO ₂ isolation medium, which can effectively form SiC and SiO ₂ interface, and oxidize C atoms into gas to discharge, completely solving the problem of The problem of high interface state and low carrier mobility caused by C atom complex in high temperature thick oxide layer.

5. Since the final SiO ₂ isolation medium is formed by chemical vapor deposition and annealing in the present invention, the problem of C complex formation at the interface between SiC and SiO ₂ is completely solved on the premise of ensuring the quality of the SiO ₂ dielectric layer.

Other aspects and features of the present invention will become apparent from the following detailed description with reference to the accompanying drawings. It should be understood, however, that the drawings are designed for purposes of illustration only and not as a limitation of the scope of the invention since reference should be made to the appended claims. It should also be understood that, unless otherwise indicated, the drawings are not necessarily drawn to scale and are merely intended to conceptually illustrate the structures and processes described herein.

Description of drawings

The specific implementation manners of the present invention will be described in detail below in conjunction with the accompanying drawings.

Fig. 1 is a flow chart of a method for preparing a SiC power diode device provided by an embodiment of the present invention;

2a to 2i are schematic diagrams of a fabrication process flow of a SiC power diode device provided by an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a SiC power diode device provided by an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of another SiC power diode device provided by an embodiment of the present invention.

Detailed ways

In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

Embodiment one

Please refer to FIG. 1 , which is a flowchart of a method for fabricating a SiC power diode device provided by an embodiment of the present invention. This preparation method comprises the steps:

Step a, growing a SiC epitaxial layer on the SiC substrate layer;

Step b, forming a P ⁺ region in the SiC epitaxial layer;

Step c, growing a TiC alloy layer on the surface of the SiC epitaxial layer forming the P ⁺ region to form a Schottky contact;

Step d, growing a first copper graphene layer 109 on the TiC alloy layer to form an anode electrode of the device;

Step e, forming a cathode electrode of the device on the back of the SiC substrate layer, so as to complete the preparation of the SiC power diode device.

Wherein, before step b also includes:

Step b1, forming an ion implantation barrier layer on the upper surface of the SiC epitaxial layer.

Wherein, step b1 includes:

Step b11, after performing photolithography and development on the upper surface of the SiC epitaxial layer, using photoresist as a barrier layer, and etching to form an alignment mark;

Step b12, overlaying the alignment mark to form a graphic area;

Step b13, forming a Ni/Au layer on the SiC epitaxial layer with the pattern area by electron beam evaporation, and peeling off the Ni/Au layer to form the ion implantation blocking layer.

Wherein, step b includes:

Step b2, performing Al ion implantation on the SiC epitaxial layer;

Step b3, forming a carbon film protection on the upper surface of the SiC epitaxial layer;

Step b4, performing ion activation annealing in an argon atmosphere at a temperature of 1700° C. to 1750° C. for 20 minutes to form a P ⁺ region.

Wherein, after step b also includes:

Step b5, using a chemical vapor deposition process to deposit a layer of _SiO2 isolation medium on the upper surface of the SiC epitaxial layer;

Step b6, annealing the SiO ₂ isolation dielectric in an oxygen atmosphere at a temperature of 800° C. for 60 minutes to form a SiO ₂ isolation dielectric layer.

Wherein, step c includes:

Step c1, coating and developing the _SiO2 isolation dielectric layer, and forming a Schottky contact window by photolithography;

Step c2, using a chemical vapor deposition process to deposit a TiC alloy layer on the Schottky contact window on the SiC epitaxial layer;

Step c3, annealing for 3 minutes in a nitrogen atmosphere at a temperature of 800° C. to 900° C. to form a Schottky contact.

Wherein, step d includes:

Step d1, using a magnetron sputtering process to sputter a first Cu metal layer on the TiC alloy layer;

Step d2, using a chemical vapor deposition process to deposit a graphene layer on the first Cu metal layer;

Step d3, using a magnetron sputtering process to sputter a second Cu metal layer on the graphene layer;

Step d4, annealing the device at a temperature of 500° C. for 30 minutes to prepare the first copper graphene layer to form an anode electrode of the device.

Wherein, before step e also includes:

Step e1, growing a first metal layer on the back side of the SiC substrate layer to form an ohmic contact. Wherein, step e includes:

Step e2, using a magnetron sputtering process to sputter metal Ag on the lower surface of the first metal layer;

Step e3, annealing in a nitrogen atmosphere to prepare the second metal layer to form the cathode electrode of the device.

Preferably, the first copper graphene layer is a copper graphene composite material.

Preferably, the structure of the SiC power diode device includes: the second metal layer, the first metal layer, the SiC substrate layer, the SiC epitaxial layer, the _SiO2 isolation dielectric layer, the TiC alloy layer, the first copper graphene layer stacked in sequence, Wherein, a P+ region is arranged in the SiC epitaxial layer.

The beneficial effects of this embodiment are specifically:

1. In this embodiment, a layer of TiC alloy material is formed on the surface of the SiC epitaxial layer to form a Schottky contact, and the Schottky barrier height is reduced through the Schottky contact between the SiC epitaxial layer and the TiC alloy layer, which can Reduce the turn-on voltage of SiC power diode devices, thereby achieving the effects of reducing leakage current and energy consumption, and increasing reverse voltage.

2. In this embodiment, TiC alloy material is used as the Schottky contact metal material, which can not only increase the temperature of SiC epitaxial growth, but also enable SiC power diode devices to be applied under high temperature conditions.

3. In this embodiment, the copper-graphene composite material is used as the anode, which improves the high temperature resistance and electrical conductivity of the SiC power diode device, and improves the heat dissipation performance of the SiC power diode device.

Embodiment two

Please refer to FIG. 2a to FIG. 2h , which are schematic diagrams of a manufacturing process flow of a SiC power diode device provided by an embodiment of the present invention. On the basis of the above embodiments, this embodiment will introduce the process flow of the present invention in more detail. The preparation method includes:

S1. Substrate selection

The N ⁺ -type SiC substrate layer 103 with a doping concentration of 5×10 ¹⁸ cm ⁻³ is selected as the initial material.

S11 , cleaning the N ⁺ -type SiC substrate layer 103 by RCA (wet chemical cleaning method) cleaning standard, so as to remove organic and inorganic chemical pollutants on the surface of the sample.

S2. Epitaxial growth of SiC epitaxial layer 104 on SiC substrate layer 103

S21. As shown in FIG. 2a, using a chemical vapor deposition process, epitaxially grow an N ^- type SiC epitaxial layer 104 with a thickness of 8 μm and a nitrogen ion doping concentration of 1×10 ¹⁵ cm ⁻³ above the SiC substrate layer 103. The process The conditions are: the epitaxial growth temperature is 1570°C, the pressure is 100mbar, the reaction gas is silane and propane, the carrier gas is pure hydrogen, and the impurity source is liquid nitrogen.

S3. Growing an ion implantation barrier layer 105 on the SiC epitaxial layer 104

S31. After RCA standard cleaning is performed on the SiC epitaxial layer 104, after coating photolithography and development, use photoresist as a barrier layer, and use RE etching for 5 minutes to form an alignment mark, and the depth of the alignment mark is 0.4 μm;

S32. Overlay the formed alignment mark to form a graphic area;

S33, as shown in Figure 2b, by electron beam evaporation on the upper surface of the SiC epitaxial layer 104 with a pattern area Ni/Au layer, where the thickness of Ni is The thickness of Au is Then soak in acetone for ultrasonic treatment to peel off the metal to form the ion implantation blocking layer 105 .

S4, forming a P ⁺ region 106 in the SiC epitaxial layer 104

S41. As shown in FIG. 2c, five times of Al ion implantation is performed on the SiC epitaxial layer 104 at an ambient temperature of 450° C., the implantation depth is 0.4 μm, and the implantation energies are 30 keV, 120 keV, 300 keV, 420 keV and 550 keV respectively, and the implantation energies are At 30keV, the implant dose is 2.8×10 ¹² cm ^-2 ; when the implant energy is 120keV, the implant dose is 6.5×10 ¹² cm ^-2 ; when the implant energy is 300keV, the implant dose is 1.05×10 ¹³ cm ^-2 ; When the implantation energy is 420keV, the implantation dose is 1.3×10 ¹³ cm ^-2 ; when the implantation energy is 550keV, the implantation dose is 1.45×10 ¹³ cm ^-2 , forming P ⁺ regions 106 arranged at intervals;

S42. Clean the surface of the SiC epitaxial layer 104 using the RCA cleaning standard, and dry it at 1000° C. for 20 minutes. After drying, apply glue on the surface of the SiC epitaxial layer 104 three times, and heat at 400° C. for 90 minutes to carbonize the photoresist. After conversion into an amorphous C film to form a carbon film protection;

S43 , performing ion activation annealing in an argon atmosphere at 1700° C.˜1750° C. for 20 minutes to form a P ⁺ region 106 .

S5, growing a SiO ₂ isolation dielectric layer 107 on the SiC epitaxial layer 104

S51. Put the device as a whole into a chemical vapor deposition furnace and heat it to 300°C, and then pass in oxygen for 60 seconds. Under an O ion atmosphere, oxidize the surface of the SiC epitaxial layer 104 into a 1-2nm SiO ₂ isolation medium, then pass in silane, and deposit 100nm SiO ₂ isolation dielectric.

S52 , as shown in FIG. 2 d , anneal the SiC sample at 800° C. for 60 minutes in an oxygen atmosphere to form a SiO ₂ isolation dielectric layer 107 .

S6, growing a TiC alloy layer 108 on the Schottky contact window on the SiC epitaxial layer 104

S61, coating and developing the _SiO2 isolation dielectric layer 107, and then performing photolithography to form a Schottky contact window;

S62. As shown in FIG. 2e, a TiC alloy layer 108 is deposited on the Schottky contact window by a chemical vapor deposition process;

S63 , annealing for 3 minutes in a nitrogen atmosphere at a temperature of 850±50° C. to form a Schottky contact between the SiC epitaxial layer 104 and the TiC alloy layer 108 .

S7, growing the first copper graphene layer 109 on the SiO ₂ isolation dielectric layer 107 and the TiC alloy layer 108

S71. As shown in FIG. 2f, use magnetron sputtering process to sputter copper-graphene composite material on _SiO2 isolation dielectric layer 107 and TiC alloy layer 108 to form a first copper-graphene layer 109, wherein the first copper-graphene layer The vinyl layer 109 has a thickness of 1 μm, and is an anode.

S8, growing a first metal layer (ie Ni metal layer 102) on the lower surface of the SiC substrate layer 103

S81, using a magnetron sputtering process to sputter the Ni metal layer 102 on the lower surface of the SiC substrate layer 103;

S82, as shown in FIG. 2g, annealing in a nitrogen atmosphere to form an ohmic contact between the SiC substrate layer 103 and the Ni metal layer 102, and the Ni metal layer 102 is a cathode.

S9, growing a second metal layer (i.e. Ag metal layer 101) on the lower surface of the Ni metal layer 102

S91, as shown in FIG. 2h, sputter metal Ag on the lower surface of the Ni metal layer 102 by using a magnetron sputtering process;

S92 , annealing in a nitrogen atmosphere at a temperature of 900° C. to form an Ag metal layer 101 , and the Ag metal layer 101 is a cathode.

The beneficial effect of this embodiment:

1. In this embodiment, before depositing the _SiO2 isolation medium, the SiC surface is oxidized into a _SiO2 isolation medium in an O ion atmosphere, which can effectively form the interface between SiC and _SiO2 , and oxidize the C atoms into gas to be discharged, completely Solve the problem of high interface state and low carrier mobility caused by C atom complex in high temperature and thick oxide layer.

2. In this embodiment, since the final SiO ₂ isolation medium is formed by chemical vapor deposition and annealing, the problem of C complex formation at the interface between SiC and SiO ₂ can be completely solved on the premise of ensuring the quality of the SiO ₂ dielectric layer.

Embodiment three

Please refer to Fig. 2a-Fig. 2h again. On the basis of the above embodiments, this embodiment will introduce another process flow of the present invention in more detail. The preparation method includes:

S1. Substrate selection

The N ⁺ -type SiC substrate layer 103 with a doping concentration of 5×10 ¹⁸ cm ⁻³ is selected as the initial material.

S11 , cleaning the N ⁺ -type SiC substrate layer 103 by RCA (wet chemical cleaning method) cleaning standard, so as to remove organic and inorganic chemical pollutants on the surface of the sample.

S2. Epitaxial growth of SiC epitaxial layer 104 on SiC substrate layer 103

S21. As shown in FIG. 2a, using a chemical vapor deposition process, epitaxially grow an N ^- type SiC epitaxial layer 104 with a thickness of 8 μm and a nitrogen ion doping concentration of 1×10 ¹⁵ cm ⁻³ above the SiC substrate layer 103. The process The conditions are: the epitaxial growth temperature is 1570°C, the pressure is 100mbar, the reaction gas is silane and propane, the carrier gas is pure hydrogen, and the impurity source is liquid nitrogen.

S3. Growing an ion implantation barrier layer 105 on the SiC epitaxial layer 104

S31. After RCA standard cleaning is performed on the SiC epitaxial layer 104, after coating photolithography and development, use photoresist as a barrier layer, and use RE etching for 5 minutes to form an alignment mark, and the depth of the alignment mark is 0.4 μm;

S32. Overlay the formed alignment mark to form a graphic area;

S33, as shown in Figure 2b, by electron beam evaporation on the upper surface of the SiC epitaxial layer 104 with a pattern area Ni/Au layer, where the thickness of Ni is The thickness of Au is Then soak in acetone for ultrasonic treatment to peel off the metal to form the ion implantation blocking layer 105 .

S4, forming a P ⁺ region 106 in the SiC epitaxial layer 104

S41. As shown in FIG. 2c, five times of Al ion implantation is performed on the SiC epitaxial layer 104 at an ambient temperature of 450° C., the implantation depth is 0.4 μm, and the implantation energies are 30 keV, 120 keV, 300 keV, 420 keV and 550 keV respectively, and the implantation energies are At 30keV, the implant dose is 2.8×10 ¹² cm ^-2 ; when the implant energy is 120keV, the implant dose is 6.5×10 ¹² cm ^-2 ; when the implant energy is 300keV, the implant dose is 1.05×10 ¹³ cm ^-2 ; When the implantation energy is 420keV, the implantation dose is 1.3×10 ¹³ cm ^-2 ; when the implantation energy is 550keV, the implantation dose is 1.45×10 ¹³ cm ^-2 , forming P ⁺ regions 106 arranged at intervals;

S42. Clean the surface of the SiC epitaxial layer 104 using the RCA cleaning standard, and dry it at 1000° C. for 20 minutes. After drying, apply glue on the surface of the SiC epitaxial layer 104 three times, and heat at 400° C. for 90 minutes to carbonize the photoresist. After that, it is converted into an amorphous C film to form a carbon film protection, and the thickness of the C film is 0.4 μm;

S43 , performing ion activation annealing in an argon atmosphere at 1700° C.˜1750° C. for 20 minutes to form a P ⁺ region 106 .

S5, growing a SiO ₂ isolation dielectric layer 107 on the SiC epitaxial layer 104

S51. Put the device as a whole into a chemical vapor deposition furnace and heat it to 300°C, and then pass in oxygen for 60 seconds. Under an O ion atmosphere, oxidize the surface of the SiC epitaxial layer 104 into a 1-2nm SiO ₂ isolation medium, then pass in silane, and deposit 100nm _SiO2 isolation dielectric;

S52 , as shown in FIG. 2 d , anneal the SiC sample at 800° C. for 60 minutes in an oxygen atmosphere to form a SiO ₂ isolation dielectric layer 107 .

S6, growing a TiC alloy layer 108 on the Schottky contact window on the SiC epitaxial layer 104

S61, coating and developing the _SiO2 isolation dielectric layer 107, and then performing photolithography to form a Schottky contact window;

S62. As shown in FIG. 2e, a TiC alloy layer 108 is deposited on the Schottky contact window by a chemical vapor deposition process;

S63 , annealing for 3 minutes in a nitrogen atmosphere at a temperature of 850±50° C. to form a Schottky contact between the SiC epitaxial layer 104 and the TiC alloy layer 108 .

S7, growing the first copper graphene layer 109 on the SiO ₂ isolation dielectric layer 107 and the TiC alloy layer 108

S71, utilizing the magnetron sputtering process to sputter the first Cu metal layer on the _SiO2 isolation dielectric layer 107 and the TiC alloy layer 108;

S72, using a chemical vapor deposition process to grow a graphene layer on the first Cu metal layer;

S73, using a magnetron sputtering process to sputter a second Cu metal layer on the graphene layer;

S74 , as shown in FIG. 2f , annealing the first Cu metal layer, the graphene layer and the second Cu metal layer at a temperature of 500° C. for 30 minutes to form the first copper graphene layer 109 .

S8, growing a first metal layer (ie Ni metal layer 102) on the lower surface of the SiC substrate layer 103

S81, using a magnetron sputtering process to sputter the Ni metal layer 102 on the lower surface of the SiC substrate layer 103;

S82 , as shown in FIG. 2 g , annealing in a nitrogen atmosphere at a temperature of 900° C. to form an ohmic contact between the SiC substrate layer 103 and the Ni metal layer 102 , and the Ni metal layer 102 is a cathode.

S9, growing a second metal layer (i.e. Ag metal layer 101) on the lower surface of the Ni metal layer 102

S91, as shown in FIG. 2h, sputter metal Ag on the lower surface of the Ni metal layer 102 by using a magnetron sputtering process;

S92 , annealing in a nitrogen atmosphere at a temperature of 900° C. to form an Ag metal layer 101 , and the Ag metal layer 101 is a cathode.

Embodiment four

Please refer to FIGS. 2a-2g and 2i again. On the basis of the above embodiments, this embodiment will introduce another technical process of the present invention in more detail. The preparation method includes:

S1. Substrate selection

The N ⁺ -type SiC substrate layer 103 with a doping concentration of 5×10 ¹⁸ cm ⁻³ is selected as the initial material.

S11 , cleaning the N ⁺ -type SiC substrate layer 103 by RCA (wet chemical cleaning method) cleaning standard, so as to remove organic and inorganic chemical pollutants on the surface of the sample.

S2. Epitaxial growth of SiC epitaxial layer 104 on SiC substrate layer 103

S21. As shown in FIG. 2a, using a chemical vapor deposition process, epitaxially grow an N ^- type SiC epitaxial layer 104 on the surface of the SiC substrate layer 103 with a thickness of 8 μm and a nitrogen ion doping concentration of 1×10 ¹⁵ cm ⁻³ , which The process conditions are as follows: epitaxial growth temperature is 1570°C, pressure is 100mbar, silane and propane are used as reaction gas, pure hydrogen is used as carrier gas, and liquid nitrogen is used as impurity source. S3. Growing an ion implantation barrier layer 105 on the SiC epitaxial layer 104

S31. After RCA standard cleaning is performed on the SiC epitaxial layer 104, after coating photolithography and development, use photoresist as a barrier layer, and use RE etching for 5 minutes to form an alignment mark, and the depth of the alignment mark is 0.4 μm;

S32. Overlay the formed alignment mark to form a graphic area;

S33, as shown in Figure 2b, by electron beam evaporation on the upper surface of the SiC epitaxial layer 104 with a pattern area Ni/Au layer, where the thickness of Ni is The thickness of Au is Then soak in acetone for ultrasonic treatment to peel off the metal to form the ion implantation blocking layer 105 .

S4, forming a P ⁺ region 106 in the SiC epitaxial layer 104

S41. As shown in FIG. 2c, five times of Al ion implantation is performed on the SiC epitaxial layer 104 at an ambient temperature of 450° C., the implantation depth is 0.4 μm, and the implantation energies are 30 keV, 120 keV, 300 keV, 420 keV and 550 keV respectively, and the implantation energies are At 30keV, the implant dose is 2.8×10 ¹² cm ^-2 ; when the implant energy is 120keV, the implant dose is 6.5×10 ¹² cm ^-2 ; when the implant energy is 300keV, the implant dose is 1.05×10 ¹³ cm ^-2 ; When the implantation energy is 420keV, the implantation dose is 1.3×10 ¹³ cm ^-2 ; when the implantation energy is 550keV, the implantation dose is 1.45×10 ¹³ cm ^-2 , forming P ⁺ regions 106 arranged at intervals;

S42. Clean the surface of the SiC epitaxial layer 104 using the RCA cleaning standard, and dry it at 1000° C. for 20 minutes. After drying, apply glue on the surface of the SiC epitaxial layer 104 three times, and heat at 400° C. for 90 minutes to carbonize the photoresist. After that, it is converted into an amorphous C film to form a carbon film protection, and the thickness of the C film is 0.4 μm;

S43 , performing ion activation annealing in an argon atmosphere at 1700° C.˜1750° C. for 20 minutes to form a P ⁺ region 106 .

S5, growing a SiO ₂ isolation dielectric layer 107 on the SiC epitaxial layer 104

S51. Put the device as a whole into a chemical vapor deposition furnace and heat it to 300°C, and then pass in oxygen for 60 seconds. Under an O ion atmosphere, oxidize the surface of the SiC epitaxial layer 104 into a 1-2nm SiO ₂ isolation medium, then pass in silane, and deposit 100nm SiO ₂ isolation dielectric.

S52 , as shown in FIG. 2 d , anneal the SiC sample at 800° C. for 60 minutes in an oxygen atmosphere to form a SiO ₂ isolation dielectric layer 107 .

S6, growing a TiC alloy layer 108 on the Schottky contact window on the SiC epitaxial layer 104

S61, coating and developing the _SiO2 isolation dielectric layer 107, and then performing photolithography to form a Schottky contact window;

S62. As shown in FIG. 2e, a TiC alloy layer 108 is deposited on the Schottky contact window by a chemical vapor deposition process;

S63 , annealing for 3 minutes in a nitrogen atmosphere at a temperature of 850±50° C. to form a Schottky contact between the SiC epitaxial layer 104 and the TiC alloy layer 108 .

S7, growing the first copper graphene layer 109 on the SiO ₂ isolation dielectric layer 107 and the TiC alloy layer 108

S71. As shown in FIG. 2f, use magnetron sputtering process to sputter copper-graphene composite material on _SiO2 isolation dielectric layer 107 and TiC alloy layer 108 to form a first copper-graphene layer 109, wherein the first copper-graphene layer The vinyl layer 109 has a thickness of 1 μm, and is an anode.

Optionally, metal Al is sputtered on the SiO ₂ isolation dielectric layer 107 and the NiCr alloy layer 108 by a magnetron sputtering process to form an Al metal layer as an anode.

S8, growing a first metal layer (ie Ni metal layer 102) on the lower surface of the SiC substrate layer 103

S81, using a magnetron sputtering process to sputter the Ni metal layer 102 on the lower surface of the SiC substrate layer 103;

S82 , as shown in FIG. 2 g , annealing in a nitrogen atmosphere at a temperature of 900° C. to form an ohmic contact between the SiC substrate layer 103 and the Ni metal layer 102 , and the Ni metal layer 102 is a cathode.

S9, growing a second copper graphene layer on the lower surface of the Ni metal layer 102

S91. As shown in FIG. 2i, sputter a copper-graphene composite material on the lower surface of the Ni metal layer 102 by magnetron sputtering to form a second copper-graphene layer, and the second copper-graphene layer is a cathode.

Embodiment five

Please refer to FIG. 3 again. FIG. 3 is a schematic structural diagram of a SiC power diode device provided by an embodiment of the present invention. This embodiment provides a structure of a SiC power diode device, which includes:

The second metal layer (i.e. the Ag metal layer 101);

Wherein, the Ag metal layer 101 is a cathode with a thickness of 1 μm.

The first metal layer (i.e. the Ni metal layer 102) is located on the upper surface of the Ag metal layer 101;

Wherein, the Ni metal layer 102 is a cathode with a thickness of 1 μm.

SiC substrate layer 103, located on the upper surface of Ni metal layer 102;

Wherein, the SiC substrate layer 103 is made of N ⁺ -type SiC material with a doping concentration of 5×10 ¹⁸ cm ⁻³ and has a thickness of 360 μm. The SiC substrate layer 103 and the Ni metal layer 102 form an ohmic contact.

SiC epitaxial layer 104, located on the upper surface of SiC substrate layer 103;

Wherein, the SiC epitaxial layer 104 is made of N ^- type SiC material with a doping concentration of 1×10 ¹⁵ cm ⁻³ , and has a thickness of 8 μm.

a P ⁺ region 106 within the SiC epitaxial layer 104;

Wherein, the doping concentration of the P ⁺ region 106 is 3×10 ¹⁸ cm ⁻³ , the depth is 0.4 μm, and the P ⁺ region 106 is located inside the SiC epitaxial layer 104 and arranged at intervals.

The SiO ₂ isolation dielectric layer 107 is located on the upper surface of the SiC epitaxial layer 104;

Wherein, the thickness of the SiO ₂ isolation dielectric layer 107 is 100 nm.

TiC alloy layer 108, located on the upper surface of SiC epitaxial layer 104;

Wherein, the SiC epitaxial layer 104 and the TiC alloy layer 108 form a Schottky contact.

The first copper graphene layer 109 is positioned at the _SiO2 isolation dielectric layer 107 and the TiC alloy layer 108 upper surface;

Wherein, the first copper graphene layer 109 is a composite material, the thickness of the first copper graphene layer 109 is 1 μm, and it is an anode.

The beneficial effect of this embodiment:

1. In this embodiment, a layer of TiC alloy material is formed on the surface of the SiC epitaxial layer to form a Schottky contact, and the Schottky barrier height is reduced through the Schottky contact between the SiC epitaxial layer and the TiC alloy layer, which can Reduce the turn-on voltage of SiC power diode devices, thereby achieving the effects of reducing leakage current and energy consumption, and increasing reverse voltage.

2. In this embodiment, TiC material is used as the Schottky contact metal material, which can increase the SiC epitaxial growth temperature and enable SiC power diode devices to be applied under high temperature conditions.

3. In this embodiment, the copper-graphene composite material is used as the anode, which improves the high temperature resistance and electrical conductivity of the SiC power diode device, and improves the heat dissipation performance of the SiC power diode device.

Embodiment six

Please refer to FIG. 4 , which is a schematic structural diagram of another SiC power diode device provided by an embodiment of the present invention. This embodiment provides another structure of a SiC power diode device, which includes:

second copper graphene layer 110;

Wherein, the second copper graphene layer 110 is a copper graphene composite material, and the second copper graphene layer 110 is a cathode.

The first metal layer (i.e. the Ni metal layer 102) is located on the second copper graphene layer 110 upper surface;

Wherein, the Ni metal layer 102 is a cathode with a thickness of 1 μm.

SiC substrate layer 103, located on the upper surface of Ni metal layer 102;

Wherein, the SiC substrate layer 103 is made of N ⁺ -type SiC material with a doping concentration of 5×10 ¹⁸ cm ⁻³ and has a thickness of 360 μm. The SiC substrate layer 103 and the Ni metal layer 102 form an ohmic contact.

SiC epitaxial layer 104, located on the upper surface of SiC substrate layer 103;

Wherein, the SiC epitaxial layer 104 is made of N ^- type SiC material with a doping concentration of 1×10 ¹⁵ cm ⁻³ , and has a thickness of 8 μm.

a P ⁺ region 106 within the SiC epitaxial layer 104;

Wherein, the doping concentration of the P ⁺ region 106 is 3×10 ¹⁸ cm ⁻³ , the depth is 0.4 μm, and the P ⁺ region 106 is located inside the SiC epitaxial layer 104 and arranged at intervals.

The SiO ₂ isolation dielectric layer 107 is located on the upper surface of the SiC epitaxial layer 104;

Wherein, the thickness of the SiO ₂ isolation dielectric layer 107 is 100 nm.

TiC alloy layer 108, located on the upper surface of SiC epitaxial layer 104;

Wherein, the SiC epitaxial layer 104 and the TiC alloy layer 108 form a Schottky contact.

The first copper graphene layer 109 is positioned at the _SiO2 isolation dielectric layer 107 and the TiC alloy layer 108 upper surface;

Wherein, the first copper graphene layer 109 is a composite material, the thickness of the first copper graphene layer 109 is 1 μm, and it is an anode.

Optionally, the Al metal layer is located on the upper surface of the SiO ₂ isolation dielectric layer and the NiCr alloy layer, and the Al metal layer is an anode.

In this embodiment, the copper-graphene composite material is used to prepare the anode and cathode of the SiC power diode device, which can improve the high temperature resistance and electrical conductivity of the SiC device, and improve the heat dissipation performance of the SiC power diode device.

To sum up, this paper uses specific examples to illustrate a method for preparing a SiC power diode device provided by the embodiment of the present invention, its structure, principle and implementation. The description of the above embodiment is only used to help understand the present invention The method of the invention and its core idea; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation and scope of application. In summary, the content of this specification should not be understood In order to limit the present invention, the scope of protection of the present invention should be based on the appended claims.

Claims (10)

1. A method for preparing a SiC power diode device, comprising: growing a SiC epitaxial layer on the SiC substrate layer; forming a P ⁺ region within the SiC epitaxial layer; growing a TiC alloy layer on the surface of the SiC epitaxial layer forming the P ⁺ region to form a Schottky contact; growing a first copper graphene layer on the TiC alloy layer to form an anode electrode of the device; A cathode electrode of the device is formed on the back side of the SiC substrate layer to complete the preparation of the SiC power diode device. 2. The method according to claim 1, further comprising: before forming a P ⁺ region in the SiC epitaxial layer: An ion implantation blocking layer is fabricated on the upper surface of the SiC epitaxial layer. 3. The method according to claim 2, characterized in that, forming an ion implantation barrier layer on the upper surface of the SiC epitaxial layer, comprising: After performing photolithography and development on the upper surface of the SiC epitaxial layer, using photoresist as a barrier layer, and etching to form an alignment mark; Overlaying the alignment mark to form a graphic area; Making a Ni/Au layer on the SiC epitaxial layer with the pattern area by electron beam evaporation, and peeling off the Ni/Au layer to form the ion implantation blocking layer. 4. The method according to claim 1, wherein forming a P ⁺ region in the SiC epitaxial layer comprises: performing Al ion implantation on the SiC epitaxial layer; forming a carbon film protection on the upper surface of the SiC epitaxial layer; Ion activation annealing is performed in an argon atmosphere at a temperature of 1700° C. to 1750° C., and the annealing time is 20 minutes to form the P ⁺ region. 5. The method according to claim 1, further comprising: after forming a P ⁺ region in the SiC epitaxial layer: Depositing a layer of _SiO2 isolation medium on the upper surface of the SiC epitaxial layer by chemical vapor deposition process; At a temperature of 800° C., the SiO ₂ isolation dielectric was annealed for 60 minutes in an oxygen atmosphere to form a SiO ₂ isolation dielectric layer. 6. The method according to claim 1, wherein growing a TiC alloy layer on the surface of the SiC epitaxial layer forming the P ⁺ region to form a Schottky contact comprises: Coating and developing the _SiO2 isolation dielectric layer, and forming a Schottky contact window by photolithography; depositing the TiC alloy layer on the SiC epitaxial layer by using a chemical vapor deposition process; Anneal at a temperature of 800° C. to 900° C. for 3 minutes in a nitrogen atmosphere to form a Schottky contact. 7. method according to claim 1, is characterized in that, grows the anode electrode of first copper graphene layer formation device on described TiC alloy layer, comprises: Sputtering a first Cu metal layer on the TiC alloy layer by using a magnetron sputtering process; Depositing a graphene layer on the first Cu metal layer by using a chemical vapor deposition process; Sputtering a second Cu metal layer on the graphene layer by using a magnetron sputtering process; The device was annealed at a temperature of 500° C. for 30 minutes to prepare the first copper graphene layer to form an anode electrode of the device. 8. The method according to claim 1, characterized in that, before forming the cathode electrode of the device on the back side of the SiC substrate layer, comprising: A first metal layer is grown on the back side of the SiC substrate layer to form an ohmic contact. 9. The method according to claim 8, characterized in that, after growing a first metal layer on the back side of the SiC substrate layer to form an ohmic contact, comprising: sputtering metal Ag under the first metal layer by using a magnetron sputtering process; Annealing in a nitrogen atmosphere prepares the second metal layer to form the cathode electrode of the device. 10. A structure of a SiC power diode device, characterized in that it comprises: a second metal layer, a first metal layer, a SiC substrate layer, a SiC epitaxial layer, _{an SiO2} isolation dielectric layer, a TiC alloy layer, and a first layer stacked in sequence A copper graphene layer, wherein a P+ region is arranged in the SiC epitaxial layer, and the SiC power diode device is formed by the method described in any one of claims 1-9.