CN103906370B - Chip packaging structure, circuit board having embedded component and manufacturing method thereof - Google Patents
Chip packaging structure, circuit board having embedded component and manufacturing method thereof Download PDFInfo
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- CN103906370B CN103906370B CN201210577545.XA CN201210577545A CN103906370B CN 103906370 B CN103906370 B CN 103906370B CN 201210577545 A CN201210577545 A CN 201210577545A CN 103906370 B CN103906370 B CN 103906370B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title abstract description 4
- 238000000034 method Methods 0.000 claims description 39
- 238000003466 welding Methods 0.000 claims description 36
- 238000009713 electroplating Methods 0.000 claims description 8
- 238000005516 engineering process Methods 0.000 claims description 7
- 230000005611 electricity Effects 0.000 claims 5
- 229910000679 solder Inorganic materials 0.000 description 12
- 239000007800 oxidant agent Substances 0.000 description 7
- 230000001590 oxidative effect Effects 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000007747 plating Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- -1 PI) Polymers 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 229920000139 polyethylene terephthalate Polymers 0.000 description 4
- 239000005020 polyethylene terephthalate Substances 0.000 description 4
- 229920003207 poly(ethylene-2,6-naphthalate) Polymers 0.000 description 3
- 239000011112 polyethylene naphthalate Substances 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- LYCAIKOWRPUZTN-UHFFFAOYSA-N Ethylene glycol Chemical compound OCCO LYCAIKOWRPUZTN-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 239000003985 ceramic capacitor Substances 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 239000004698 Polyethylene Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- WGCNASOHLSPBMP-UHFFFAOYSA-N hydroxyacetaldehyde Natural products OCC=O WGCNASOHLSPBMP-UHFFFAOYSA-N 0.000 description 1
- 238000002386 leaching Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000005026 oriented polypropylene Substances 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention relates to a circuit board, comprising an embedment structure, first and second conducting circuit layers, a second dielectric layer and a third conducting circuit layer. The embedment structure comprises a first dielectric layer and an electronic component, wherein the first dielectric layer comprises first and second surfaces which are opposite to each other, the electronic component comprises a plurality of conductive connection terminals and a first surface embedded in the first dielectric layer, the electronic component is exposed on the surface of the first surface and is flush with the first surface, and the plurality of conductive connection terminals of the electronic component are exposed on the first surface. The first and the second conducting circuit layers are arranged on the first surface and the second surface respectively, wherein the first conducting circuit layer comprises a terminal connection circuit arranged on a surface where part of the conductive connection terminals of the electronic component is flush with the first surface. The second dielectric layer and the third conductive circuit layer are formed at one side of the first conductive circuit layer in sequence. The invention also relates to a manufacturing method of the circuit board and a chip packaging structure.
Description
Technical field
The present invention relates to circuit board making field, particularly relate to a kind of there is the circuit board of embedded element, the chip-packaging structure using this circuit board and preparation method thereof.
Background technology
Printed circuit board (PCB) is widely used because having packaging density advantages of higher.Application about circuit board refers to document Takahashi, A. Ooki, N. Nagai, A. Akahoshi, H. Mukoh, A. Wajima, M. Res. Lab,
High density multilayer printed circuit board for HITAC M-880, IEEE Trans. on Components, Packaging, and Manufacturing
Technology, 1992, 15(4): 1418-1425。
The electronic component of the printed circuit board (PCB) of prior art is arranged at the outside of circuit board mostly, the most then increase the overall volume of printed circuit board (PCB)；It addition, when printed circuit board (PCB) needs to arrange more electronic component, due to the finite surface area of printed circuit board (PCB), electronic component to arrange quantity the most limited.This electronic component can be actively or passively element, such as resistance, electric capacity etc..
Summary of the invention
Therefore, it is necessary to provide a kind of small volume and design more reasonably chip-packaging structure, the circuit board with embedded element and preparation method thereof.
A kind of making has the method for the circuit board of embedded element, including step: provide embedded structure, this embedded structure includes the first dielectric layer and electronic component, this first dielectric layer includes relative first surface and second surface, this electronic component includes multiple being conductively connected terminal, this electronic component is embedded in the first surface of this first dielectric layer and this electronic component is exposed to the surface of this first surface and flushes with this first surface, and multiple terminals that are conductively connected of this electronic component are exposed to this first surface；Multiple through hole running through this first surface and second surface is formed in this first dielectric layer；The first conductive circuit layer and the second conductive circuit layer is formed respectively at this first surface and second surface by electroplating technology, and formed in the plurality of through hole and to electrically connect this first conductive circuit layer and the conductive through hole of the second conductive circuit layer, this first conductive circuit layer includes being arranged at the terminal connecting line road on the surface that the partially electronically conductive connection terminal of this electronic component flushes with this first surface；And sequentially form the second dielectric layer and the 3rd conductive circuit layer in this first conductive circuit layer side, thus form the circuit board with embedded element.
A kind of circuit board with embedded element, including embedded structure, the first conductive circuit layer, the second conductive circuit layer, the second dielectric layer and the 3rd conductive circuit layer.This embedded structure includes the first dielectric layer and electronic component, this first dielectric layer includes relative first surface and second surface, this electronic component includes multiple being conductively connected terminal, this electronic component is embedded in the first surface of this first dielectric layer and this electronic component is exposed to the surface of this first surface and flushes with this first surface, and multiple terminals that are conductively connected of this electronic component are exposed to this first surface.This first conductive circuit layer and the second conductive circuit layer are respectively arranged at this first surface and second surface, and this first conductive circuit layer includes being arranged at the terminal connecting line road on the surface that the partially electronically conductive connection terminal of this electronic component flushes with this first surface.This second dielectric layer and the 3rd conductive circuit layer are sequentially formed in this first conductive circuit layer side.
A kind of chip-packaging structure, including circuit board and the chip as above with embedded element.This circuit board with embedded element farther includes the 3rd dielectric layer, the 4th conductive circuit layer, the first welding resisting layer and the second welding resisting layer.3rd dielectric layer and the 4th conductive circuit layer are sequentially formed in this second conductive circuit layer side, this first welding resisting layer and the second welding resisting layer are respectively formed in the 3rd conductive circuit layer and the 4th conductive circuit layer, this the first welding resisting layer part covers the 3rd conductive circuit layer, the 3rd conductive circuit layer being exposed to this first welding resisting layer constitutes the first electric connection pad, this the second welding resisting layer part covers the 4th conductive circuit layer, and the 4th conductive circuit layer being exposed to this second welding resisting layer constitutes the second electric connection pad.This chip package has on the circuit board of embedded element in this and electrically connects with this first electric connection pad.
Relative to prior art, electronic component is inserted inside circuit board by the circuit board with embedded element of the present embodiment, then the quantity of the element that can arrange on circuit board increases, and adds elasticity to the design of circuit board.It addition, the circuit board with embedded element in the present embodiment can be applicable to HDI high-density lamination plate.
Accompanying drawing explanation
Fig. 1 is the profile that two dielectric layers, two electronic components and the opposite sides that the embodiment of the present invention provides is respectively provided with the loading plate of release layer.
Fig. 2 is the sectional view of the multiple structure dielectric layer in Fig. 1, electronic component and loading plate formed according to the sequential layer poststack of dielectric layer, electronic component, loading plate, electronic component and dielectric layer.
Fig. 3 is that after being separated by the loading plate in the multiple structure of Fig. 2, the electronic component that formed embeds the sectional view of the structure in dielectric layer.
Fig. 4 is the sectional view after offering through hole in dielectric layer in figure 3.
Fig. 5 is that dielectric layer opposite sides in the diagram forms conductive circuit layer respectively and forms conductive material in through hole with the sectional view after formation conductive through hole.
Fig. 6 is the sectional view after two conductive circuit layer sides in Figure 5 sequentially form dielectric layer and conductive circuit layer respectively.
Fig. 7 be form welding resisting layer respectively in outermost conductive circuit layer in figure 6 after form the sectional view of circuit board with embedded element.
Fig. 8 is sectional view after the side of the circuit board of Fig. 7 forms solder projection.
Fig. 9 is the sectional view with the chip-packaging structure formed after encapsulation chip on the circuit board of embedded element at Fig. 8.
Main element symbol description
| First dielectric layer | 11 |
| Electronic component | 12 |
| Loading plate | 14 |
| Release layer | 13 |
| It is conductively connected terminal | 121 |
| First surface | 112 |
| Second surface | 114 |
| Embedded structure | 10 |
| Through hole | 115 |
| First conductive circuit layer | 15 |
| Second conductive circuit layer | 16 |
| Conductive through hole | 17 |
| Terminal connecting line road | 151 |
| Second dielectric layer | 18 |
| 3rd conductive circuit layer | 19 |
| 3rd dielectric layer | 20 |
| 4th conductive circuit layer | 21 |
| Conductive hole | 22 |
| First welding resisting layer | 23 |
| Second welding resisting layer | 24 |
| First electric connection pad | 25 |
| Second electric connection pad | 26 |
| There is the circuit board of embedded element | 30 |
| First surface processes layer | 27 |
| Second surface processes layer | 28 |
| Solder projection | 29 |
| Chip | 40 |
| Chip-packaging structure | 50 |
| Soldered ball | 34 |
Following detailed description of the invention will further illustrate the present invention in conjunction with above-mentioned accompanying drawing.
Detailed description of the invention
Refer to Fig. 1 to Fig. 9 embodiment of the present invention and a kind of method making chip-packaging structure is provided, comprise the steps:
Step 1: refer to Fig. 1 and Fig. 2,11, two electronic components 12 of two the first dielectric layers and loading plate 14 are provided, opposite sides at this loading plate 14 is respectively provided with release layer 13, and stacks gradually and one step press the first dielectric layer 11, electronic component 12, loading plate 14, electronic component the 12, first dielectric layer 11 become an entirety.
The material of these two the first dielectric layers 11 can be polyimides (Polyimide, PI), polyethylene terephthalate glycol (Polyethylene Terephthalate,
Or PEN (Polyethylene naphthalate, PEN), PP (Prepreg) or ABF (Ajinomoto PET)
Build-up film) etc., preferably PP or ABF, each first dielectric layer 11 all includes relative first surface 112 and second surface 114.This electronic component 12 can be actively or passively element, and such as resistance, electric capacity etc., in the present embodiment, this electronic component 12 is ceramic capacitor, including two electrodes being conductively connected terminal 121, i.e. ceramic capacitor.This loading plate 14 is for supporting and carry these two the first dielectric layers 11 and two electronic components 12 in bonding processes, and the material of this loading plate 14 can be PI, glass layer compress or metal such as copper etc..This release layer 13 for doing plasma treatment or being coated with fluorine process formation by plastic sheeting, or on the film material such as top layer of PET, PE, OPP, it being coated with the formation of silicon (silicone) mould release, this release layer 13 is for facilitating the mutual stripping of these two the first dielectric layers 11 and electronic component 12 and loading plate 14 in subsequent step.
It is understood that this quantity being conductively connected terminal 121 can also more than two, however it is not limited to the present embodiment.
This first dielectric layer 11 of pressing, electronic component 12, loading plate 14, electronic component the 12, first dielectric layer 11 can be carried out in pressing machine.After pressing, two electronic components 12 are fitted in the surface of adjacent release layer 13 respectively；The first surface 112 of two the first dielectric layers 11 is relative with corresponding release layer 13 and fits in the surface of corresponding release layer 13 under pressure force effect respectively, and make each electronic component 12 be embedded in the first surface 112 of the first corresponding dielectric layer 11, each electronic component 12 is adjacent to the corresponding surface of release layer 13 and flushes with the first surface 112 of the first corresponding dielectric layer 11, and two of each electronic component 12 are conductively connected terminal 121 and are exposed to first surface 112, the thickness of each first dielectric layer 11 is more than the thickness of corresponding electronic component 12.
Step 2: refer to Fig. 3, utilizes stripping process this loading plate 14 and two release layers 13 to be removed, and obtains two embedded structures 10 including the first dielectric layer 11 and the electronic component 12 being embedded in this first dielectric layer 11.
Because being respectively provided with release layer 13 between this loading plate 14 and the first dielectric layer 11 and electronic component 12, utilize the rippability of release layer 13, easily this loading plate 14 and release layer 13 can be peeled off removal, thus the structure of loading plate 14 opposite sides is separated from each other, form two embedded structures 10.
Two embedded structure 10 structures are identical, illustrate with one of them below.This embedded structure 10 includes the first dielectric layer 11 and is embedded in the electronic component 12 of first surface 112 of this first dielectric layer 11, this electronic component 12 is exposed to the surface of this first surface 112 and flushes with this first surface 112, and two of electronic component 12 are conductively connected terminal 121 and are exposed to this first surface 112.
Step 3: refer to Fig. 4, forms the multiple through holes 115 running through this first surface 112 and second surface 114 on this dielectric layer.The method forming the plurality of through hole 115 can be laser pit or machine drilling.
Step 4: refer to Fig. 5, the surface being exposed to this first surface 112 at this first surface 112 and this electronic component 12 by electric plating method forms the first conductive circuit layer 15, form the second conductive circuit layer 16 at this second surface 114, and in the plurality of through hole 115, form the conductive through hole 17 making this first conductive circuit layer 15 and the second conductive circuit layer 16 conduct respectively.
Form the method for first conductive circuit layer the 15, second conductive circuit layer 16 and conductive through hole 17 by electric plating method and specifically include following steps:
First, embedded structure 10 is carried out, the waste residue etc. of residual when removing its surface blot and carry out step 3 pit or bore process, makes the surface of embedded structure 10 and the inwall cleaning of through hole 115, be beneficial to the carrying out of subsequent step.
Secondly, it is exposed to the surface of first surface 112 and the inwall formation conducting film (not shown) of through hole 115 by the method for electroless copper at first surface 112 and second surface 114, this electronic component 12 of this first dielectric layer 11.It is appreciated that the technique forming this conducting film can also not be limited with the present embodiment for black holes metallization processes, shadow technique etc..
Again, it is provided that the photoresist oxidant layer (not shown) of patterning, making the region of pre-formed first conductive circuit layer the 15, second conductive circuit layer 16 and conductive through hole 17 be exposed to this photoresist oxidant layer, other region is blocked by this photoresist oxidant layer.
Further, the embedded structure 10 defining conducting film and photoresist oxidant layer is inserted electroplating bath and connects electrode and electroplate, the conducting film being exposed to this photoresist oxidant layer is formed copper electroplating layer.In electroplating process, copper electroplating layer fills up this through hole 115, forms this conductive through hole 17.
Finally, remove this photoresist oxidant layer, and etch the conducting film that removal is blocked by this photoresist oxidant layer, form the first conductive circuit layer the 15, second conductive circuit layer 16 and conductive through hole 17.
This first conductive circuit layer 15 includes two terminal connecting line roads 151, and these two electrode connecting line roads 151 are at least partly formed at these two respectively and are conductively connected terminal 121 surface, is conductively connected terminal 121 being electrically connected these two.
It is understandable that, one of them is conductively connected terminal 121 and can not also electrically connect with the first conductive circuit layer 15, but electrically connected with the second conductive circuit layer 16 by conductive blind hole (not shown), another is conductively connected terminal 121 and electrically connects with the first conductive circuit layer 15 yet by terminal connecting line road 151, the most partially electronically conductive connection terminal 121 electrically connects with the first conductive circuit layer 15, remainder is conductively connected terminal 121 and is electrically connected by conductive blind hole and the second conductive circuit layer 16, is not limited with the present embodiment.The manufacture method of this conductive blind hole is as follows: formed through this second surface 114 a connection wherein blind hole being conductively connected terminal 121 in this first dielectric layer 11, the terminal 121 that is conductively connected making correspondence is exposed to this second surface 114 from this blind hole, while formed first conductive circuit layer the 15, second conductive circuit layer 16 and conductive through hole 17 by electroplating technology, formed in this blind hole and this second conductive circuit layer 16 is conductively connected, with corresponding, the conductive blind hole that terminal 121 electrically connects.
Step 5: refer to Fig. 6, sequentially forms the second dielectric layer 18 and the 3rd conductive circuit layer 19, and sequentially forms the 3rd dielectric layer 20 and the 4th conductive circuit layer 21 in this second conductive circuit layer 16 side in this first conductive circuit layer 15 side.
This second dielectric layer 18 and the 3rd conductive circuit layer 19 and the 3rd dielectric layer 20 and the 4th conductive circuit layer 21 can be made by Layer increasing method respectively and be formed.Between 3rd conductive circuit layer 19 and this first conductive circuit layer 15, and can be electrically connected by the conductive hole 22 being formed in this second dielectric layer 18 and the 3rd dielectric layer 20 respectively between the 4th conductive circuit layer 21 with this second conductive circuit layer 16.
Step 6: refer to Fig. 7, the first welding resisting layer 23 is covered in the 3rd conductive circuit layer 19 upper part, and cover the second welding resisting layer 24 in the 4th conductive circuit layer 21 upper part, the 3rd conductive circuit layer 19 being exposed to this first welding resisting layer 23 constitutes multiple first electric connection pad 25, the 4th conductive circuit layer 21 being exposed to this second welding resisting layer 24 constitutes multiple second electric connection pad 26, thus forms the circuit board 30 with embedded element.
In the present embodiment, this first electric connection pad 25 and the second electric connection pad 26 are arranged in array respectively, this first electric connection pad 25 is for electrically connecting with chip (chip 40 as in Fig. 9), and this second electric connection pad 26 is for electrically connecting with other electronic equipment such as circuit board etc..
It is appreciated that, more dielectric layer and conductive circuit layer can be set between the 3rd conductive circuit layer 19 and this first conductive circuit layer 15 and between the 4th conductive circuit layer 21 and this second conductive circuit layer 16 respectively further, to form the circuit board with more conductive circuit layer.Can also not be limited with one of the present embodiment for multiple it addition, this has the quantity of electronic component 12 in the circuit board 30 of embedded element.
As it is shown in fig. 7, the circuit board 30 with embedded element of the present embodiment includes embedded structure the 10, first conductive circuit layer the 15, second conductive circuit layer the 16, second dielectric layer the 18, the 3rd conductive circuit layer the 19, the 3rd dielectric layer the 20, the 4th conductive circuit layer the 21, first welding resisting layer 23 and the second welding resisting layer 24.This first conductive circuit layer 15 is formed at the first surface 112 of this first dielectric layer 11 and this electronic component 12 is exposed to the surface of this first surface 112, second conductive circuit layer 16 is formed at the second surface of the first dielectric layer 11, this first conductive circuit layer 15 includes two terminal connecting line roads 151, these two terminal connecting line roads 151 are at least partly formed at these two respectively and are conductively connected terminal 121 surface, are conductively connected terminal 121 being electrically connected these two.Electrical connection this first conductive circuit layer 15 and conductive through hole 17 of the second conductive circuit layer 16 it is formed with in this first dielectric layer 11.This second dielectric layer 18 and the 3rd conductive circuit layer 19 are sequentially formed in this first conductive circuit layer 15 side, 3rd dielectric layer 20 and the 4th conductive circuit layer 21 are sequentially formed in this second conductive circuit layer 16 side, between 3rd conductive circuit layer 19 and this first conductive circuit layer 15, and electrically connected by the conductive hole 22 being formed in this second dielectric layer 18 and the 3rd dielectric layer 20 respectively between the 4th conductive circuit layer 21 with this second conductive circuit layer 16.This first welding resisting layer 23 is formed in the 3rd conductive circuit layer 19 and part covers the 3rd conductive circuit layer 19, and the 3rd conductive circuit layer 19 being exposed to this first welding resisting layer 23 constitutes multiple first electric connection pad 25；This second welding resisting layer 24 is formed in the 4th conductive circuit layer 21 and part covers the 4th conductive circuit layer 21, and the 4th conductive circuit layer 21 being exposed to this second welding resisting layer 24 constitutes multiple second electric connection pad 26.
Step 7: refer to Fig. 8, this first electric connection pad 25 and the second electric connection pad 26 are carried out surface gold-plating, form first surface respectively at this first electric connection pad 25 and the second electric connection pad 26 and process layer 27 and second surface process layer 28, and process layer 27 surface formation solder projection 29 at this first surface.
This first surface processes layer 27 and second surface processes layer 28 and is used for protecting this first electric connection pad 25 and the second electric connection pad 26 to prevent it from aoxidizing.The plurality of first surface processes layer 27 and second surface processes layer 28 and conducts with the first corresponding electric connection pad 25 and the second electric connection pad 26 respectively.It is appreciated that forming this first surface processes layer 27 and second surface and process the method for layer 28 and can also be substituted by plating nickel gold, change nickel leaching gold, nickel plating porpezite, tin plating etc., is not limited with the present embodiment.
In the present embodiment, the first surface can being respectively formed on the plurality of first electric connection pad 25 by multiple solder projections 29 by the way of plating or printing processes the surface of layer 27, and the plurality of solder projection 29 protrudes from the surface of this first welding resisting layer 23.This solder projection 29 can be column, spherical etc., is column in the present embodiment, and its material is typically mainly stannum.It is understood that this first surface processes layer 27 and second surface processes layer 28 and can also omit, now this solder projection 29 is formed directly into the surface of this first electric connection pad 25.
Step 8: refer to Fig. 9, it is provided that chip 40, and chip 40 is electrically connected to the plurality of first electric connection pad 25 and is packaged in this circuit board 30 with embedded element, form chip-packaging structure 50.
In the present embodiment, this chip 40 is chip package (flip-chip) chip, this chip 40 have respectively with the plurality of first electric connection pad 25 the most multiple contact tab (not shown), this contact tab is typically also made up of solder, and its material is mainly stannum.The plurality of contact tab can be adopted with the following method with the connection of corresponding solder projection 29: first, is arranged at by chip 40 on the circuit board 30 with embedded element, and makes the plurality of contact tab contact with corresponding solder projection 29 respectively；Then, by this chip 40 together with the circuit board 30 with embedded element through Overwelding and rewelding furnace, make contact tab and solder projection 29 is melted combine after form soldered ball 34 and cool and solidify, so that contact tab and solder projection 29 are connected with each other and conduct.It is understood that this chip 40 can also be wire bonding (wire
Bonding, WB) chip, known method for packing can be used to be packaged in this circuit board 30 with embedded element, be not limited with the present embodiment.
As it is shown in figure 9, the chip-packaging structure 50 of the present embodiment includes the circuit board 30 with embedded element and is packaged in the chip 40 of this circuit board 30 with embedded element.This chip 40 is electrically connected with the circuit board 30 with embedded element by the multiple soldered balls 34 being formed between this first electric connection pad 25 with this chip 40, one end of each soldered ball 34 is welded in this first electric connection pad 25, the relative other end is connected to this chip 40, and the material of this soldered ball 34 mainly includes stannum.
Relative to prior art, electronic component 12 is inserted inside circuit board by the circuit board 30 with embedded element of the present embodiment, then the quantity of the element that can arrange on circuit board increases, and adds elasticity to the design of circuit board.It addition, the circuit board 30 with embedded element in the present embodiment can be applicable to HDI high-density lamination plate.
It is understood that for the person of ordinary skill of the art, can conceive according to the technology of the present invention and make other various corresponding changes and deformation, and all these change all should belong to the protection domain of the claims in the present invention with deformation.
Claims (11)
1. making has the method for circuit board for embedded element, including step:
There is provided two the first dielectric layers, two electronic components and loading plate, relative at this loading plate
Both sides are respectively provided with release layer, and stack gradually and one step press the first dielectric layer, electronics unit
Part, loading plate, electronic component, the first dielectric layer become an entirety；
Utilize stripping process this loading plate and two release layers to be removed, obtain two and include first Jie
Electric layer and the embedded structure of electronic component being embedded in this first dielectric layer；This embedded structure
Including the first dielectric layer and electronic component, this first dielectric layer include relative first surface and
Second surface, this electronic component includes multiple being conductively connected terminal, and this electronic component is embedded in
The first surface of this first dielectric layer and this electronic component be exposed to the surface of this first surface with
This first surface flushes, and multiple terminals that are conductively connected of this electronic component are exposed to this first table
Face:
Multiple through hole running through this first surface and second surface is formed in this first dielectric layer；
By electroplating technology this first surface and second surface formed respectively the first conductive circuit layer and
Second conductive circuit layer, and in the plurality of through hole, form this first conductive circuit layer of electrical connection
With the conductive through hole of the second conductive circuit layer, this first conductive circuit layer includes being arranged at this electricity
The terminal on surface that the partially electronically conductive connection terminal of sub-element flushes with this first surface is connected
Circuit；And
The second dielectric layer and the 3rd conductive circuit layer is sequentially formed in this first conductive circuit layer side,
Thus form the circuit board with embedded element.
2. the method making the circuit board with embedded element as claimed in claim 1, its feature
Being, this first conductive circuit layer farther includes to be arranged at multiple conductions of this electronic component
Other parts in terminal are conductively connected the terminal on the surface that terminal flushes with this first surface
Connection line.
3. the method making the circuit board with embedded element as claimed in claim 1, its feature
It is, is forming the first conduction by electroplating technology respectively at this first surface and second surface
When line layer and the second conductive circuit layer, formed and this electronic component in this first dielectric layer
Multiple conducting terminals in other parts be conductively connected terminal and this second conductive circuit layer electricity
The conductive blind hole connected.
4. the method making the circuit board with embedded element as claimed in claim 1, its feature
It is, farther includes step: sequentially form the 3rd Jie in this second conductive circuit layer side
Electric layer and the 4th conductive circuit layer, and in the 3rd conductive circuit layer and the 4th conductive circuit layer
Upper form the first welding resisting layer and the second welding resisting layer respectively, this first welding resisting layer part cover this
Three conductive circuit layer, the 3rd conductive circuit layer being exposed to this first welding resisting layer constitutes the first electricity
Property connection gasket, this second welding resisting layer part covers the 4th conductive circuit layer, be exposed to this
4th conductive circuit layer of two welding resisting layers constitutes the second electric connection pad.
5. there is a circuit board for embedded element, including:
Embedded structure, this embedded structure includes the first dielectric layer and electronic component, this first dielectric layer
Including relative first surface and second surface, this electronic component includes multiple being conductively connected end
Son, this electronic component is embedded in the first surface of this first dielectric layer, this electronic component with should
It is in close contact between first dielectric layer, there is not space；This electronic component be exposed to this first
The surface on surface flushes with this first surface, and the multiple of this electronic component are conductively connected terminal dew
For this first surface；
First conductive circuit layer and the second conductive circuit layer, be respectively arranged at this first surface and second
Surface, this first conductive circuit layer includes the partially electronically conductive connection end being arranged at this electronic component
The terminal connecting line road on surface that son flushes with this first surface；And
Second dielectric layer and the 3rd conductive circuit layer, be sequentially formed in this first conductive circuit layer side.
There is the circuit board of embedded element the most as claimed in claim 5, it is characterised in that this is years old
One conductive circuit layer farther includes to be arranged at the other parts of this electronic component and is conductively connected end
The terminal connecting line road on surface that son flushes with this first surface.
There is the circuit board of embedded element the most as claimed in claim 5, it is characterised in that this is years old
Have in one dielectric layer and conduct electricity even with the other parts in multiple conducting terminals of this electronic component
Connecting terminal and the conductive blind hole of this second conductive circuit layer electrical connection.
There is the circuit board of embedded element the most as claimed in claim 5, it is characterised in that this tool
The circuit board having embedded element farther include the 3rd dielectric layer, the 4th conductive circuit layer,
One welding resisting layer and the second welding resisting layer, the 3rd dielectric layer and the 4th conductive circuit layer sequentially form
In this second conductive circuit layer side, this first welding resisting layer and the second welding resisting layer are respectively formed in
In 3rd conductive circuit layer and the 4th conductive circuit layer, this first welding resisting layer part covers should
3rd conductive circuit layer, the 3rd conductive circuit layer being exposed to this first welding resisting layer constitutes first
Electric connection pad, this second welding resisting layer part covers the 4th conductive circuit layer, is exposed to this
4th conductive circuit layer of the second welding resisting layer constitutes the second electric connection pad.
9. a chip-packaging structure, including the electricity as claimed in claim 8 with embedded element
Road plate and chip, this chip package in this have on the circuit board of embedded element and with this first
Electric connection pad electrically connects.
10. chip-packaging structure as claimed in claim 9, it is characterised in that this first conduction
Line layer farther includes to be arranged at the other parts of this electronic component and is conductively connected terminal and is somebody's turn to do
Terminal connecting line road on the surface that first surface flushes.
11. chip-packaging structures as claimed in claim 9, it is characterised in that this first dielectric
Have in Ceng and be conductively connected terminal with the other parts in multiple conducting terminals of this electronic component
And the conductive blind hole of this second conductive circuit layer electrical connection.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210577545.XA CN103906370B (en) | 2012-12-27 | 2012-12-27 | Chip packaging structure, circuit board having embedded component and manufacturing method thereof |
| TW102101268A TWI466611B (en) | 2012-12-27 | 2013-01-14 | Printed circuit board having buried component, method for manufacturing same and chip package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210577545.XA CN103906370B (en) | 2012-12-27 | 2012-12-27 | Chip packaging structure, circuit board having embedded component and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103906370A CN103906370A (en) | 2014-07-02 |
| CN103906370B true CN103906370B (en) | 2017-01-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210577545.XA Active CN103906370B (en) | 2012-12-27 | 2012-12-27 | Chip packaging structure, circuit board having embedded component and manufacturing method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103906370B (en) |
| TW (1) | TWI466611B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448856B (en) * | 2014-09-01 | 2018-04-06 | 碁鼎科技秦皇岛有限公司 | Chip-packaging structure, preparation method and chip package base plate |
| TWI611523B (en) * | 2014-09-05 | 2018-01-11 | 矽品精密工業股份有限公司 | Method for fabricating semiconductor package |
| TWI571185B (en) * | 2014-10-15 | 2017-02-11 | 矽品精密工業股份有限公司 | Electronic package and method of manufacture |
| CN111354687B (en) * | 2018-12-21 | 2023-12-15 | 深南电路股份有限公司 | Packaging structure and preparation method thereof |
| TWI762777B (en) * | 2019-03-27 | 2022-05-01 | 恆勁科技股份有限公司 | Semiconductor package substrate and manufacturing method thereof and electronic package and manufacturing method thereof |
| WO2023272642A1 (en) | 2021-06-30 | 2023-01-05 | 深南电路股份有限公司 | Electronic component package, electronic component, voltage regulator module, and voltage stabilizing device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1518080A (en) * | 2003-01-23 | 2004-08-04 | 新光电气工业株式会社 | Electronic element packaging structure and its manufacturing method |
| CN101594740A (en) * | 2008-05-27 | 2009-12-02 | 华通电脑股份有限公司 | Circuit board with embedded electronic device and method thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI263313B (en) * | 2005-08-15 | 2006-10-01 | Phoenix Prec Technology Corp | Stack structure of semiconductor component embedded in supporting board |
| TWI365689B (en) * | 2007-12-19 | 2012-06-01 | Unimicron Technology Corp | Embedded circuit board and manufacturing method thereof |
| TWI389279B (en) * | 2009-01-23 | 2013-03-11 | Unimicron Technology Corp | Printed circuit board structure and fabrication method thereof |
-
2012
- 2012-12-27 CN CN201210577545.XA patent/CN103906370B/en active Active
-
2013
- 2013-01-14 TW TW102101268A patent/TWI466611B/en active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1518080A (en) * | 2003-01-23 | 2004-08-04 | 新光电气工业株式会社 | Electronic element packaging structure and its manufacturing method |
| CN101594740A (en) * | 2008-05-27 | 2009-12-02 | 华通电脑股份有限公司 | Circuit board with embedded electronic device and method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201427523A (en) | 2014-07-01 |
| CN103906370A (en) | 2014-07-02 |
| TWI466611B (en) | 2014-12-21 |
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