CN103872670B

CN103872670B - Electrostatic discharge protection circuit, bias circuit and electronic device

Info

Publication number: CN103872670B
Application number: CN201210578414.3A
Authority: CN
Inventors: 陈哲宏; 杨宗翰
Original assignee: Microchip Technology Inc
Current assignee: British Cayman Islands Business Miley Electronic Ltd By Share Ltd; Microchip Technology Inc
Priority date: 2012-12-07
Filing date: 2012-12-27
Publication date: 2017-05-31
Anticipated expiration: 2032-12-27
Also published as: TWI455435B; TW201424181A; CN103872670A

Abstract

The invention discloses an electrostatic discharge protection circuit, a bias circuit and an electronic device. The trigger unit has an input end and an output end for triggering the clamping unit. The control unit receives the transformation enabling signal to start the trigger unit, and determines the opening or closing of the current discharge channel in the clamping unit by the transformation enabling signal, wherein when the transformation enabling signal is a low voltage level, the trigger unit can open the current discharge channel of the clamping unit so as to protect the bias circuit from damage caused by instantaneous high voltage generated by static electricity.

Description

ESD protection circuit, bias circuit and electronic installation

Technical field

The present invention is related to a kind of ESD protection circuit, and especially with regard to one kind when bias circuit is closed, The discharge channel for automatically turning on ESD protection circuit is discharged to rapidly earthing potential with by bias circuit current potential.

Background technology

Typically in IC design, the power management of IC interior often can drop voltage-stablizer using to linear low voltage (Linear Low-dropout Regulator, LDO), while for the stability of compensation low dropout voltage-stablizer, can be in output End hangs up the capacity cell of larger capacitance value.But, in integrated circuit, capacity cell quite accounts for area, so big portion Dividing can all select that this compensating electric capacity is placed on the outside of integrated circuit, that is, on printed circuit board (PCB).

Therefore, the output voltage terminal of IC interior low dropout voltage regulator, it is necessary to by padding (Pad) via lead (bond wire) is connected to the pin of encapsulation position and can just be established a connection with the electric capacity on printed circuit board (PCB).Wherein, pad (Pad) must design with static discharge (Electrostatic discharge, ESD) protection, to prevent IC interior Low dropout voltage regulator be subjected to electrostatic breakdown.In general, the design of electrostatic discharge protective must under normal operation in height Resistance state pattern, but the electrostatic discharging path of low resistance can be provided being subjected to when electrostatic bombards, to avoid electrostatic charge to collection The big voltage (such as kilovolt grade) of moment is produced into circuit and cause damage.

Figure 1A is refer to, Figure 1A is the circuit diagram of existing bias circuit.As shown in Figure 1A.Existing bias circuit 10 is wrapped Low dropout voltage regulator 12 and ESD protection circuit 14 are included, wherein ESD protection circuit 14 is coupled to low dropout voltage regulator 12.Low dropout voltage regulator 12 includes amplifier OP ', P-type transistor MP ' and feedback resistance R1 ', R2 '.The compensation electricity of chip exterior Hold CL ' through being connected with feedback resistance R1 ' with the drain electrode of P-type transistor MP '.Wherein, the negative input end of amplifier OP ' receives one and joins Voltage VREF ' is examined, the positive input terminal of amplifier OP ' receives feedback voltage V F '.The source electrode of P-type transistor MP ' receives input voltage VIN’。

Generation action when can only be bombarded being subjected to electrostatic due to ESD protection circuit 14, therefore work as low dropout voltage regulator 12 from normal operating conditions close when, stored electric charge can only be connected via feedback resistance R1 ', R2 ' on load capacitance CL Path be discharged to ground, without flowing to ESD protection circuit 14.It is general in order that the circuit power saving of low dropout voltage regulator 12, The resistance value of feedback resistance R1, R2 can be designed in kilohm (k Ω) grade, low dropout voltage regulator 12 is reached relatively low quiet State loss current (Quiescent Current).So, when electric charge from μ F grades of load capacitance CL ' via k Ω grades R1 ' and During R2 ' conductive discharges to ground, it may be necessary to which the time more than several tens of seconds can be discharged completely.

Therefore, if it is desired to low dropout voltage regulator 12 from normal operating conditions close when, output voltage VO UT can be quick It is discharged to ground, it will usually additionally add a discharge path.

Figure 1B is refer to, Figure 1B is the schematic diagram of another existing bias circuit.As shown in Figure 1B, from unlike Figure 1A, The extra discharge path for adding is made up of resistance R3 ' (ohm level) and N-type transistor MN ' in Figure 1B.N-type transistor MN's ' Grid receives a switching signal LDO_enb opposite with the enable signal LDO_en of low dropout voltage regulator.Therefore, low pressure drop is steady During 12 normal work of depressor, N-type transistor MN ' is closed.When low dropout voltage regulator 12 is closed from normal operating conditions, N-type is brilliant Body pipe MN ' conducting form discharge path, enable electric charge stored on load capacitance CL ' via resistance R3 ' repid discharges extremely Ground.

In fig. ib, the resistance value of resistance R3 ' is smaller, and the discharge current of moment is bigger, and the speed of electric discharge is also faster, but by Outside is connected directly in this pin position, is thus susceptible to be subjected to electrostatic bombardment, under the design consideration of ESD protection circuit, must The resistance of R3 must be increased to increase the repellence of electrostatic bombardment, but being so designed that not only increases layout area, and reduce again The speed of the charge discharge on load capacitance CL '.

The content of the invention

It is an object of the invention to provide a kind of ESD protection circuit, the ESD protection circuit includes strangulation Unit, trigger element and control unit.Strangulation unit is coupled between positive power line and negative power line.Trigger element has input With output end, trigger element coupling negative power line and reference voltage, and output end are coupled to strangulation unit and are used to trigger pincers Unit processed.Control unit is coupled to the input of positive power line, negative power line and the trigger element, and control unit receives transformation Enable signal thereby determines that the current discharge passage of strangulation unit is turned on and off to trigger trigger element, wherein when this When transformation enable signal is a low voltage level, the trigger element can open the current discharge passage of strangulation unit.

The embodiment of the present invention provides a kind of bias circuit, and bias circuit includes voltage conversion circuit with electrostatic discharge (ESD) protection electricity Road.The input voltage that voltage conversion circuit is used to be received is converted to output voltage, and wherein output voltage is stored in negative Carry electric capacity.ESD protection circuit is electrically connected to output voltage, and ESD protection circuit is received and according to transformation enable Signal determines being turned on and off for its internal current discharge passage.When transformation enable signal is low voltage level, bias Circuit is closed, and ESD protection circuit firing current discharge channel, and the self-supported electric capacity inflow of discharge current Current discharge passage, by the electric charge release in load capacitance.

In one of embodiment of the invention, control unit includes control resistance with control electric capacity.The one of control resistance End is electrically connected with positive power line, controls the other end of resistance to receive transformation enable signal.One end of electric capacity is controlled to be electrically connected with control The other end of resistance processed, controls the other end of electric capacity to be electrically connected with ground voltage.

In one of embodiment of the invention, trigger element includes p-type triggering transistor AND gate N-type triggering transistor.P-type The grid for triggering transistor is electrically connected with the other end of 3rd resistor, and the source electrode of p-type triggering transistor is electrically connected with reference voltage, It is used to, when current discharge passage is opened, the electric charge in load capacitance can be released.The grid of N-type triggering transistor is electrical Electricity connects the other end of 3rd resistor, and the drain electrode of N-type triggering transistor is electrically connected with the drain electrode of the second P-type transistor, and N-type triggering is brilliant The source electrode of body pipe is electrically connected with negative power line.

In one of embodiment of the invention, strangulation unit includes N-type clamp transistor.The grid of N-type clamp transistor Pole is electrically connected with the drain electrode that N-type triggers transistor, and the drain electrode of N-type clamp transistor is electrically connected with output capacitance, N-type strangulation crystal The source electrode of pipe is electrically connected with negative power line.P-type triggering transistor AND gate N-type triggering transistor constitutes phase inverter, when transformation enable letter During number for high-voltage level, then p-type triggering transistor is closed and N-type triggering transistor is opened, and the grid of N-type clamp transistor The voltage of negative power line is received, to close current discharge passage, when transformation enable signal is low voltage level, then p-type triggering Transistor is opened and N-type triggering transistor is closed, and the grid of N-type clamp transistor receives reference voltage, is put with firing current Electric channel.

In one of embodiment of the invention, ESD protection circuit further includes catching diode.Catching diode Anode be electrically connected with positive power line, the negative electrode of catching diode is electrically connected with the source electrode that p-type triggers transistor, catching diode It is used to the voltage level of the source electrode for determining p-type triggering transistor.In one of embodiment of the invention, when transformation enable signal It is high-voltage level, bias circuit is in normal operating conditions, and voltage conversion circuit is enabled, and ESD protection circuit Current discharge passage is closed, voltage conversion circuit exports charging current to load capacitance to produce output voltage.

In one of embodiment of the invention, voltage conversion circuit is low dropout voltage regulator, is used to give input voltage With step-down and regulated output voltage.

In one of embodiment of the invention, low dropout voltage regulator includes the first amplifier, the first P-type transistor, the One resistance and second resistance.The negative input end of the first amplifier receives reference voltage, the output end output first of the first amplifier Voltage.The grid of the first P-type transistor receives first voltage, and the source electrode of the first P-type transistor is electrically connected with input voltage, first The drain electrode output output voltage of P-type transistor.One end of first resistor is electrically connected with the drain electrode of the first P-type transistor, the first electricity The other end of resistance exports feedback voltage and feedback voltage is sent to the positive input terminal of the first amplifier.One end electricity of second resistance Property connection first resistor the other end, the other end of second resistance is electrically connected with ground voltage.When feedback voltage is more than with reference to electricity During pressure, then first voltage rises and flows through the electric current decline of first and second resistance, and then reduces output voltage, works as feedback voltage During less than reference voltage, then first voltage declines and flows through the electric current rising of first and second resistance, and then increases output voltage.

In one of embodiment of the invention, ESD protection circuit includes strangulation unit, a trigger element and Control unit.Described control unit includes 3rd resistor and the first electric capacity.The trigger element includes the second P-type transistor and the One N-type transistor.The strangulation unit includes the second N-type transistor.One end of 3rd resistor is electrically connected with the first P-type transistor Drain electrode, the other end of 3rd resistor receives transformation enable signal.One end of first electric capacity is electrically connected with the another of 3rd resistor End, the other end of the first electric capacity is electrically connected with ground voltage.The grid of the second P-type transistor is electrically connected with the another of 3rd resistor End, the source electrode of the second P-type transistor is electrically connected with the second voltage of stabilization, is used to when current discharge passage is opened, can be by Electric charge in load capacitance is released.The electrical electricity of grid of the first N-type transistor connects the other end of 3rd resistor, and the first N-type is brilliant The drain electrode of body pipe is electrically connected with the drain electrode of the second P-type transistor, and the source electrode of the first N-type transistor is electrically connected with ground voltage.The The grid of two N-type transistors is electrically connected with the drain electrode of the first N-type transistor, and the drain electrode of the second N-type transistor is electrically connected with output Voltage, the source electrode of the second N-type transistor is electrically connected with ground voltage.Wherein the second P-type transistor and the first N-type transistor are constituted Phase inverter, when transformation enable signal is high-voltage level, then the second P-type transistor is closed and the first N-type transistor is opened, and The grid of the second N-type transistor receives ground voltage, to close current discharge passage, when transformation enable signal is low voltage level When, then the second P-type transistor is opened and the first N-type transistor is closed, and the grid of the second N-type transistor receives second voltage, With firing current discharge channel.

In one of embodiment of the invention, ESD protection circuit further includes the first diode.First diode Anode be electrically connected with output voltage, the negative electrode of the first diode is electrically connected with the source electrode of the second P-type transistor, works as bias circuit Cause that output voltage rises extremely when being bombarded by electrostatic, then the voltage of the source electrode of the second P-type transistor subtracts for output voltage The conducting voltage of the first diode is gone, to maintain the unlatching of current discharge passage in discharge process.

In one of embodiment of the invention, ESD protection circuit include the 3rd P-type transistor, the second electric capacity, 4th P-type transistor, the 3rd N-type transistor and the 4th N-type transistor.The grid of the 3rd P-type transistor receives transformation enable letter Number, the source electrode of the 3rd P-type transistor is electrically connected with output voltage.One end of second electric capacity is electrically connected with the 3rd P-type transistor Drain electrode, the other end of the second electric capacity is electrically connected with ground voltage.The grid of the 4th P-type transistor is electrically connected with the 3rd P-type crystal The drain electrode of pipe, the source electrode of the 4th P-type transistor is electrically connected with the tertiary voltage of stabilization, is used to when current discharge passage is opened, Electric charge in load capacitance can be released.The electrical electricity of grid of the 3rd N-type transistor connects the drain electrode of the 3rd P-type transistor, The drain electrode of the 3rd N-type transistor is electrically connected with the drain electrode of the 4th P-type transistor, and the source electrode of the 3rd N-type transistor connects Ground voltage.The grid of the 4th N-type transistor is electrically connected with the drain electrode of the 3rd N-type transistor, and the drain electrode of the 4th N-type transistor is electrical Connection output voltage, the source electrode of the 4th N-type transistor is electrically connected with ground voltage.Wherein the 4th P-type transistor and the 3rd N-type are brilliant Body pipe constitutes phase inverter, and when transformation enable signal is high-voltage level, then the 3rd and the 4th P-type transistor is closed and the 3rd N Transistor npn npn is opened, and the grid of the 4th N-type transistor receives ground voltage, to close current discharge passage, when transformation enable When signal is low voltage level, then the 3rd and the 4th P-type transistor is opened and the 3rd N-type transistor is closed, and the 4th N-type crystal The grid of pipe receives tertiary voltage, with firing current discharge channel.

In one of embodiment of the invention, ESD protection circuit further includes the second diode.Second diode Anode be electrically connected with output voltage, the negative electrode of the second diode is electrically connected with the source electrode of the 4th P-type transistor, works as bias circuit Cause that output voltage rises extremely when being bombarded by electrostatic, then the voltage of the source electrode of the 4th P-type transistor subtracts for output voltage The conducting voltage of the second diode is gone, to maintain the unlatching of current discharge passage in discharge process.

The embodiment of the present invention separately provides a kind of electronic installation, and the electronic installation includes bias circuit and load, wherein negative Carry and be electrically connected with bias circuit, to receive output voltage.Bias circuit includes voltage conversion circuit and ESD protection circuit. The input voltage that voltage conversion circuit is used to be received is converted to output voltage, and wherein output voltage is stored in load electricity Hold.ESD protection circuit is electrically connected to output voltage, and ESD protection circuit is received and according to transformation enable signal To determine being turned on and off for its internal current discharge passage.When transformation enable signal is low voltage level, bias circuit It is closed, and ESD protection circuit firing current discharge channel, and the self-supported electric capacity inflow current of discharge current Discharge channel, by the electric charge release in load capacitance.

In sum, the embodiment of the present invention proposes bias circuit and electronic installation, when transformation enable signal is low-voltage During level, bias circuit is closed from normal operating conditions, and ESD protection circuit can be forced firing current discharge channel, make Obtaining discharge current being capable of self-supported electric capacity inflow current discharge channel.Accordingly, this disclosure need not only increase extra Layout area is just capable of the discharge time of efficient reduction load capacitance, the cost of integrated circuit can more declined and improves inclined The antistatic effect of volt circuit.

For enable be further understood that feature of the invention and technology contents, refer to below in connection with it is of the invention specifically Bright and accompanying drawing, but this multiple explanation is only used for illustrating the present invention with institute's accompanying drawings, rather than to scope of the presently claimed invention Make any limitation.

Brief description of the drawings

Explain specific embodiment of the invention with reference to alterations above, thereby can be more bright to the present invention In vain, in the schema such as this：

Figure 1A is the circuit diagram of existing bias circuit.

Figure 1B is the schematic diagram of another existing bias circuit.

Fig. 2A is the block diagram of the ESD protection circuit according to the embodiment of the present invention.

Fig. 2 B are the block diagram of the ESD protection circuit according to the embodiment of the present invention.

Fig. 3 A are the schematic diagram of the bias circuit according to the embodiment of the present invention.

Fig. 3 B are the schematic diagram for not going up electrical bias circuit according to the embodiment of the present invention.

Fig. 3 C are the schematic diagram of the bias circuit in normal operating conditions according to the embodiment of the present invention.

Fig. 3 D are the signal according to the transient state bias circuit for switching to closed mode in the embodiment of the present invention from working condition Figure.

Fig. 4 is the physical circuit schematic diagram of the bias circuit according to another embodiment of the present invention.

Fig. 5 A are the voltage time oscillogram of the discharge waveform of existing bias circuit.

Fig. 5 B are the voltage time oscillogram of the discharge waveform of the bias circuit of corresponding diagram 3D.

Fig. 6 is the specific schematic diagram for not going up electrical bias circuit according to another embodiment of the present invention.

Fig. 7 is the physical circuit figure of the bias circuit according to yet another embodiment of the invention.

Fig. 8 is the specific schematic diagram for not going up electrical bias circuit according to yet another embodiment of the invention.

Fig. 9 is the schematic diagram of the electronic installation of the embodiment of the present invention.

Wherein, description of reference numerals is as follows：

10、20：Existing bias circuit

12：Low dropout voltage regulator

14：ESD protection circuit

200：ESD protection circuit

210：Control unit

220：Trigger element

230：Strangulation unit

300、400、600、700、800：Bias circuit

310：Voltage conversion circuit

320：ESD protection circuit

410：Low dropout voltage regulator

900：Electronic installation

910：Bias circuit

920：Load

C：Output capacitance

C1：First electric capacity

C2：Second electric capacity

CL’、CL：Load capacitance

CS：Control signal

D1：First diode

D2：Second diode

ENS：Transformation enable signal

GND：Ground voltage

I1：Electric current

IC：Charging current

ID：Discharge current

IES：Electrostatic induced current

LDO_en：Enable signal

LDO_enb：Switching signal

MN’：N-type transistor

MN1：First N-type transistor

MN2：Second N-type transistor

MN3：3rd N-type transistor

MN4：4th N-type transistor

MNT：N-type triggers transistor

MNC：N-type clamp transistor

MP’：P-type transistor

MP1：First P-type transistor

MP2：Second P-type transistor

MP3：3rd P-type transistor

MP4：4th P-type transistor

MPT：P-type triggers transistor

n1、n2：Node

OP’：Amplifier

OP：First amplifier

R：Control resistance

R1：First resistor

R1’：Feedback resistance

R2’、R2：Second resistance

R3：3rd resistor

R3’：Resistance

T1：Negative input end

T2：Positive input terminal

TC：Control electric capacity

V1：First voltage

V2：Second voltage

V3：Tertiary voltage

VDD：Positive power line

VSS：Negative power line

VF’、VF：Feedback voltage

VIN’、VIN：Input voltage

VR、VREF’、VREF：Reference voltage

VOUT’、VOUT：Output voltage

Specific embodiment

Various exemplary embodiments will be more fully described referring to alterations below, show in alterations Exemplary embodiments.However, concept of the present invention may embody in many different forms, and should not be construed as limited by institute herein The exemplary embodiments of elaboration.Specifically, there is provided this multiple exemplary embodiments causes that the present invention will be detailed and complete, and The category of concept of the present invention will be fully passed on to those skilled in the art.In all schemas, Ceng Ji areas can be lavished praise on oneself in order to clear Size and relative size.Similar numeral indicates similar component all the time.

Although it should be understood that may describe various elements using term first, second, third, etc. herein, this is multiple Element should not be limited by this multiple term.This multiple term is to distinguish an element with another element.Therefore, it is discussed herein below First element can be described as teaching of second element without departing from concept of the present invention.As used herein, term " and/or " include The associated all combinations for listing any one of project and one or more.

(embodiment of ESD protection circuit)

Fig. 2A is refer to, Fig. 2A is the block diagram of the ESD protection circuit according to the embodiment of the present invention.At this In embodiment, ESD protection circuit 200 includes control unit 210, trigger element 220 and strangulation unit 230.Strangulation unit 230 are coupled between positive power line VDD and negative power line VSS.Trigger element 220 has an input and an output end, triggering Unit 220 couples negative power line VSS and reference voltage VR, and the output end of trigger element 220 is coupled to strangulation unit 230, It is used to trigger strangulation unit 230.Control unit 210 is coupled to being somebody's turn to do for positive power line VDD, negative power line VSS and trigger element 220 Input.Control unit 210 receives transformation enable signal ENS and triggers the trigger element 220 according to control signal CS, And thereby determine being turned on and off for current discharge passage in strangulation unit 230.

In an embodiment, other circuit blocks (figures are coupled in the positive power line VDD of ESD protection circuit 200 2A is not illustrated), and other circuit blocks are in the case that output capacitance C produces an output voltage, when transformation enable signal ENS is During low voltage level (that is, other circuit blocks are closed in its working condition), control unit 210 can be according to the transformation for being received Enable signal ENS transmits control signal CS to trigger element 220.Then, trigger element 220 can be according to the control signal for being received CS opens the current discharge passage of strangulation unit 230 to discharge the output voltage on output capacitance C.On the other hand, transformation is worked as When enable signal ENS is high-voltage level (that is, in other circuit blocks normal works), control unit 210 can be according to being received Transformation enable signal ENS transmit control signal CS to trigger element 220.Then, trigger element 220 can be according to the control for being received Signal CS processed closes the current discharge passage of strangulation unit 230, to maintain the output voltage on output capacitance C.It is worth mentioning , in one embodiment, transformation enable signal ENS is equal to control signal CS.

(another embodiment of ESD protection circuit)

Fig. 2 B are refer to, Fig. 2 B are the block diagram of the ESD protection circuit according to the embodiment of the present invention.With it is upper State unlike Fig. 2A embodiments, control unit 210 includes control resistance R with control electric capacity TC.Trigger element 220 includes p-type Triggering transistor MPT and N-type triggering transistor MNT.Strangulation unit 230 includes N-type clamp transistor MNC.

One end of control resistance R is electrically connected with positive power line VDD, and the other end of control resistance R receives transformation enable signal ENS.One end of control electric capacity TC is electrically connected with the other end of control resistance R, and the other end of control electric capacity TC is electrically connected with negative electricity Source line VSS.The grid of p-type triggering transistor MPT is electrically connected with the other end of control resistance R, the source of p-type triggering transistor MPT Pole is electrically connected with reference voltage VR, is used to when current discharge passage is opened, and can discharge the electric charge on an output capacitance C It is complete.The electrical electricity of grid of N-type triggering transistor MNT connects the other end of control resistance R, the drain electrode electricity of N-type triggering transistor MNT Property connect the drain electrode of p-type triggering transistor MPT, the source electrode of N-type triggering transistor MNT is electrically connected with negative power line VSS.N-type The grid of clamp transistor MNC is electrically connected with the drain electrode of N-type triggering transistor MNT, and the drain electrode of N-type clamp transistor MNC is electrical An output capacitance C is connected, the source electrode of N-type clamp transistor MNC is electrically connected with negative power line VSS.

In the present embodiment, must first illustrate, due to p-type triggering transistor MPT and the grid of N-type triggering transistor MNT Pole is coupled to transformation enable signal ENS, so control signal CS is equal to transformation enable signal ENS.In ESD protection circuit 200 positive power line VDD is coupled to other circuit blocks (Fig. 2 B are not illustrated), and other circuit blocks are produced in output capacitance C In the case of one output voltage, when transformation enable signal ENS is low voltage level (that is, other circuit blocks close its work In state), the p-type triggering transistor MPT for constituting phase inverter can be according to the transformation enable for being received with N-type triggering transistor MNT Signal ENS opens the current discharge passage of N-type clamp transistor MNT to discharge the output voltage on output capacitance C.In other words Say, p-type triggering transistor MPT can be opened and N-type triggering transistor MNT can be closed, and then make the grid of N-type clamp transistor MNT Pole is coupled to reference voltage VREF and firing current discharge channel.

On the other hand, when transformation enable signal ENS is high-voltage level (that is, in other circuit blocks normal works), Constitute phase inverter p-type triggering transistor MPT and N-type triggering transistor MNT can according to the transformation enable signal ENS for being received come Close output voltage of the current discharge passage of N-type clamp transistor MNT to be maintained on output capacitance C.In other words, p-type Triggering transistor MPT can be closed and N-type triggering transistor MNT can be opened, and then couple the grid of N-type clamp transistor MNT The firing current discharge channel to negative power line.In one embodiment, negative power line VSS is coupled to ground voltage, not with this Embodiment is limited.

In order to illustrate in greater detail the operation workflow of bias circuit of the present invention 200, below will be for multiple embodiments At least one of do further description.

In ensuing multiple embodiments, the part different from above-mentioned Fig. 2A~2B embodiments will be described, and remaining is saved Slightly part is identical with the part of above-mentioned Fig. 2A~2B embodiments.Additionally, to illustrate conventionally, similar reference numeral or label Indicate similar element.

(embodiment of bias circuit)

Fig. 3 A are refer to, Fig. 3 A are the schematic diagram of the bias circuit according to the embodiment of the present invention.Bias circuit 300 includes electricity Voltage conversion circuit 310 and ESD protection circuit 320.ESD protection circuit 320 is electrically connected with voltage conversion circuit 310.As shown in Figure 3A, the input voltage VIN that voltage conversion circuit 310 is used to be received is converted to output voltage VOUT, wherein output voltage VO UT are stored on load capacitance CL.ESD protection circuit 320 is received and according to transformation enable Signal ENS is turned on and off state determine its internal current discharge passage.Bias circuit 300 can be band gap reference Circuit or other voltage boosting/lowering circuits.

In an embodiment of this disclosure, when transformation enable signal ENS is low voltage level (low voltage When level), bias circuit 300 is closed, ESD protection circuit 320 then can firing current discharge channel, and Discharge current can self-supported electric capacity CL flow into current discharge passage inside ESD protection circuit 320, by load capacitance Electric charge quick release on CL.In a preferred embodiment, the electric charge of load capacitance CL can completely be discharged.On the other hand, When transformation enable signal ENS is high-voltage level (high voltage level), bias circuit 300 is in normal work shape State, and voltage conversion circuit 310 can be enabled, and ESD protection circuit 320 can close current discharge passage, and then make electricity Voltage conversion circuit 310 exports charging current to load capacitance CL to produce stable output voltage VO UT.

In order to become apparent from illustrating this disclosure, bias circuit 300 will be further taught from three kinds of states below Specific action, wherein three kinds of state instruction bias circuits 200 (do not go up electricity) during being completed to be installed on circuit board from manufacture And bias circuit 200 is installed on the working condition and closed mode on circuit board.

Fig. 3 B are refer to, Fig. 3 B are the schematic diagram for not going up electrical bias circuit according to the embodiment of the present invention.Work as bias circuit 300 from manufacture be completed to be installed on circuit board during (that is, not going up electricity), " not going up electricity " is defined as not any defeated Enter voltage VIN, reference voltage VREF and transformation enable signal ENS.Due to may occur human contact's pin position (pin) or other because Cause that the output voltage VO UT of output end rises extremely, reaches ESD protection circuit in the case that element touches pin position During 320 trigger condition, then ESD protection circuit 320 can open a static discharge passage and cause to pass through electrostatic induced current IES Inflow is directly guided by static discharge passage (ground), to avoid damageeing the inner member of voltage conversion circuit 310 And reduce the function of integrated circuit.

On the other hand, refer to Fig. 3 C, Fig. 3 C is the bias plasma in normal operating conditions according to the embodiment of the present invention The schematic diagram on road.After bias circuit 300 is installed on circuit board, voltage conversion circuit 310 and the meeting of ESD protection circuit 320 Receive and normal operating conditions is according to a transformation enable signal ENS for high-voltage level.Then, voltage conversion circuit Input voltage VIN can be converted to output voltage VO UT and exported to next stage circuit block (Fig. 2 B are not illustrated) by 310.Namely Say, voltage conversion circuit 310 can export a charging current IC to load capacitance CL to store electric charge, substantially stable to export Output voltage VO UT used with providing next stage circuit block.It is worth noting that, at the same time, ESD protection circuit 320 can close current discharge passage according to transformation enable signal ENS, to ensure that charging current IC will not be via current discharge Passage and flow to ground, and then reach bias circuit 300 make a reservation for export output voltage VO UT.

Finally, refer to Fig. 3 D, Fig. 3 D is to switch to the temporary of closed mode from working condition according to the embodiment of the present invention The schematic diagram of state bias circuit.After bias circuit 300 is installed on circuit board, voltage conversion circuit 310 and electrostatic discharge (ESD) protection Circuit 320 can be received and switch to closing from normal operating conditions according to a transformation enable signal ENS for low voltage level State.Now, voltage conversion circuit 310 can be disabled and stop output charging current to load capacitance CL, and static discharge is protected Protection circuit 320 can portion produces a current discharge passage in the inner according to transformation enable signal ENS, and then can guide electric discharge electricity Stream ID flow to current discharge passage inside ESD protection circuit 320 with quick release load capacitance CL from load capacitance CL On electric charge.Therefore, when bias circuit 300 switches to closed mode from normal operating conditions, output voltage OUT can be quick Ground is dropped to close to no-voltage, the action without influencing whether next stage circuit.In another embodiment, output voltage OUT energy It is enough rapidly to drop to no-voltage, it is not limited with the present embodiment.

In order to illustrate in greater detail the operation workflow of bias circuit of the present invention 300, below will be for multiple embodiments At least one of do further description.

In ensuing multiple embodiments, the part different from above-mentioned Fig. 3 A~3D embodiments will be described, and remaining is saved Slightly part is identical with the part of above-mentioned Fig. 3 A~3D embodiments.Additionally, to illustrate conventionally, similar reference numeral or label Indicate similar element.

(another embodiment of bias circuit)

Fig. 4 is refer to, Fig. 4 is the physical circuit schematic diagram of the bias circuit according to another embodiment of the present invention.Such as Fig. 4 institutes Show, in the present embodiment, voltage conversion circuit is low dropout voltage regulator 410 (Low Dropout Regulator, LDO), is used to Input voltage VIN is depressured and the output voltage VO UT of stabilization is exported.In other embodiments, voltage conversion circuit can be with It is other reduction voltage circuits or booster circuit, is not limited with the present embodiment.For convenience of explanation, below explanation will be with low pressure Drop voltage-stablizer 410 makees an example to teach the overall start of bias circuit.Low dropout voltage regulator 410 include the first amplifier OP, First P-type transistor MP1, first resistor R1 and second resistance R2.ESD protection circuit 200 includes strangulation unit 230, touches Bill unit 220 and control unit 210.Control unit 210 includes 3rd resistor R3 and the first electric capacity C1.Trigger element 220 includes Second P-type transistor MP2 and the first N-type transistor MN1.Strangulation unit 230 includes the second N-type transistor MN2.

The negative input end T1 of the first amplifier OP receives the output end output first of reference voltage VREF, the second amplifier OP Voltage V1.The source electrode electric connection that the grid of the first P-type transistor MP1 receives first voltage V1, the first P-type transistor MP1 is defeated The drain electrode for entering voltage VIN, the first P-type transistor MP1 exports an output voltage VO UT.One end of first resistor R1 is electrically connected with the The drain electrode of one P-type transistor MP1, the other end of first resistor R1 exports a feedback voltage V F and feedback voltage V F is sent into the The positive input terminal T2 of one amplifier OP.One end of second resistance R2 is electrically connected with the other end of first resistor R1, second resistance R2 The other end be electrically connected with ground voltage GND.One end of 3rd resistor R3 is electrically connected with the drain electrode of the first P-type transistor MP1, the The other end of three resistance R3 receives transformation enable signal ENS.One end of first electric capacity C1 is electrically connected with the another of 3rd resistor R3 End, the other end of the first electric capacity C1 is electrically connected with ground voltage GND.The grid of the second P-type transistor MP2 is electrically connected with the 3rd electricity The other end of R3 is hindered, the source electrode of the second P-type transistor MP2 is electrically connected with the second voltage V2 of stabilization.First N-type transistor MN1 Grid be electrically connected with the other end of 3rd resistor R3, the drain electrode of the first N-type transistor MN1 is electrically connected with the second P-type transistor The drain electrode of MP2, the source electrode of the first N-type transistor MN1 is electrically connected with ground voltage GND.The grid electricity of the second N-type transistor MN2 Property connection the first N-type transistor MN1 drain electrode, the drain electrode of the second N-type transistor MN2 is electrically connected with output voltage VO UT, the 2nd N The source electrode of transistor npn npn MN2 is electrically connected with ground voltage GND.

It is described below, is the specific start on bias circuit 400 in Fig. 4 embodiments.

Fig. 4 is continued referring to, after bias circuit 400 is installed on circuit board, low dropout voltage regulator 410 is protected with static discharge Protection circuit 200 can be received and be in normal operating conditions according to a transformation enable signal ENS for high-voltage level.First P The source electrode of transistor npn npn MP1 couples input voltage VIN to receive input voltage VIN, and the size of output voltage VO UT can be by joining The value of voltage VREF, first resistor R1 and second resistance R2 is examined to determine.Furthermore, it is understood that due to the configuration of the first amplifier OP It is imaginary short relation, so feedback voltage V F can substantially be equal to reference voltage VREF, therefore designer can set according to circuit Meter demand or practical application request design the size of predetermined output voltage VO UT according to equation (1).

VOUT=[(R1+R2)/R2] x VREF equations (1)

When feedback voltage V F is more than reference voltage VREF, then the first voltage V1 that the first amplifier OP is exported can go up Rise, and the grid source electrode cross-pressure of the first P-type transistor MP1 can be declined, and then cause to flow through first resistor R1 and second resistance The electric current I1 of R2 declines.Therefore, according to the relation of current resistor voltage drop (IR drop), output voltage VO UT can decline, and then Feedback voltage V F is caused to be decreased until that feedback voltage V F is less than reference voltage VREF.When feedback voltage V F is less than reference voltage VREF When, then the first voltage V1 that the first amplifier OP is exported can decline, and cause the grid source electrode cross-pressure of the first P-type transistor MP1 Can rise, and then cause the electric current I1 for flowing through first resistor R1 and second resistance R2 to rise.Therefore, according to current resistor voltage drop The relation of (IR drop), output voltage VO UT can rise, and then cause feedback voltage V F to rise until feedback voltage V F is less than ginseng Examine voltage VREF.According to above-mentioned negative-feedback (negative feedback) mechanism, low dropout voltage regulator 410 can be provided surely Fixed output voltage VO UT, and designer can be according further to reference voltage VREF, first resistor R1 and second resistance R2 Value determines the size of output voltage VO UT.

Now, the transformation enable letter of high-voltage level is received due to the node n1 in ESD protection circuit 200 Number ENS, so while the phase inverter (inverter) that is constituted of the second P-type transistor M2 and the first N-type transistor MN1 is also simultaneously Receive the transformation enable signal ENS of high-voltage level.Therefore, the second P-type transistor MP2 can be closed, and the first N-type Transistor MN1 can be in opening, and then the signal that phase inverter exports a low voltage level is sent to the second N-type transistor MN2.That is, the grid of the second N-type transistor MN2 can receive or be electrically connected to ground voltage GND, and cause the 2nd N Transistor npn npn MN2 is closed.What deserves to be explained is, in the present embodiment, the second N-type transistor MN2 is put as electrostatic Current discharge passage in electric protection circuit 200, therefore, if the second N-type transistor MN2 is closed, electrostatic is put Current discharge passage in electric protection circuit 220 is also in closed mode.Therefore, when the output of low dropout voltage regulator 410 one is filled When electric current IC to load capacitance CL is to provide output voltage VO UT to next stage circuit block (Fig. 3 is not illustrated), charging current IC can't flow through current discharge passage and produce the phenomenon of leakage current (leakage current).

On the other hand, when low dropout voltage regulator 410 and ESD protection circuit 200 can receive a low voltage level During transformation enable signal ENS, low dropout voltage regulator 410 can be disabled and switch to closed mode from normal operating conditions.Electrostatic Node n1 in discharge protection circuit 200 after the transformation enable signal ENS for receiving low voltage level, in causing phase inverter The second P-type transistor MP2 be in opening, the first N-type transistor MN1 is closed.Then, phase inverter can be exported The grid of the N-type transistors of second voltage V2 to second MN2 opens electrostatic discharge (ESD) protection to open the second N-type transistor MN2 Current discharge passage in circuit 200.Then, discharge current ID can self-supported electric capacity CL flow to through current discharge passage ground, That is, the electric charge on load capacitance CL can be from inside ESD protection circuit 200 current discharge passage repid discharge, So that output voltage VO UT rapid decreases, and avoid having influence on the action of other circuits.In one embodiment, can more be increased The integral passage width of two N-type transistor MN2 to reduce electric conduction group, and then to improve discharging efficiency.

It is noted that in the present embodiment, because the grid of the second N-type transistor MN2 is electrically connected to stabilization Second voltage V2, so in the transient process of circuit discharging, output voltage VO UT can constantly decline, but the second N-type crystal The grid voltage of pipe MN2 still can keep the second voltage V2 of stabilization.That is, the grid source electrode of the second N-type transistor MN2 across Pressure remains able to the second voltage V2 of stabilization.Therefore, the source electrode coupling compared to the second P-type transistor MP2 of the prior art To output voltage VO UT, this disclosure helps to finish the electric charge quick release on load capacitance CL, and can be effectively Lift the speed of electric discharge.Subsidiary one is mentioned that, second voltage V2 can be the voltage of system voltage or other stabilizations.

In order to better understand this disclosure, referring to Fig. 5 A and Fig. 5 B.Fig. 5 A are putting for existing bias circuit The voltage time oscillogram of electrical waveform.Fig. 5 B are the voltage time oscillogram of the discharge waveform of the bias circuit of corresponding diagram 3D.By Fig. 5 A and Fig. 5 B understand, the voltage of load capacitance is discharged to 10% by existing bias circuit by 90% about needs 500 microseconds, but The voltage of load capacitance CL is discharged to 10% and about only needs to 2 microseconds by the bias circuit 400 of this disclosure by 90%.Therefore phase Compared with prior art, this disclosure can be greatly reduced discharge time, and need not be extra layout area.

Additionally, refer to Fig. 5, Fig. 5 is the specific schematic diagram for not going up electrical bias circuit according to another embodiment of the present invention. ESD protection circuit 200 further includes the first diode D1.The anode of the first diode D1 is electrically connected with output voltage VO UT, The negative electrode of the first diode D1 is electrically connected with the source electrode of the second P-type transistor MP2.In the present embodiment, the first diode D1 is used (bombarded when electrostatic is subjected to the voltage level that the source electrode of the second P-type transistor MP2 is determined before bias circuit 500 does not go up electricity When).

During bias circuit 600 is completed to be installed on circuit board from manufacture (that is, not going up electricity), " not going up electricity " is fixed Justice is not any input voltage VIN, reference voltage VREF and transformation enable signal ENS, is connect due to human body may occur Contact pin position (pin) or other factors touch the situation of pin position (pin) and cause in the output voltage VO UT exceptions of output end Rise, when the trigger condition of ESD protection circuit 200 is reached, then ESD protection circuit 200 can open an electrostatic and put Electric channel cause by electrostatic induced current IES via static discharge passage directly guide inflow (ground), to avoid damageeing The inner member of low dropout voltage regulator 410 and reduce the function of integrated circuit.Therefore, when the pin position of IC chip or output When end is subjected to electrostatic bombardment and causes that output voltage VO UT rises extremely, the second P-type transistor is gone out in order to expliciting the position The voltage level of the source electrode of MP2, the present embodiment utilizes the voltage-current characteristic of the first diode D1, by the second P-type transistor The voltage level of the source electrode of MP2 orientates the forward conducting voltage that output voltage VO UT subtracts the first diode D1 as, with bias Circuit 600 is subjected to electrostatic bombardment and in the discharge process after firing current discharge channel, can determine and maintain current discharge to lead to The unlatching in road, helps to be directed to ground by electrostatic induced current IES.

Specifically, because in human-body model, the rise time of its discharge waveform is about in 10 nanoseconds, and integrated electricity The voltage waveform rise time on road about in millisecond grade, so the capacity resistance cime constant of 3rd resistor R3 and the first electric capacity C1 (RC constant) is typically designed to the time between millisecond~nanosecond.Therefore, when bias circuit 500 is subjected to electrostatic to be bombarded, Output voltage VO UT abnormal can rise, and now, the source voltage of the second P-type transistor MP2 subtracts first for output voltage VO UT The conducting voltage of diode D1.In this transient process, because the voltage of node n1 is typically mostly in the case of this suspension joint The level of low voltage, so the second P-type transistor MP2 can be opened, and the first N-type transistor MN1 can be closed, and cause second The grid voltage of N-type transistor MN2 is substantially equal to the source voltage of the second P-type transistor MP2.That is, the second N-type is brilliant The grid voltage of body pipe MN2 is the conducting voltage that output voltage VO UT subtracts the first diode D1, to ensure the second N-type transistor The unlatching of MN2 or current discharge passage, and then electrostatic induced current IES is flow to ground via the second N-type transistor MN2.

In order to illustrate in greater detail the operation workflow of bias circuit of the present invention, below will lift multiple embodiments in extremely It is one of few to do further description.

In ensuing multiple embodiments, the part different from above-mentioned Fig. 2~6 embodiment will be described, and remaining is omitted Part is identical with the part of above-mentioned Fig. 2~6 embodiment.Additionally, to illustrate conventionally, similar reference numeral or label are indicated Similar element.

(another embodiment of bias circuit)

Fig. 7 is refer to, Fig. 7 is the physical circuit figure of the bias circuit according to yet another embodiment of the invention.With above-mentioned Fig. 4 realities Apply unlike example, the 3rd resistor R3 in ESD protection circuit 200 is with the 3rd P-type transistor in the present embodiment MP3 replaces, improving the allomeric function of bias circuit 700.Furthermore, it is understood that in the present embodiment, electrostatic discharge (ESD) protection electricity Road 200 includes the 3rd P-type transistor MP3, the second electric capacity C2, the 4th P-type transistor MP4, the 3rd N-type transistor MN3 and the 4th N Transistor npn npn MN4.

The grid of the 3rd P-type transistor MP3 receives transformation enable signal ENS, and the source electrode of the 3rd P-type transistor MP3 is electrical Connection output voltage VO UT.One end of second electric capacity C2 is electrically connected with the drain electrode of the 3rd P-type transistor MP3, the second electric capacity C2's The other end is electrically connected with ground voltage GND.The grid of the 4th P-type transistor MP4 is electrically connected with the leakage of the 3rd P-type transistor MP3 Pole, the source electrode of the 4th P-type transistor MP4 is electrically connected with the tertiary voltage V3 of stabilization.The grid of the 3rd N-type transistor MN3 is electrical The drain electrode of the 3rd P-type transistor MP3 is connected, the drain electrode of the 3rd N-type transistor MN3 is electrically connected with the leakage of the 4th P-type transistor MP4 Pole, the source electrode of the 3rd N-type transistor MN3 is electrically connected with ground voltage GND.The grid of the 4th N-type transistor MN4 is electrically connected with the The drain electrode of three N-type transistor MN3, the drain electrode of the 4th N-type transistor MN4 is electrically connected with output voltage VO UT, the 4th N-type transistor The source electrode of MN4 is electrically connected with ground voltage GND.

It is described below, is the specific start on bias circuit 700 in Fig. 7 embodiments.

Fig. 7 is continued referring to, after bias circuit 700 is installed on circuit board, low dropout voltage regulator 410 is protected with static discharge Protection circuit 200 can be received and be in normal operating conditions according to a transformation enable signal ENS for high-voltage level.First P The source electrode of transistor npn npn MP1 couples input voltage VIN to receive input voltage VIN, and the size of output voltage OUT can be by referring to The value of voltage VREF, first resistor R1 and second resistance R2 is determined.Because the configuration of the first amplifier OP is imaginary short relation, So feedback voltage V F can substantially be equal to reference voltage VREF, therefore designer can answer according to circuit design demand or reality The size of predetermined output voltage VO UT is designed according to equation (1) with demand.

Now, the transformation enable letter of high-voltage level is received due to the node n2 in ESD protection circuit 200 Number ENS, so the 3rd P-type transistor MP3 can be closed, so electric charge will not be via the 3rd p-type on the second electric capacity C2 Transistor MP3 leaks electricity and has influence on the voltage level of node n2, and then has influence on follow-up circuit operation.Then, due to the 4th P The phase inverter (inverter) that transistor npn npn MP4 and the 3rd N-type transistor MN3 are constituted also receives the change of high-voltage level simultaneously Pressure enable signal ENS.Therefore, the 4th P-type transistor MP4 can be closed, and the 3rd N-type transistor MN3 can be in and hold State is opened, and then the signal that phase inverter exports a low voltage level is sent to the 4th N-type transistor MN4.That is, the 4th The grid of N-type transistor MN4 can receive or be electrically connected to ground voltage GND, and cause that the 4th N-type transistor MN4 is in and close Closed state.What deserves to be explained is, in the present embodiment, the 4th N-type transistor MN4 is used as the electric current in ESD protection circuit Discharge channel, therefore, if the 4th N-type transistor MN4 is closed, the electric current in ESD protection circuit 200 Discharge channel is also in closed mode.Therefore, when low dropout voltage regulator 410 export a charging current IC to load capacitance CL with When providing output voltage VO UT to next stage circuit block (Fig. 6 is not illustrated), charging current IC can't flow through current discharge and lead to Road and produce the phenomenon of leakage current (leakage current).

On the other hand, when low dropout voltage regulator 410 and ESD protection circuit 200 can receive a low voltage level During transformation enable signal ENS, low dropout voltage regulator 410 can be disabled and switch to closed mode from normal operating conditions.Electrostatic Node n2 in discharge protection circuit 200, can be brilliant by the 3rd p-type after the transformation enable signal ENS for receiving low voltage level Body pipe MP3 is opened, and the 4th P-type transistor MP4 in phase inverter is in opening, the 3rd N-type transistor MN3 meetings It is closed.Then, phase inverter can export the grid of the N-type transistor MN4 of tertiary voltage V3 to the 4th to open the 4th N-type Transistor MN4, and then open the current discharge passage in ESD protection circuit 200.Then, discharge current ID can be self-supported Electric capacity CL flow to ground through current discharge passage, that is to say, that the electric charge on load capacitance CL can be from ESD protection circuit Current discharge passage repid discharge inside 200, so that output voltage VO UT rapid decreases, and avoid having influence on other circuits Action.In one embodiment, the integral passage width of the 4th N-type transistor MN4 can more be increased to reduce conducting resistance, and then To improve discharging efficiency.

It is noted that in the present embodiment, because the grid of the 4th N-type transistor MN4 electrically connects respectively with drain electrode The tertiary voltage V3 and output voltage VO UT of stabilization are connected to, so, in the transient process of circuit discharging, output voltage VO UT meetings Constantly decline, but the grid voltage of the 4th N-type transistor MN4 still can keep stable tertiary voltage V3.That is, the The grid source electrode cross-pressure of four N-type transistor MN4 remains able to the tertiary voltage V3 of stabilization.Therefore, compared to of the prior art The source electrode of four P-type transistor MP4 is coupled to output voltage VO UT, and this disclosure contributes to the electric charge on load capacitance CL is fast Quick-release discharges complete, and can effectively lift the speed of electric discharge.Subsidiary one is mentioned that, tertiary voltage V3 can be system voltage or It is the voltage of other stabilizations.

Additionally, refer to Fig. 8, Fig. 8 is the specific schematic diagram for not going up electrical bias circuit according to yet another embodiment of the invention. ESD protection circuit 200 further includes the second diode D2.The anode of the second diode D2 is electrically connected with output voltage VO UT, The negative electrode of the second diode D2 is electrically connected with the source electrode of the 4th P-type transistor MP4.In the present embodiment, the second diode D2 is used (bombarded when electrostatic is subjected to the voltage level that the source electrode of the 4th P-type transistor MP4 is determined before bias circuit 800 does not go up electricity When).

During bias circuit 800 is completed to be installed on circuit board from manufacture (that is, not going up electricity), " not going up electricity " is fixed Justice is not any input voltage VIN, reference voltage VREF and transformation enable signal ENS, is connect due to human body may occur Contact pin position (pin) or other factors touch the situation of pin position (pin) and cause in the output voltage VO UT exceptions of output end Rise, when the trigger condition of ESD protection circuit 200 is reached, then ESD protection circuit 200 can open an electrostatic and put Electric channel cause by electrostatic induced current IES via static discharge passage directly guide inflow (ground), to avoid damageeing The inner member of low dropout voltage regulator 410 and reduce the function of integrated circuit.Therefore, when the pin position of IC chip or output When end is subjected to electrostatic bombardment and causes that output voltage VO UT rises extremely, the 4th P-type transistor is gone out in order to expliciting the position The voltage level of the source electrode of MP4, the present embodiment utilizes the voltage-current characteristic of the second diode D2, by the 4th P-type transistor The voltage level of the source electrode of MP4 orientates the forward conducting voltage that output voltage VO UT subtracts the second diode D2 as, with bias Circuit 800 is subjected to electrostatic bombardment and in the discharge process after firing current discharge channel, can determine and maintain current discharge to lead to The unlatching in road, helps to be directed to ground by electrostatic induced current IES.

Specifically, because in human-body model, the rise time of its discharge waveform is about in 10 nanoseconds, and integrated electricity The voltage waveform rise time on road is about in millisecond grade, so the equivalent electric group of the 3rd P-type transistor MP3 is with the first electric capacity C1's Capacity resistance cime constant (RC constant) is typically designed to the time between millisecond~nanosecond, wherein the 3rd P-type transistor The equivalent resistance of MP3 can in technique geometry or material parameter determine.Therefore, when bias circuit 800 is subjected to electrostatic During bombardment, output voltage VO UT abnormal can rise, and now, the source voltage of the 4th P-type transistor MP4 subtracts for output voltage VO UT Go the conducting voltage of the second diode D2.In this transient process, because the voltage of node n2 is general in the case of this suspension joint All it is the level of low voltage, so the 4th P-type transistor MP4 can be opened, and the 3rd N-type transistor MN3 can be closed, and be caused The grid voltage of the 4th N-type transistor MN4 is substantially equal to the source voltage of the 4th P-type transistor MP4.That is, the 2nd N The grid voltage of transistor npn npn MN2 is the conducting voltage that output voltage VO UT subtracts the second diode D2, to ensure that the 4th N-type is brilliant The unlatching of body pipe MN4 or current discharge passage, and then electrostatic induced current IES is flow to ground via the 4th N-type transistor MN4.

(embodiment of electronic installation)

Fig. 9 is refer to, Fig. 9 is the schematic diagram of the electronic installation of the embodiment of the present invention.Electronic installation 900 includes load 920 With the bias circuit 910 of electric property coupling load 920, the wherein reception of bias circuit 910 input voltage VIN.Bias circuit 910 can be with It is one of bias circuit 300,400,600,700 and 800 in above-described embodiment, and is used to provide the output electricity of stabilization Pressure VOUT is to load 920.Electronic installation 900 can be various types of electronic installations, for example display device, hand-held device or row Dynamic device etc..

(possibility effect of embodiment)

In sum, the embodiment of the present invention proposes bias circuit and electronic installation, when transformation enable signal is low-voltage During level, bias circuit is closed from normal operating conditions, and ESD protection circuit can be forced firing current discharge channel, make Obtaining discharge current being capable of self-supported electric capacity inflow current discharge channel.Accordingly, this disclosure need not only increase extra Layout area is just capable of the discharge time of efficient reduction load capacitance, the cost of integrated circuit is declined and is improved quiet The ability of discharge of electricity protection circuit.

Embodiments of the invention are the foregoing is only, it simultaneously is not used to limit to scope of the patent claims of the invention.

Claims

1. a kind of ESD protection circuit, it is characterised in that the ESD protection circuit includes：

Strangulation unit, between coupling positive power line and negative power line；

Trigger element, with input and output end, the trigger element couples the negative power line and reference voltage, and the output End is coupled to the strangulation unit and is used to trigger the strangulation unit；And

Control unit, is coupled to the input of the positive power line, the negative power line and the trigger element, and the control unit is received Transformation enable signal thereby determines that the current discharge passage of the strangulation unit is turned on and off to trigger the trigger element,

Wherein when the transformation enable signal is low voltage level, the trigger element can open the current discharge of the strangulation unit Passage.

2. ESD protection circuit as claimed in claim 1, it is characterised in that the control unit includes：

Control resistance, its one end is electrically connected with the positive power line, and its other end receives the transformation enable signal；And

Control electric capacity, its one end is electrically connected with the other end of the control resistance, and its other end is electrically connected with the negative power line.

3. ESD protection circuit as claimed in claim 1, it is characterised in that the trigger element includes：

P-type triggers transistor, and its grid is electrically connected with the other end of the control resistance, and its source electrode is electrically connected with the reference voltage, It is used to, when the current discharge passage is opened, the electric charge in load capacitance can be released；And

N-type triggers transistor, and the electrical electricity of its grid connects the other end of the control resistance, and it is brilliant that its drain electrode is electrically connected with p-type triggering The drain electrode of body pipe, its source electrode is electrically connected with the negative power line.

4. ESD protection circuit as claimed in claim 3, it is characterised in that the strangulation unit includes：

N-type clamp transistor, its grid is electrically connected with the drain electrode that the N-type triggers transistor, and its drain electrode is electrically connected with output capacitance, Its source electrode is electrically connected with the negative power line,

Wherein p-type triggering transistor AND gate N-type triggering transistor constitutes phase inverter, when the transformation enable signal is high voltage electricity Usually, then p-type triggering transistor is closed and N-type triggering transistor is opened, and the reception of the grid of the N-type clamp transistor should The voltage of negative power line, to close the current discharge passage, when the transformation enable signal is low voltage level, then the p-type is touched Hair transistor is opened and N-type triggering transistor is closed, and the grid of the N-type clamp transistor receives the reference voltage, to open Open the current discharge passage.

5. ESD protection circuit as claimed in claim 4, it is characterised in that the ESD protection circuit is further included：

Catching diode, its anode is electrically connected with the positive power line, and its negative electrode is electrically connected with the source electrode that the p-type triggers transistor, The catching diode is used to the voltage level of the source electrode for determining p-type triggering transistor.

6. ESD protection circuit as claimed in claim 1, it is characterised in that the negative power line couples ground voltage.

7. a kind of bias circuit, it is characterised in that the bias circuit includes：

Voltage conversion circuit, the input voltage for being used to be received is converted to output voltage, wherein output voltage storage In load capacitance；

ESD protection circuit, is electrically connected to the output voltage, and the ESD protection circuit is received and caused according to transformation Can signal determine being turned on and off for its internal current discharge passage,

Wherein, when the transformation enable signal is low voltage level, the bias circuit is closed, and the static discharge is protected Protection circuit opens the current discharge passage, and discharge current flows into the current discharge passage from the load capacitance, and this is loaded Electric charge release on electric capacity.

8. bias circuit as claimed in claim 7, it is characterised in that when the transformation enable signal is high-voltage level, this is inclined Volt circuit is in normal operating conditions, and the voltage conversion circuit is enabled, and the ESD protection circuit closes the electric current Discharge channel, the voltage conversion circuit exports charging current to the load capacitance to produce the output voltage.

9. bias circuit as claimed in claim 8, it is characterised in that the voltage conversion circuit is low dropout voltage regulator, is used to The input voltage is depressured and is stablized the output voltage.

10. bias circuit as claimed in claim 9, it is characterised in that the low dropout voltage regulator includes：

First amplifier, its negative input end receives reference voltage, its output end output first voltage；

First P-type transistor, its grid receives the first voltage, and its source electrode is electrically connected with input voltage, and it is defeated that its drain electrode exports this Go out voltage；

First resistor, its one end is electrically connected with the drain electrode of first P-type transistor, its other end output feedback voltage and this is anti- Feedthrough voltage is sent to the positive input terminal of first amplifier；And

Second resistance, its one end is electrically connected with the other end of the first resistor, and its other end is electrically connected with ground voltage,

Wherein when the feedback voltage be more than the reference voltage when, then the first voltage rise and flow through this first with the second resistance Electric current decline, and then reduce the output voltage, when the feedback voltage is less than the reference voltage, then the first voltage decline and Flow through this first to rise with the electric current of the second resistance, and then increase the output voltage.

11. bias circuits as claimed in claim 10, the wherein ESD protection circuit include strangulation unit, trigger element With control unit, it is characterised in that the control unit includes：

3rd resistor, its one end is electrically connected with the drain electrode of first P-type transistor, and its other end receives the transformation enable signal； And

First electric capacity, its one end is electrically connected with the other end of the 3rd resistor, and its other end is electrically connected with the ground voltage；

Wherein the trigger element includes：

Second P-type transistor, its grid is electrically connected with the other end of the 3rd resistor, and its source electrode is electrically connected with the second electricity of stabilization Pressure, is used to, when the current discharge passage is opened, to release the electric charge in the load capacitance；And

First N-type transistor, the electrical electricity of its grid connects the other end of the 3rd resistor, and it is brilliant that its drain electrode is electrically connected with second p-type The drain electrode of body pipe, its source electrode is electrically connected with the ground voltage；

Wherein the strangulation unit includes：

Second N-type transistor, its grid is electrically connected with the drain electrode of first N-type transistor, and its drain electrode is electrically connected with output electricity Pressure, its source electrode is electrically connected with the ground voltage,

Wherein second P-type transistor constitutes phase inverter with first N-type transistor, when the transformation enable signal is high voltage electricity Usually, then second P-type transistor is closed and first N-type transistor is opened, and the grid of second N-type transistor is received and is somebody's turn to do Ground voltage, to close the current discharge passage, when the transformation enable signal is low voltage level, then second P-type crystal Pipe is opened and first N-type transistor is closed, and the grid of second N-type transistor receives the second voltage, to open the electricity Banish electric channel.

12. bias circuits as claimed in claim 11, it is characterised in that the ESD protection circuit is further included：

First diode, its anode is electrically connected with the output voltage, and its negative electrode is electrically connected with the source electrode of second P-type transistor, First diode is used to the voltage level of the source electrode for determining second P-type transistor.

13. bias circuits as claimed in claim 12, it is characterised in that caused when the bias circuit is bombarded by electrostatic The output voltage rises extremely, then the voltage of the source electrode of second P-type transistor subtracts first diode for the output voltage Conducting voltage, in discharge process maintain current discharge passage unlatching.

14. bias circuits as claimed in claim 10, it is characterised in that the ESD protection circuit includes：

3rd P-type transistor, its grid receives the transformation enable signal, and its source electrode is electrically connected with the output voltage；

Second electric capacity, its one end is electrically connected with the drain electrode of the 3rd P-type transistor, and its other end is electrically connected with the ground voltage；

4th P-type transistor, its grid is electrically connected with the drain electrode of the 3rd P-type transistor, and its source electrode is electrically connected with the of stabilization Three voltages, are used to, when the current discharge passage is opened, to release the electric charge in the load capacitance；

3rd N-type transistor, the electrical electricity of its grid connects the drain electrode of the 3rd P-type transistor, and its drain electrode is electrically connected with the 4th p-type The drain electrode of transistor, its source electrode is electrically connected with the ground voltage；And

4th N-type transistor, its grid is electrically connected with the drain electrode of the 3rd N-type transistor, and its drain electrode is electrically connected with output electricity Pressure, its source electrode is electrically connected with the ground voltage,

Wherein the 4th P-type transistor constitutes phase inverter with the 3rd N-type transistor, when the transformation enable signal is high voltage electricity Usually, then the 3rd closed with the 4th P-type transistor and the unlatching of the 3rd N-type transistor, and the grid of the 4th N-type transistor Pole receives the ground voltage, to close the current discharge passage, when the transformation enable signal is low voltage level, then and the 3rd Opened with the 4th P-type transistor and the 3rd N-type transistor is closed, and the grid of the 4th N-type transistor receives the 3rd Voltage, to open the current discharge passage.

15. bias circuits as claimed in claim 14, it is characterised in that the ESD protection circuit is further included：

Second diode, its anode is electrically connected with the output voltage, and its negative electrode is electrically connected with the source electrode of the 4th P-type transistor, Second diode is used to the voltage level of the source electrode for determining the 4th P-type transistor.

16. bias circuits as claimed in claim 15, it is characterised in that caused when the bias circuit is bombarded by electrostatic The output voltage rises extremely, then the voltage of the source electrode of the 4th P-type transistor subtracts second diode for the output voltage Conducting voltage, in discharge process maintain current discharge passage unlatching.

17. a kind of electronic installations, it is characterised in that the electronic installation includes：

Bias circuit as claimed in claim 7；And

Load, receives the output voltage.