200849540 九、發明說明： 【發明所屬之技術領域】 本發明係提供一種電路佈局方法與相關電路，尤指一 種能依據既有兩相鄰輸入/輸出電路單元之間及/或一輸入/ 輸出電路單元與一角落單元之間的空間來置入靜電放電防 護電路單元的靜電放電防護設計方法與相關電路。 【先前技術】 隨著互補式金氧半導體（Complementary Metal-Oxide Semiconductor, CMOS)製程技術發展至深次微米、奈米階段，積 體電路效能也因此不斷的提升，因此如今已有許多積體電路以 CMOS導入量產。更先進製程技術，即積體電路中元件尺寸縮小、 更薄閘極氧化層（Gate-Oxide)、更淺汲極/源極（Drain/Source) 深度以及金屬矽化物（Silicide)等，能有效提高密集度與改善元 件特性。然而這些先進製程技術，卻嚴重降低積體電路對靜電放 電（Electro-static discharge，ESD)的耐受度，使得靜電放電更容易 成為量產積體電路中的良率瓶頸所在。 請參考第1圖，第1圖為習知晶片1〇〇的電路佈局示 意圖。晶片100包含複數個輸入/輸出電路單元（I/〇celi)ii〇 , 用來接收輸人職或是送出輪出訊號；分別位於兩相鄰輸入 • /輸出電路單元110間之複數個繞線區域120 (虛線所標示之區 ,域）；以及複數個角落單元（贿ercelI) 130。一般而言，每一輸 6 200849540 3出電路單元110在晶片謂上會連接至—連接墊（pad)，而 =t線的用S主要是作為每—輪入/輸出電路單元 之電源繞線/接地繞線之間的連接，亦 用來設置電源繞線及/或接地繞線以建立11線區域120僅 叮！的電氣連接路徑。 複數個輸入/輸出電路單元n〇能 其他電路/晶片連接，以實現出季统=片100得以和外界 而木日u 貫現出糸統層級的整體功能，缺 而，虽曰日片1〇〇在進行封裝、測試、運 Μ 這些輸入/輸出電路單元110也很容易與外女裝時’ 將靜電所引發的不當電力傳導至晶片|接觸’ 日日片内部電路的損毀；這也就是所謂的靜電放電（ε=,200849540 IX. Description of the Invention: [Technical Field] The present invention provides a circuit layout method and related circuit, and more particularly to an existing two adjacent input/output circuit units and/or an input/output circuit. The space between the unit and the corner unit is placed in the electrostatic discharge protection design method and related circuit of the electrostatic discharge protection circuit unit. [Prior Art] With the development of Complementary Metal-Oxide Semiconductor (CMOS) process technology to the deep micron and nano phase, the performance of integrated circuits has been continuously improved, so many integrated circuits are available today. Mass production in CMOS. More advanced process technology, ie, component size reduction in integrated circuits, thinner gate oxide layer (Gate-Oxide), shallower drain/source depth (Drain/Source) depth, and metal silicide, etc. Increase density and improve component characteristics. However, these advanced process technologies have severely reduced the tolerance of the integrated circuit to Electro-static discharge (ESD), making electrostatic discharge more likely to be the yield bottleneck in mass production circuits. Please refer to Fig. 1. Fig. 1 is a schematic diagram showing the circuit layout of a conventional wafer. The chip 100 includes a plurality of input/output circuit units (I/〇celi) ii〇 for receiving input or output of a turn-out signal; and a plurality of windings between two adjacent input/output circuit units 110, respectively. Area 120 (the area indicated by the dotted line, the domain); and a plurality of corner units (bribe ercelI) 130. In general, each input 6 200849540 3 out circuit unit 110 will be connected to the pad on the wafer, and the S line of the =t line is mainly used as the power supply winding for each wheel input/output circuit unit. / The connection between the grounding windings is also used to set the power supply winding and / or grounding winding to establish the 11 line area 120 only! Electrical connection path. A plurality of input/output circuit units can be connected to other circuits/chips to realize the overall function of the seasons=slices 100 and the outside world, and the overall function of the system level is lacking, although the Japanese film 1〇封装Packaging, testing, and operation These I/O circuit units 110 are also very easy to transmit to the outside of the women's clothing. The improper power generated by static electricity is transmitted to the wafer|contact's internal circuit damage; this is also called Electrostatic discharge (ε=,
Electro-Static Discharge)事件。因此，— 單元11。中都會有一靜電放電防護電路靜:出:: 防護電路可在兩輸人猶電路單元u 4電放電 電流路抨，佶尸盔木亡赵+ ^通一個低阻抗的 電路^吏仔母當有靜電荷發生在其中一輸入/輪出 兀 ¥，靜電放電產生的電流能優先從此電、士 而不會流入至晶片刚的其他内部 :僅流出’ =:片：:中的其他内部電路不受靜電放電影響。 將輸入/輪出電路單元觀-败I 放電防護電路就是 ★ 卿電路早兀购構而導引料放電利 抓，以便旁通(bypass)靜電放電的電流，使其 古 片1〇〇中的其他内部電路。不過，當j、"IL入至晶 時，靜電放電電路就要中止其在兩輸Λ/輪出電路單 == 7 200849540 建立的電流路徑，以免妨礙晶片100的正常功能。 一般而言，在電路設計上常常增加許多靜電放電防護電 路以提升靜電放電防護的效果，然而，增加靜電放電防護電路 同日守也會佔用較大的佈局面積，也造成晶片生產成本增加， 因此，如何選用適合的靜電放電防蹲電路以及適當的佈 局’乃是一個電路佈局設計上的重要課題。 【發明内容】 因此本發明的目的在於提供一種能依據既有輸入/輪出電路單 元佈局之間的空間來置入靜電放電防護電路單元的靜電放電防護 設計方法與相關電路。 依據本發明之實施例，其揭露一種靜電放電防護設計方法。 該方法包含有：將一第一輸入/輸出電路單元與一第二輸入/輸出電 路單元佈局於-晶片之—側邊，其中該第—、第二輸人/輸出電路 早7L之間具有-繞龜域位於該側邊；提供—靜電放電防護電路 單元；以及佈局該靜電放電防魏路單元魏齡區域中。 依據本發明之實施例，直_ J具另揭路一種具有靜電放電防護功能 之晶片。該晶片包含有：一第一於 ^ 弟輸入/輸出電路單元，位於該晶片 之一側邊，一苐—輸入/輸出電路軍$ ^ 屯峪早70，位於該晶片之該侧邊，其 凡之間具有一繞線區域位於該側 中3亥弟一、弟一輸入/輸出電路單 200849540 邊·，以及-靜電放電防魏路單元，位於該繞線區域中。 依據本發明之實施例，其另揭露一種靜電放電防護設計方 法。該方法包含有：將-輪人/輪出單元與—肖落單元佈局於 -晶片之-側邊’其巾該輪人/輪出電路單元與該肖落單元之間具 有-繞線區雜於細邊；提供—靜電放電防護電料元；以及 佈局該靜電放電防護電路單元至該繞線區域中。 依據本發明之實施例，其另揭露—種具有靜電放電防護功能 之晶片。該晶片包含有：-輪入/輸出電路單元，位於該晶片之一 侧邊；一角落單元，位於該晶片之該侧邊，其中該輸入/輸出電路 單元與該肖落單元之間具有—繞線區域位於該侧邊；以及一靜電 放電防護電路單元，位於該繞線區域中。 【實施方式】 請參考第2圖，第2圖所示為本發明晶片2〇〇之一實施例的 電路佈局示意圖。如第2圖所示，晶片2〇〇之一側邊設置有一電 源繞線210、一接地繞線22〇、用來接收輸入訊號或是送出輸 出訊號之複數個輸入/輸出電路單元23〇a、23〇b、分別位於兩輸 入/輸出電路單元230a、230b間及輸入/輸出電路單元23〇b與角落 單元245間之複數個繞線區域24〇a、24〇b以及複數個靜電放電防 護電路250a、250b、250c。在不影響本發明技術揭露之下，相較 於第1圖所示之習知晶片100,第2圖僅顯示本發明晶片2〇〇之部 200849540 分電路。本實施例中，繞線區域240a、240b除了提供輸入/輸出電 路單元230a、230b之電源繞線210與接地繞線220之間的連接以 外，另用來設置靜電放電防護電路250a、250b、250c連接於電源 繞線210與地繞線220之間以提供靜電放電防護功能，此外，第2 圖所示之實施例中，繞線區域240a的大小係大於繞線區域24〇b 的大小，因此，多個靜電放電防護電路250a、250b係分別佈局於 繞線區域240a中兩個子繞線區域240a__l、240a一2中。請注意，複 數個靜電放電防護電路250a、250b、250c係可依據需求分別選擇 不同型式的靜電放電防護電路。換言之，本案所揭露之電路佈局 方法可依據繞線區域的大小來決定所要使用之靜電放電防護電路 的型式與個數。 凊參考第3圖，第3圖所示本發明一實施例之將電源箝制電 路佈局於兩輸入輸出電路單元之間之繞線區域的電路示意圖。如 第3圖所不，晶片3〇〇之一側邊設置有一電源繞線31〇、一接地繞 線320'用來接收輸入訊號或/且送出輸出訊號之複數個輸入 /輸出電路單元330a、330b、位於兩輸入/輸出電路單元間之一繞線 區域340以及複數個電源箝制電路35〇a、35〇b分別佈局於繞線區 域340之子繞線區域340J、340一2中。繞線區域340除了用來提 供輸入/輸出電路單元33〇a、330b之電源繞線之間的連接以外，另 設置有複數個電源箝制電路35〇a、35〇b連接於電源繞線31〇與地 繞線320之間以提供靜電放電防護功能。在本實施例中，假設繞 線區域340具有較大的空間，因此，可以將多個的電源籍制電路 200849540 350佈局於繞線區域340巾，以達到更佳的靜電放電防護效果，然 而，此僅為範例說明，並非是本發明的限制。請注意，複數個電 源箝制電路350a、350b可依據需求分別選擇*同型式的電源籍制 電，。一般而言’在晶片300之側邊所設置的複數個輸入/輸出電 路單元330a、330b中，也會依照空間配置以及需求加入靜電放電 護電路於其巾。此外’此—實蘭巾僅說縣電源箝制電路設 置於兩輸人/輸出電路單元之間的繞線區域，然而，熟習此項技藝 者經由以上所述之技術内容應可輕易地得知本發明亦可將 制電路設置於輸入/輸出電路單元與角落單元之間的繞線區域，'故 於此便不另贅述。 凊參考第4圖，第4圖為第3圖所示之電源箝制電路之一第 -實施例的電路示意圖。如第4圖所示，電源箝制電路4⑻連接 於一電源繞線410與一接地繞線420之間，其包含有一電阻43〇、 一電容440以及一 ρ型金氧半導體(㈣押M〇s，pM〇s)電晶體 450 ;其中，電容440在實作上會使用一金氧半導體電容(MOS capacitor)，而電阻43〇與電容44〇形成一電容電阻網路(rc network)。在本實施例中，當有一靜電波形發生在電源繞線上 時，，由於該電容電阻網路會使訊號產生—延遲效應，因此第4圖 中之節點VI電壓上升的速度會較電源繞線彻慢，因此點 力與電源繞線形成一電位差：同一時間，相同的電壓差出現 在P型金氧半導體電晶體450與電源繞線41〇之間。當此電壓差 大於P型通道金氧半導體電晶體450之臨界電壓恤es_ v〇itage) 200849540 - 日守’p型金氧半導體電晶體45〇即會導通。因此靜電放電防護電路 (亦即電源箝制電路400)便可提供一靜電放電電流路徑，以免靜 電放電時電流流入1C内部電路而造成損傷。 请參考第5圖，第5圖為第3圖所示之電源箝制電路之一第 二實施例的電路示意圖。如第5圖所示，電源箝制電路5〇〇係連 接於一電源繞線510與一接地繞線520之間，且包含有一電阻 530、一電容540、一反向器550以及一 n型金氧半導體電晶體56〇。 其中，電容540在實作上會使用一金氧半導體電容，而電阻53〇 與電容540形成一電容電阻網路；反向器55〇包含一 p型金氧半 導體電晶體551以及一 n型金氧半導體電晶體552。在本實施例 中，當有一靜電波形發生在電源繞線510上時，由於該電容電阻 網路會使訊號產生一延遲效應，因此第5圖中之節點電壓上升 的速度會較電源繞線510慢，因此在節點vi與電源繞線51〇之間 形成一電壓差·同一時間，相同的電壓差出現在ρ型金氧半導體 電晶體551與電源繞線510之間。當此電壓差大於ρ型金氧半導 體電晶體551之臨界電壓時，ρ型金氧半導體電晶體551即會導 通，所以節點V2的電壓會被往上拉至接近電源繞線5丨〇之電壓準 位。對η型金氧半導體電晶體560而言，節點V2即是其閘極(gate)， 此時節點V2的電壓會大於n型金氧半導體電晶體56〇的臨界電 壓，如此一來，η型金氧半導體電晶體56〇就會導通以疏浚 . (discharSe)靜電電流，因此靜電放電防護電路（亦即電源箝制電 路500)提供了靜電放電電流路徑，以免靜電放電時電流流入Ic 12 200849540 内部電路而造成損傷。 而言’靜電放電防護電路的數量越多，對於靜電放電防 門不越好然而’當兩輪入輸出電路單元之間的繞線區域空 :士足或者輸人輸㈣路單元與角落單元之_繞祕域空間不 k ’本發明另揭露_佈局面積較小的電源箝制電路。如第6 Z斤不’第6圖為第3圖所示之電源箝制電路之-第三實施例的 =示意圖。_制電路_連接於—獅繞_與一接地 繞線620 ’且包含右—η开丨〗、上、苦 半導體許640 / 體電晶體630以及一 Ρ型金氧 aa - ⑽，此電源箝制電路議本身具有較小的佈 本實施例中，n型金氧半_晶體_以及P型金氧 -;、S曰體64G可分別作為—電源㈣電路，以疏浚靜電電流。 上述係以電源箝制電路來作為佈局於兩輸入輸出電路單元之 間之繞線_巾的靜魏電防魏路，_，本㈣絲以此為 限。睛參考第7圖，第7騎示為本發明一實施例之將電容佈局 於兩輸入輸出電路單元之間之繞線區域的電路示意圖。如第7圖 卿’日日日片700之-側邊設置有一電源繞線爪、一接地繞線勝 複數個輸入/輸出電路單元730a、73〇b，用來接收輸入訊號或/ 且达出輸itm號、錄秘人/細電路單糾之魏個 域屬、7儀以及複數個電容顺、黑分別佈局於繞:域° 740a :740b中。複數個繞線區域74〇a、7働除了作為輸入/輸出 電路單元之電源繞線/接地繞線之間的連接外，另設置複數個電容 13 200849540 、 • 750a、750b連接於該電源繞線710與接地繞線720之間以提供靜 電放電防護功能。在本實施例中，假設繞線區域740a、740b具有 較小的空間，因此無法放置前述之電源箝制電路的完整電路，故 在空間不足的情形下，繞線區域740a、740b可放置電容750a、750b 以作為前述之電源箝制電路中電容電阻網路的電容；而該電源箝 制電路之其他元件則放置於輸入/輸出電路單元730a、730b中，如 此一來，也能間接增進晶片700之靜電放電防護能力。此外，此 一實施例中僅說明將電容設置於兩輸入/輸出電路單元之間的繞線 區域，然而，熟習此項技藝者經由以上所述之技術揭露應可輕易 地得知本發明亦可將電容設置於輸入/輸出電路單元與角落單元之 間的繞線區域，故於此便不另贅述。 凊注思，於第3圖所示之實施例中，每一繞線區域中均設置 電源箝制電路，而於於第7圖所示之實施例中，每一繞線區域中 均设置電容’然而，此僅為範例說明’亦即於本發明其他實施例 中’亦可於同-晶片的複數個繞線區域中依據設計需求而同時設 置有電源箝制電路、電容與其他可提供靜電防護功能的元件，亦 符合本發明之精神。 請參馨8 第8目為本發0勝魏電賴料方法之一 實施例的流程圖。靜電放電防護設計方法係用來實現第 之晶片200的電路佈局，其步驟簡要歸納如下： " 14 200849540 步驟800 :開始； 步驟802 :將一第一輸入/輸出電 早疋（例如第2圖所示之輪入/ 輸出電路單元230a)、一第-仏^ 翰入/ D ^ - ^ 弟一輪入/輸出電路單元（例如 第2圖所枚輸入/輪出電路單元糊以及一角 疋（例如第2圖所示之角落單元245)佈局於一晶片之 側邊其中該第-、第二輪入/輸出電路單元之間具有 一第-繞線區域（例如第2圖所示之繞線區域細心位 於該侧邊以及該第二輪入/輸出電路單元以及該角落單 疋之間具有-第二繞醜域（例如第2圖所示之繞線區 域240b)位於該側邊； 步驟_ :依據該第―、第二繞線區域之面積大小分別提供一第 -靜電放電防護f路單元與—第二靜電放電防護電路 單元（例如電源箝制電路、電容與其他可提供靜電防護 功能的元件）； 步驟806 ·分別佈局該第―、第二靜電放電防護電路單元至該第 一、第二繞線區域中；以及 步驟808 ··結束。 睛注意，由於本發明靜電放電防護設計的技術特徵已於上詳 細揭露’故第8圖所示之流程中各個步驟的操作細節便不另於此 贅述。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 15 200849540 、 _做之均等變化與修飾，皆應屬本發明之涵蓋賴。 【圖式簡單說明】 第1圖為習知晶片的電路佈局示意圖。 第2圖為本發明晶片之—實施例的電路佈局示意圖。 第3圖所示本發明一實施例之將電源箝制電路佈局於兩輸入輸出 電路單元之間之繞線區域的電路示意圖。 第4圖為第3圖所示之電源箝制電路之一第—實施例的電路示意 圖。 第5圖為第3圖所示之電源箝制電路之一第二實施例的電路示意 圖。 第6圖為第3圖所示之魏箝制電路之一第三實施例的電路示意 圖。 第7圖所示為本發明-實施狀將電容佈局麵輸人輸出電路單 元之間之繞線區域的電路示意圖。 第8圖為本發明靜電放電防護設計方法之—實施例的流裎圖。 【主要元件符號說明】 100、200、600、700 -—η 110、230a、230b、630a、630b、730a、 輪入輪出電路單元厂〜一 730b 120、240a、240b、640、740a、740b 130、245 -— 16 200849540 210、310、410、510、610、710 電源繞線 220、320、420、520、620、720 接地繞線 240a_l、240a_2、640—1、640—2 子繞線區域 250a、250b、250c 靜電放電防護電路 330、430 電阻 340、440、750 電容 300、400、500、650a、650b 電源箝制電路 452、460、530 η型金氧半導體電晶體 350、45卜 540 Ρ型金氧半導體電晶體 17Electro-Static Discharge) event. Therefore, - unit 11. There will be an electrostatic discharge protection circuit in the static: Out:: The protection circuit can be in the two input circuit unit u 4 electric discharge current path, 佶 盔 盔 木 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + The static charge occurs in one of the inputs/rounds 兀¥, and the current generated by the electrostatic discharge can preferentially flow from this to the other internals of the wafer: only the other internal circuits in the '=:chip:: are not Electrostatic discharge effects. Will input / turn out the circuit unit view - defeat I discharge protection circuit is ★ Qing circuit early purchase and guide material discharge grab, in order to bypass the electrostatic discharge current, making it in the ancient film Other internal circuits. However, when j, "IL enters the crystal, the ESD circuit will suspend its current path established in the two-input/round-out circuit list == 7 200849540, so as not to hinder the normal function of the wafer 100. In general, many electrostatic discharge protection circuits are often added to the circuit design to enhance the effect of electrostatic discharge protection. However, increasing the electrostatic discharge protection circuit also occupies a large layout area, which also causes an increase in wafer production cost. Therefore, how Choosing the right ESD protection circuit and proper layout is an important issue in circuit layout design. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an electrostatic discharge protection design method and associated circuit capable of placing an ESD protection circuit unit in accordance with a space between existing input/wheeling circuit unit layouts. In accordance with an embodiment of the present invention, a method of electrostatic discharge protection design is disclosed. The method includes: arranging a first input/output circuit unit and a second input/output circuit unit on a side of the wafer, wherein the first and second input/output circuits have an interval between 7L and - The surrounding turtle domain is located at the side; providing an electrostatic discharge protection circuit unit; and arranging the electrostatic discharge anti-Wei road unit in the Weiling area. According to an embodiment of the present invention, a wafer having an electrostatic discharge protection function is disclosed. The chip comprises: a first input/output circuit unit, located on one side of the chip, a 苐-input/output circuit army $^ 屯峪 early 70, located on the side of the chip, There is a winding area between the side of the side, the third input, the output circuit of the input/output circuit, the 200849540 side, and the -electrostatic discharge anti-wei unit, located in the winding area. In accordance with an embodiment of the present invention, an electrostatic discharge protection design method is further disclosed. The method comprises: arranging a wheeled person/rounding unit and a sloping unit on a side of the wafer-side thereof, and having a winding area between the wheeled person/rounding circuit unit and the slanting unit Providing an electrostatic discharge protection electric element; and arranging the electrostatic discharge protection circuit unit to the winding area. According to an embodiment of the present invention, there is further disclosed a wafer having an electrostatic discharge protection function. The wafer comprises: a wheel input/output circuit unit located on one side of the wafer; a corner unit located on the side of the wafer, wherein the input/output circuit unit and the sloping unit have a winding The line area is located at the side; and an ESD protection circuit unit is located in the winding area. [Embodiment] Please refer to Fig. 2, which shows a circuit layout of an embodiment of a wafer 2 according to the present invention. As shown in FIG. 2, one side of the chip 2 is provided with a power supply wire 210, a ground wire 22, a plurality of input/output circuit units for receiving an input signal or for outputting an output signal. 23〇b, a plurality of winding areas 24〇a, 24〇b between the two input/output circuit units 230a and 230b and between the input/output circuit unit 23〇b and the corner unit 245, and a plurality of electrostatic discharge protection Circuits 250a, 250b, 250c. Without affecting the disclosure of the present invention, FIG. 2 shows only the 200849540 sub-circuit of the wafer 2 of the present invention compared to the conventional wafer 100 shown in FIG. In the present embodiment, the winding regions 240a, 240b are provided for providing the electrostatic discharge protection circuits 250a, 250b, 250c in addition to the connection between the power supply winding 210 and the ground winding 220 of the input/output circuit units 230a, 230b. Connected between the power supply winding 210 and the ground winding 220 to provide an electrostatic discharge protection function. Further, in the embodiment shown in FIG. 2, the size of the winding area 240a is larger than the size of the winding area 24〇b, A plurality of electrostatic discharge protection circuits 250a, 250b are respectively disposed in the two sub-wound regions 240a__1, 240a-2 in the winding region 240a. Please note that a plurality of ESD protection circuits 250a, 250b, 250c can select different types of ESD protection circuits according to requirements. In other words, the circuit layout method disclosed in the present invention can determine the type and number of ESD protection circuits to be used depending on the size of the winding area. Referring to Fig. 3, there is shown a circuit diagram of a winding region in which a power supply clamp circuit is disposed between two input/output circuit units according to an embodiment of the present invention. As shown in FIG. 3, a power supply winding 31A is disposed on one side of the chip 3, and a ground winding 320' is used to receive an input signal or/and a plurality of input/output circuit units 330a for outputting an output signal. 330b, a winding area 340 between the two input/output circuit units, and a plurality of power supply clamping circuits 35A, 35B are respectively arranged in the sub-winding areas 340J, 340-2 of the winding area 340. The winding area 340 is provided with a plurality of power supply clamp circuits 35a, 35b connected to the power supply winding 31 in addition to the connection between the power supply windings of the input/output circuit units 33a, 330b. Between the ground winding 320 and the ground winding 320 to provide an electrostatic discharge protection function. In this embodiment, it is assumed that the winding area 340 has a large space. Therefore, a plurality of power source circuits 200849540 350 can be arranged in the winding area 340 to achieve better electrostatic discharge protection effect, however, This is merely an example and is not a limitation of the invention. Please note that a plurality of power clamping circuits 350a, 350b can select the same type of power source power supply according to requirements. In general, in a plurality of input/output circuit units 330a, 330b disposed on the side of the wafer 300, an electrostatic discharge protection circuit is also added to the substrate in accordance with the space configuration and requirements. In addition, the 'this-Shilan towel only states that the county power supply clamp circuit is disposed in the winding area between the two input/output circuit units. However, those skilled in the art should easily know the present contents through the above technical contents. The invention can also provide a circuit in a winding area between the input/output circuit unit and the corner unit, so that it will not be described here. Referring to Fig. 4, Fig. 4 is a circuit diagram showing a first embodiment of the power supply clamp circuit shown in Fig. 3. As shown in FIG. 4, the power supply clamping circuit 4 (8) is connected between a power supply winding 410 and a grounding winding 420, and includes a resistor 43A, a capacitor 440, and a p-type metal oxide semiconductor ((4). , pM 〇 s) transistor 450; wherein the capacitor 440 is implemented using a MOS capacitor, and the resistor 43 〇 and the capacitor 44 〇 form a rc network. In this embodiment, when an electrostatic waveform occurs on the power supply winding, since the capacitor resistance network causes a signal-delay effect, the voltage of the node VI in FIG. 4 rises faster than the power supply. Slow, so the point force forms a potential difference with the power supply winding: at the same time, the same voltage difference occurs between the P-type MOS transistor 450 and the power supply winding 41〇. When this voltage difference is greater than the critical voltage of the P-channel MOS transistor 450, es_v〇itage) 200849540 - The defensive 'p-type MOS transistor 45 〇 will turn on. Therefore, the ESD protection circuit (i.e., the power supply clamping circuit 400) can provide an ESD current path to prevent current from flowing into the 1C internal circuit during electrostatic discharge. Referring to Fig. 5, Fig. 5 is a circuit diagram showing a second embodiment of the power supply clamp circuit shown in Fig. 3. As shown in FIG. 5, the power supply clamping circuit 5 is connected between a power supply winding 510 and a grounding winding 520, and includes a resistor 530, a capacitor 540, an inverter 550, and an n-type gold. Oxygen semiconductor transistor 56〇. Wherein, the capacitor 540 is implemented using a MOS capacitor, and the resistor 53 〇 and the capacitor 540 form a capacitor resistor network; the inverter 55 〇 includes a p-type MOS transistor 551 and an n-type gold Oxygen semiconductor transistor 552. In this embodiment, when an electrostatic waveform occurs on the power supply winding 510, since the capacitor resistance network causes a delay effect on the signal, the node voltage in FIG. 5 rises faster than the power supply winding 510. Slow, so a voltage difference is formed between the node vi and the power supply winding 51 · at the same time, and the same voltage difference occurs between the p-type MOS transistor 551 and the power supply winding 510. When the voltage difference is greater than the threshold voltage of the p-type MOS transistor 551, the p-type MOS transistor 551 is turned on, so the voltage of the node V2 is pulled up to a voltage close to the power supply winding 5 丨〇. Level. For the n-type MOS transistor 560, the node V2 is its gate, and the voltage of the node V2 is greater than the threshold voltage of the n-type MOS transistor 56, so that the n-type The MOS transistor 56 turns on to dissipate (discharSe) electrostatic current, so the ESD protection circuit (ie, the power supply clamp circuit 500) provides an ESD current path to prevent current from flowing into the Ic 12 200849540 internal circuit during electrostatic discharge. And cause damage. In terms of 'the more the number of ESD protection circuits, the better the anti-static discharge is not good. However, the winding area between the two-input output circuit unit is empty: the foot or the input (four) way unit and the corner unit _ Around the secret space is not k 'The invention further discloses a power supply clamp circuit with a small layout area. For example, the sixth figure is not shown in Fig. 6 as a schematic diagram of the third embodiment of the power supply clamp circuit shown in Fig. 3. _ circuit _ connected to - lion winding _ and a ground winding 620 ' and including right - η opening 丨, upper, bitter semiconductor 640 / body transistor 630 and a 金 type of gold oxygen aa - (10), this power supply clamp The circuit itself has a small layout. In the embodiment, the n-type gold oxide half-crystal_and the P-type gold-oxygen-; and the S-body 64G can be respectively used as a power supply (four) circuit to dredge the electrostatic current. The above is based on the power clamp circuit as the winding wire between the two input and output circuit units, and the _, the fourth wire is limited to this. Referring to Fig. 7, a seventh ride shows a circuit diagram of a winding area in which a capacitor is disposed between two input/output circuit units according to an embodiment of the present invention. For example, in Figure 7, the Japanese solar chip 700 has a power supply winding claw and a ground winding to win a plurality of input/output circuit units 730a and 73〇b for receiving an input signal or/and The input itm number, the recorded secret person/fine circuit single correction, the Wei domain, the 7 instrument, and the plurality of capacitors are arranged in the winding: field ° 740a: 740b. In addition to the connection between the power supply winding/grounding winding of the input/output circuit unit, a plurality of winding areas 74〇a, 7働 are additionally provided with a plurality of capacitors 13 200849540, • 750a, 750b connected to the power supply winding Between 710 and ground winding 720 to provide electrostatic discharge protection. In the present embodiment, it is assumed that the winding regions 740a, 740b have a small space, so that the complete circuit of the power supply clamping circuit described above cannot be placed, so that in the case of insufficient space, the winding regions 740a, 740b can be placed with the capacitor 750a, 750b is used as the capacitance of the capacitor resistor network in the foregoing power clamp circuit; and other components of the power clamp circuit are placed in the input/output circuit units 730a, 730b, so that the electrostatic discharge of the wafer 700 can be indirectly enhanced. Protection ability. In addition, in this embodiment, only the winding area where the capacitor is disposed between the two input/output circuit units is described. However, those skilled in the art should easily know that the present invention can also be known by the above-mentioned technology. The capacitor is disposed in the winding area between the input/output circuit unit and the corner unit, and thus will not be further described herein. It is to be noted that in the embodiment shown in Fig. 3, a power supply clamp circuit is provided in each of the winding regions, and in the embodiment shown in Fig. 7, a capacitance is provided in each of the winding regions. However, this is merely an example description, that is, in other embodiments of the present invention, a power supply clamp circuit, a capacitor, and other electrostatic protection functions may be simultaneously provided in a plurality of winding regions of the same-wafer according to design requirements. The components are also in accordance with the spirit of the invention. Please refer to the 8th head of this method for the 0-win Weiwei method. The ESD protection design method is used to implement the circuit layout of the first wafer 200, and the steps thereof are summarized as follows: " 14 200849540 Step 800: Start; Step 802: Put a first input/output power early (for example, Figure 2 The wheeled in/out circuit unit 230a), a first-in-one/in-one circuit/in circuit unit (for example, the input/round-out circuit unit paste of FIG. 2 and a corner 疋 (for example The corner unit 245 shown in FIG. 2 is arranged on the side of a wafer, wherein the first and second wheel input/output circuit units have a first-wound region (for example, the winding region shown in FIG. 2). Carefully located on the side and between the second wheel input/output circuit unit and the corner unit, a second winding field (for example, the winding area 240b shown in FIG. 2) is located on the side; Step _: Providing a first-electrostatic discharge protection f-channel unit and a second electrostatic discharge protection circuit unit (such as a power supply clamp circuit, a capacitor and other components capable of providing electrostatic protection function) according to the area of the first and second winding regions respectively ; Step 806 · Separate The first and second electrostatic discharge protection circuit units are in the first and second winding regions; and the step 808 is finished. Note that the technical features of the electrostatic discharge protection design of the present invention have been disclosed in detail above. Therefore, the details of the operation of each step in the process shown in FIG. 8 are not described herein. The above description is only a preferred embodiment of the present invention, and the equivalent of the invention is disclosed in the patent application No. 15 200849540. Modifications should be covered by the present invention. [Simplified Schematic Description] Fig. 1 is a schematic diagram showing the circuit layout of a conventional wafer. Fig. 2 is a schematic diagram showing the circuit layout of the wafer according to the embodiment of the present invention. A circuit diagram of a power supply clamping circuit disposed in a winding area between two input/output circuit units according to an embodiment of the present invention. FIG. 4 is a circuit diagram of a first embodiment of the power supply clamping circuit shown in FIG. Fig. 5 is a circuit diagram showing a second embodiment of the power supply clamp circuit shown in Fig. 3. Fig. 6 is a circuit diagram showing a third embodiment of the Wei clamp circuit shown in Fig. 3. 7 is a circuit diagram showing the winding area between the capacitor layout surface and the output circuit unit according to the embodiment of the present invention. FIG. 8 is a flow diagram of an embodiment of the electrostatic discharge protection design method of the present invention. Main component symbol description] 100, 200, 600, 700 - η 110, 230a, 230b, 630a, 630b, 730a, wheel-in circuit unit ~ 730b 120, 240a, 240b, 640, 740a, 740b 130, 245 - 16 200849540 210, 310, 410, 510, 610, 710 power windings 220, 320, 420, 520, 620, 720 ground winding 240a_1, 240a_2, 644-1, 640-2 sub-wound area 250a, 250b, 250c Electrostatic discharge protection circuit 330, 430 Resistor 340, 440, 750 Capacitance 300, 400, 500, 650a, 650b Power supply clamp circuit 452, 460, 530 n-type MOS transistor 350, 45 540 Ρ type gold oxide Semiconductor transistor 17