CN103813587A - LED drive circuit with digital-analog hybrid dimming function - Google Patents

Abstract

The invention discloses an LED drive circuit with digital-analog hybrid dimming function, which mainly solves the slow input response speed of the circuit structure of the existing voltage control mode, including a dimming control unit, a peak current detection sampling unit and a constant off-time control unit. The dimming control unit adjusts the size of the average current flowing through the LED through two dimming methods, analog and digital, to achieve brightness adjustment, and outputs the peak current detection threshold V _CST1 to the peak current detection sampling unit, and outputs two enable V _EN1 and V _EN2 are given to the constant off-time control unit; the peak current detection sampling unit inputs the comparison result to the constant off-time control unit; the constant off-time control unit generates a constant off-time when the peak current is detected . The invention improves the input response speed, can realize fast digital-analog hybrid dimming, and can be applied to LED driving circuits.

Description

A kind of digital-to-analogue is mixed the LED drive circuit of light modulation

Technical field

The invention belongs to electronic circuit technology field, relate to analog integrated circuit, particularly a kind of digital-to-analogue is mixed the LED drive circuit of light modulation.

Background technology

Along with the fast development of semiconductor technology and the continuous expansion of application, the LED lighting technology with advantages such as environmental protection, energy-conservation, efficiency is high, the life-span is long has now been widely used in the every field such as automotive lighting, architectural lighting.Need LED to drive the cooperation of chip but bring into play these advantages, therefore, further developing of LED drive integrated circult becomes social active demand.In common several LED drive circuits, DC-DC transducer, because its operating efficiency is high, simple to operate, has now obtained general application.DC-DC transducer is the circuit structure that a certain DC input voitage is converted to another VD, and its principle is by the duty ratio of the time that the turns on and off regulation loop of power ratio control switching tube, thereby maintains the constant of output.DC-DC change-over circuit mainly contains Buck(step-down), Boost(boosts), Cuk(buck) and four kinds of topological structures of liter-step-down (Buck-Boost), generally formed by power switch pipe, energy-storage travelling wave tube inductance, fly-wheel diode, electric capacity, comparator and error amplifier.Come unlatching and the turn-off time of power ratio control switching tube by the feedback control loop being formed by error amplifier and comparator, thereby maintain the constant of output.Whole circuit utilizes energy storage on inductance to provide continuous electric current for load.

The system configuration of typical voltage mode control DC-DC transducer as shown in Figure 1.In this circuit, comprise a voltage negative feedback control loop, adopt pulse-width modulation method (PWM) to realize and control.Specific works principle is: output voltage V _oUTthrough sampling resistor R _sNSafter dividing potential drop with reference voltage V _rEFcompare, its difference obtains V after error amplifier amplifies _cOMP, as the in-phase input end of PWM comparator, by with the sawtooth signal V of PWM comparator inverting input _rAMPcompare, carry out power ratio control switching tube Q with gained signal after relatively ₁open and shut off.Work as output voltage V _oUTwhen decline, by sampling resistor R _sNSdividing potential drop gained feedback voltage signal can decline, the voltage V after amplifying by error amplifier _cOMPcan increase, make power switch pipe Q ₁oN time increase, output voltage rise.Voltage mode control maintains the constant of output by this degenerative mode.But this voltage mode control DC-DC transducer needs external compensation network, makes to input response speed slow, control loop is vulnerable to the interference of electric current.

Summary of the invention

The object of the invention is to; input response speed for above-mentioned voltage mode control DC-DC transducer is slow; and control loop is vulnerable to the problem of the interference of electric current; propose a kind of digital-to-analogue and mix the LED drive circuit of light modulation; this circuit can be realized constant turn-off time control model, and has digital-to-analogue mixing dimming function.At power switch pipe Q ₁under turn-on condition, when the first resistance R ₁when both end voltage reaches the threshold voltage of comparator of setting, the peak current setting detected, Q ₁turn-off.In addition, the turn-off time of system is constant.Whole circuit structure is simple, and it is convenient to control; Sluggish control response speed is fast; Loop compensation is succinct; The stability of a system is good.

For achieving the above object, the present invention adopts following technical scheme to be solved:

Digital-to-analogue is mixed a LED drive circuit for light modulation, comprises as lower unit:

Dimming control unit, comprises analog light-adjusting circuit and digital light-adjusting circuit, and wherein, described analog light-adjusting circuit is used for receiving driving voltage V _aDJ1, and by regulating driving voltage V _aDJ1magnitude of voltage and export peak current detection threshold voltage V _cST1, and will be input to peak current detection sampling unit; Described digital light-adjusting circuit is used for receiving enable signal V _eN, and at enable signal V _eNcontrol under, to peak current detection sampling unit and constant turn-off time control unit output enable signal V _eN1, simultaneously to constant turn-off time control unit output enable signal V _eN2;

Peak current detection sampling unit, the peak current detection threshold voltage V sending for receiving the reception analog light-adjusting circuit of dimming control unit _cST1and the output enable signal V of digital light-adjusting circuit transmission _eN1; And at enable signal V _eN1control under, by input voltage V _iNwith by input voltage V _iNthrough pressure drop V _sNSthe voltage V obtaining ₁with peak value detection threshold voltage V _cST1compare, to realize the detection of peak current, and by output signal V ₃input constant turn-off time control unit;

Constant turn-off time control unit: the enable signal V sending for receiving dimming control unit digital light-adjusting circuit _eN1with enable signal V _eN2, receive the output signal V that peak current detection sampling unit sends simultaneously ₃; And at enable signal V _eN1with enable signal V _eN2under control, in the time peak current being detected, regulate input voltage V _aDJ2, obtain an output voltage V ₂, and by output voltage V ₂be delivered to power switch pipe Q ₁;

Power switch pipe Q ₁: the output voltage V sending for receiving constant turn-off time control unit ₂, and according to output voltage V ₂produce a constant turn-off time T _oFF;

DC power supply first capacitor C in parallel of input ₁after obtain input voltage V _iN, the first resistance R ₁the input voltage V at two ends _iNwith voltage V ₁be connected to peak current detection unit; The output voltage V of constant turn-off time control unit output ₂be connected to a driving Driver, for power ratio control switching tube Q ₁turn-on and turn-off; Power switch pipe Q ₁with Schottky diode D ₁with the second capacitor C ₂parallel connection, and with the first inductance L ₁series connection.

Further, described dimming control unit comprises analog light-adjusting circuit and digital light-adjusting circuit.

Further, described analog light-adjusting circuit comprises that amplifier, NMOS manage M ₁₀₁, the second resistance R ₂, the 3rd resistance R ₃with current source I _s1; Described digital light-adjusting circuit 12 comprises that the first Schmidt trigger and the second Schmidt trigger, inverter, PMOS manage M ₁₀₂, PMOS manages M ₁₀₄, NMOS manages M ₁₀₃, NMOS manages M ₁₀₅with the 3rd capacitor C ₃; Wherein:

Described amplifier, its in-phase input end is connected to driving voltage V _aDJ1, and by the 3rd resistance R ₃ground connection; Its end of oppisite phase is by the second resistance R ₂ground connection; Its output is connected to NMOS pipe M ₁₀₁grid; NMOS manages M ₁₀₁drain electrode be connected to the input threshold voltage V of peak current detection sampling unit _cST1, its source class is by the second resistance R ₂ground connection; Current source I _s1input access internal electric source V _dD, its output is by the 3rd resistance R ₃receive ground, and access V _aDJ1;

Described the first Schmidt trigger, its input is connected on NMOS pipe M ₁₀₃drain electrode, be connected on the 3rd capacitor C simultaneously ₃positive pole, its output is connected on the input of inverter, accesses enable signal V simultaneously _eN1; Its power end meets respectively internal electric source V _dDand ground;

Described the second Schmidt trigger, its input is connected on the output of inverter, connects PMOS pipe M simultaneously ₁₀₄with NMOS pipe M ₁₀₅drain electrode; Its output is connected to the enable signal V of an input of NAND gate in constant turn-off time control unit _eN2on; Its power end is connected on respectively internal electric source V _dDand on the ground;

Described inverter, its input is connected on the output of Schmidt trigger, and its output is connected to PMOS pipe M ₁₀₄grid on; PMOS manages M ₁₀₂, its source electrode connects internal electric source V _dD, its grid directly arrives ground; PMOS manages M ₁₀₄, its source electrode access internal electric source V _dD; NMOS manages M ₁₀₃, its grid connection enables input signal V _eN, its source class ground connection; NMOS manages M ₁₀₅, its source class ground connection, its grid access enables input signal V _eN; The 3rd capacitor C ₃, its minus earth.

Further, described peak current detection sampling unit, comprises inverter, current source I _s2, the 4th resistance R ₄, the 5th resistance R ₅, the 6th resistance R ₆, the 7th resistance R ₇, high voltage PMOS pipe M ₂₀₃, high voltage PMOS pipe M ₂₀₅, high pressure NMOS pipe M ₂₀₄, high pressure NMOS pipe M ₂₀₆, NMOS manages M ₂₀₁, NMOS manages M ₂₀₂, NMOS manages M ₂₀₇, NMOS manages M ₂₀₈, NMOS manages M ₂₀₉, NMOS manages M ₂₁₀, NMOS manages M ₂₁₁, NMOS manages M ₂₁₂, NMOS manages M ₂₁₅, NMOS manages M ₂₂₀, NMOS manages M ₂₂₁, NMOS manages M ₂₂₃, NMOS manages M ₂₂₄, NMOS manages M ₂₂₆, PMOS manages M ₂₁₃, PMOS manages M ₂₁₄, PMOS manages M ₂₁₆, PMOS manages M ₂₁₇, PMOS manages M ₂₁₈, PMOS manages M ₂₁₉, PMOS manages M ₂₂₂with PMOS pipe M ₂₂₅; Wherein:

Described inverter, its input connection enables input signal V _eN1, its output termination NMOS pipe M ₂₀₇;

Described current source I _s2, its input termination internal electric source V _dD, its output is connected on NMOS pipe M ₂₀₇and M ₂₀₈drain electrode on, be connected on NMOS pipe M simultaneously ₂₀₈and M ₂₀₉grid on; Described NMOS pipe M ₂₀₈, M ₂₀₉, M ₂₁₀, M ₂₁₁, M ₂₁₂structure current mirror in a row, NMOS manages M ₂₀₈, M ₂₀₉, M ₂₁₀, M ₂₁₁, M ₂₁₂grid be all connected to NMOS pipe M ₂₀₈grid on, source electrode is ground connection all;

Described NMOS pipe M ₂₀₉drain electrode be connected on the NMOS pipe M of composition differential pair ₂₀₁, M ₂₀₂source electrode on; Wherein NMOS pipe M ₂₁₀drain electrode be connected on high pressure NMOS pipe M ₂₀₄source electrode on; NMOS manages M ₂₁₁drain electrode be connected on high pressure NMOS pipe M ₂₀₆source electrode on, NMOS manages M ₂₁₂drain electrode be connected on PMOS pipe M ₂₁₃drain electrode on;

Described NMOS pipe M ₂₀₁and M ₂₀₂form differential pair, their drain electrode is respectively by the 6th resistance R ₆with the 7th resistance R ₇be connected on input voltage V _iNupper, their grid is respectively by the 4th resistance R ₄with the 5th resistance R ₅be connected to input voltage V ₁and V _iNon;

Described high voltage PMOS pipe M ₂₀₃, M ₂₀₅with NMOS pipe M ₂₀₄, M ₂₀₆drain electrode high-voltage tube, wherein, high voltage PMOS pipe M ₂₀₃, M ₂₀₅source electrode be connected on respectively differential pair NMOS pipe M ₂₀₁, M ₂₀₂drain electrode on, their drain electrode is connected to NMOS pipe M ₂₀₄, M ₂₀₆drain electrode on, their grid all connects input voltage V _b1; High pressure NMOS pipe M ₂₀₄, M ₂₀₆grid all connect input voltage V _b2, their source class is connected to the NMOS pipe M of composition differential pair ₂₁₉, M ₂₁₈grid on;

Described PMOS pipe M ₂₁₃, M ₂₁₆form current mirror, their source electrode is all received internal electric source V _dD, PMOS manages M ₂₁₆drain electrode be connected to the PMOS pipe M of composition differential pair ₂₁₈, M ₂₁₉source electrode; PMOS manages M ₂₁₇source electrode connects internal electric source V _dD, grid connects enable signal V _eN1, drain electrode connects PMOS pipe M ₂₁₃drain electrode;

Described PMOS pipe M ₂₁₄and M ₂₂₂form current mirror, their source electrode meets internal electric source V _dD, wherein PMOS pipe M ₂₁₄drain electrode meet NMOS pipe M ₂₁₅drain electrode, PMOS manages M ₂₂₂drain electrode meet NMOS pipe M ₂₂₃drain electrode; Described NMOS pipe M ₂₁₅and M ₂₂₀also form current mirror, all ground connection of its source class, wherein NMOS pipe M ₂₂₀drain electrode be connected on the PMOS pipe M of composition differential pair ₂₁₈drain electrode on; Described NMOS pipe M ₂₂₁and M ₂₂₃also form current mirror, all ground connection of their source electrode, NMOS manages M ₂₂₁drain electrode be connected on the PMOS pipe M of composition differential pair ₂₁₉drain electrode on;

Described NMOS pipe M ₂₂₄, its grid connects enable signal V _eN1, for controlling its on off state, its drain electrode is connected on NMOS pipe M ₂₂₃drain electrode on, source ground; Described PMOS pipe M ₂₂₅with NMOS pipe M ₂₂₆form inverter, the input of this inverter is connected on NMOS pipe M ₂₂₃drain electrode on, its output termination output signal V ₃, wherein PMOS pipe M ₂₂₅source electrode meet internal electric source V _dD, NMOS manages M ₂₂₆source ground.

Further, described constant turn-off time control unit, comprises amplifier, comparator, rest-set flip-flop, inverter, inverter, NAND gate, the 4th capacitor C ₄, the 8th resistance R ₈, PMOS manages M ₃₀₁, PMOS manages M ₃₀₂, PMOS manages M ₃₀₃with PMOS pipe M ₃₀₄, NMOS manages M ₃₀₅with NMOS pipe M ₃₀₆; Wherein:

Described amplifier, its in-phase input end connects input voltage V _aDJ2, reverse input end is by the 8th resistance R ₈ground connection, its output termination NMOS pipe M ₃₀₅grid; Described comparator, its in-phase input end connects reference voltage V _rEF, its anti-phase termination PMOS pipe M ₃₀₃drain electrode, the reset terminal R of its output termination rest-set flip-flop; Described rest-set flip-flop is made up of two NAND gate, and it is put number end S and is connected on the output of inverter, and its output is connected on the input of inverter; Described inverter, the output signal V of its input termination peak current detection sampling unit ₃, described inverter, in an input of its output termination NAND gate; Another input termination enable signal V of described NAND gate _eN2, its output termination output voltage V ₂;

Described PMOS pipe M ₃₀₁, M ₃₀₂, M ₃₀₃and M ₃₀₄form current mirror, wherein, PMOS manages M ₃₀₁and M ₃₀₂source electrode be connected on internal electric source V _dDupper, and drain electrode is connected on respectively PMOS pipe M ₃₀₄and M ₃₀₃source electrode on; By getting identical pipe sizing, obtain current relationship and be: I _d6=i _d7=i _d8=i _d9;

Described PMOS pipe M ₃₀₄drain electrode connect NMOS pipe M ₃₀₅drain electrode, PMOS manages M ₃₀₃drain electrode by the 4th capacitor C ₄ground connection; Described NMOS pipe M ₃₀₅source electrode by the 8th resistance R ₈ground connection, NMOS manages M ₃₀₆grid meet the output signal V of peak current detection sampling unit ₃, its drain electrode connects the inverting input of comparator, source ground.

Further, described peak current detection sampling unit comprises inverter, the 4th resistance R ₄, the 5th resistance R ₅, PMOS manages M ₂₀₁, PMOS manages M ₂₀₂, PMOS manages M ₂₀₅, PMOS manages M ₂₀₆, PMOS manages M ₂₀₉, PMOS manages M ₂₁₂, PMOS manages M ₂₁₃, NMOS manages M ₂₀₃, NMOS manages M ₂₀₄, NMOS manages M ₂₀₇, NMOS manages M ₂₀₈, NMOS manages M ₂₁₀, NMOS manages M ₂₁₁, NMOS manages M ₂₁₄with NMOS pipe M ₂₁₅; Wherein:

Described inverter, its input connects PMOS pipe M ₂₁₃drain electrode, output connects in constant turn-off time control unit NMOS pipe M ₃₀₆grid, for controlling its switch; Described PMOS pipe M ₂₁₂and M ₂₁₃form current mirror, their source electrode all connects internal electric source V _dD, PMOS manages M ₂₁₂drain electrode connect NMOS pipe M ₂₁₄drain electrode, PMOS manages M ₂₁₃drain electrode connect NMOS pipe M ₂₁₅drain electrode;

Described NMOS pipe M ₂₁₅, its grid connects high pressure NMOS pipe M ₂₁₀source class, its source ground; NMOS manages M ₂₁₄, M ₂₁₁, M ₂₀₈grid be all connected on NMOS pipe M ₂₀₇grid on, all ground connection of their source electrode, wherein NMOS pipe M ₂₁₁drain electrode meet high pressure NMOS pipe M ₂₁₀source electrode, NMOS manages M ₂₀₈drain electrode connect high pressure NMOS pipe M ₂₀₆source electrode, NMOS manages M ₂₀₇drain electrode connect high pressure NMOS pipe M ₂₀₅source electrode; High pressure NMOS pipe M ₂₁₀grid connect internal electric source V _dD, its drain electrode connects high voltage PMOS pipe M ₂₀₉drain electrode; Described PMOS pipe M ₂₀₉source electrode connect input voltage V _iN, its grid connects PMOS pipe M ₂₀₂with high pressure NMOS pipe M ₂₀₄drain electrode;

Described PMOS pipe M ₂₀₁and M ₂₀₂form current mirror, their source electrode connects input voltage V _iN, wherein PMOS pipe M ₂₀₁, M ₂₀₂drain electrode connect respectively NMOS pipe M ₂₀₃, M ₂₀₄drain electrode; Described high pressure NMOS pipe M ₂₀₄, its grid connects the output threshold voltage V of analog light-adjusting circuit in dimming control unit _cST, and by the 5th resistance R ₅connect input voltage V _iN, its source electrode and NMOS pipe M ₂₀₃source electrode be all connected to high pressure NMOS pipe M ₂₀₆drain electrode; Described NMOS pipe M ₂₀₃, its grid is by the 4th resistance R ₄connect input voltage V ₁; Described high pressure NMOS pipe M ₂₀₅and M ₂₀₆form current mirror, wherein, NMOS manages M ₂₀₅drain electrode connect current source I _s2.

Further, described constant turn-off time control unit comprises comparator, rest-set flip-flop, inverter and inverter, NAND gate, the 4th capacitor C ₄, the 8th resistance R ₈with NMOS pipe M ₃₀₁; Wherein:

Described comparator, its in-phase input end connects reference voltage V _rEF, its inverting input connects NMOS pipe M ₃₀₁drain electrode, and by the 8th resistance R ₈be connected to output voltage V _aDJ2upper or by the 4th capacitor C ₄ground connection, the reset terminal R of its output termination rest-set flip-flop; Described rest-set flip-flop is made up of two NAND gate, and it is put number end S and is connected on the output of inverter, and its output is connected on the input of inverter; Described inverter, the output signal V of its input termination peak current detection sampling unit ₃; Described inverter, in an input of its output termination NAND gate; Another input termination enable signal V of described NAND gate _eN2, its output termination output voltage V ₂; Described NMOS pipe M ₃₀₁, its grid connects the output signal V of peak current detection sampling unit ₃, its source ground.

The present invention compared with prior art has the following advantages:

1, the present invention is by comparing the first resistance R ₁the threshold voltage of both end voltage and comparator triggers the shutoff of power switch pipe, does not need error amplifier and feedback network, therefore, compared with traditional voltage mode control, has response speed faster.

2, constant turn-off time control model LED drive circuit of the present invention is without external compensation network, and loop compensation is succinct, is easy to realize, and it is convenient to control; And switching frequency is only with V _iNincrease and increase, the stability of a system is good, has effectively avoided control loop in traditional system to be vulnerable to the problem of current interference.

Accompanying drawing explanation

Fig. 1 is the system block diagram of traditional LED drive circuit.

Fig. 2 is the structured flowchart that digital-to-analogue of the present invention is mixed the LED drive circuit of light modulation.

Fig. 3 is the schematic diagram of the dimming control unit in the embodiment of the present invention 1.

Fig. 4 is the schematic diagram of peak current detection sampling unit circuit in the embodiment of the present invention 1.

Fig. 5 is the schematic diagram of the constant turn-off time control unit circuit in the embodiment of the present invention 1.

Fig. 6 is the schematic diagram of the peak current detection sampling unit circuit in the embodiment of the present invention 2.

Fig. 7 is the schematic diagram of the constant turn-off time control unit circuit in the embodiment of the present invention 3.

Below in conjunction with accompanying drawing and embodiment, the invention will be further described.

Embodiment

Embodiment 1:

With reference to Fig. 2, Fig. 3, digital-to-analogue of the present invention is mixed the LED drive circuit of light modulation, comprises dimming control unit 1, peak current detection sampling unit 2 and constant turn-off time control unit 3.

Described dimming control unit 1, comprises analog light-adjusting circuit 11 and digital light-adjusting circuit 12, has two input a, b and three output c, d, e; Wherein, first input end a and the second input b input driving voltage V of connecting analog light adjusting circuit 11 respectively _aDJ1enable control signal V with the input of digital light-adjusting circuit 12 _eN, dimming control unit 1 is by changing V _aDJ1and V _eNsimulate respectively light modulation and digital dimming; The first output c connects the enable signal V of the output of the second Schmidt trigger in digital light-adjusting circuit 12 _eN2; The second output d connects the enable signal V of the first Schmidt trigger output in digital light-adjusting circuit 12 _eN1; Current peak detection threshold V in the 3rd output e connecting analog light adjusting circuit 11 _cST1, it is to pass through V _aDJ1change change.

Described peak current detection sampling unit 2, is provided with four input f, g, j, k and an output h; Wherein, the output current peak threshold voltage V of analog light-adjusting circuit 11 in first input end f and dimming control unit 1 _cST1connect; The enable signal V of digital light-adjusting circuit 12 in the second input g and dimming control unit 1 _eN1connect, for realizing the control of internal components operating state; The 3rd input j and four-input terminal k respectively with the first resistance R ₁output V ₁, circuit input V _iNconnect, for by the first resistance R ₁on pressure drop V _sNSwith peak current detection threshold value V _cSTcompare the detection that realizes peak current; Output h is connected with the input in constant turn-off time control unit 3.

Described constant turn-off time control unit 3, is provided with four input m, n, o, p and an output q; Wherein, the output signal V in first input end m and peak current detection sampling unit 2 ₃connect; The second input n and the 3rd input o respectively with dimming control unit 1 in the enable signal V of output of digital light-adjusting circuit _eN1, V _eN2connect, control for unlatching and the shutoff of internal components; The driving voltage V of four-input terminal p and amplifier _aDJ2connect, for regulating the 4th capacitor C ₄charge and discharge, thereby realize PMOS pipe Q ₁the control of turn-off time; Output q and output voltage V ₂connect.

DC power supply first capacitor C in parallel of input ₁after obtain input voltage V _iN, the first resistance R ₁the input voltage V at two ends _iNwith voltage V ₁be connected to peak current detection unit 2; The output voltage V that constant turn-off time control unit 3 is exported ₂be connected to a driving Driver, for power ratio control switching tube Q ₁turn-on and turn-off; Power switch pipe Q ₁with Schottky diode D ₁with the second capacitor C ₂parallel connection, and with the first inductance L ₁series connection.

As power switch pipe Q ₁when pipe conducting, Schottky diode D ₁in reverse-biased, DC power supply is to the first inductance L ₁charging, inductive current is linear to be increased, until to a certain degree, the electric current on LED is only provided by DC power supply, now DC power supply starts the second capacitor C ₂charging, in the time peak current being detected, power switch pipe Q ₁turn-off; Then due to the first inductance L ₁in electric current can not suddenly change, it can produce and change contrary induced electromotive force with inductive current and stop reducing of inductive current, and makes diode D ₁afterflow is carried out in conducting.This circuit of having applied just BUCK type DC-DC converter is opened up benefit structural principle, finally makes output voltage V _oUTstable, thus make to flow through the current stabilization on LED.

What the high voltage PMOS of the following stated and high pressure NMOS pipe were generally used bears pressure drop between 5V to 80V.

With reference to Fig. 3, dimming control unit 1 comprises analog light-adjusting circuit 11 and digital light-adjusting circuit 12.Wherein, analog light-adjusting circuit 11 comprises that amplifier 101, NMOS manage M ₁₀₁, the second resistance R ₂, the 3rd resistance R ₃with current source I _s1; Digital light-adjusting circuit 12 comprises that the first Schmidt trigger 102 and the second Schmidt trigger 104, inverter 103, PMOS manage M ₁₀₂, PMOS manages M ₁₀₄, NMOS manages M ₁₀₃, NMOS manages M ₁₀₅with the 3rd capacitor C ₃.Wherein:

Described amplifier 101, its in-phase input end is connected to driving voltage V _aDJ1, and by the 3rd resistance R ₃ground connection; Its end of oppisite phase is by the second resistance R ₂ground connection; Its output is connected to NMOS pipe M ₁₀₁grid; NMOS manages M ₁₀₁drain electrode be connected to the input threshold voltage V of peak current detection sampling unit 2 _cST1, its source class is by the second resistance R ₂ground connection; Current source I _s1input access internal electric source V _dD, its output is by the 3rd resistance R ₃receive ground, and access V _aDJ1; Due to R ₂=5R ₅, therefore,

$V_{\mathrm{CST}}=\frac{R_2}{R_5}{V}_{\mathrm{<figure-callout\; id="1"\; label="ADJ"\; filenames="HDA0000460524900000021.png,HDA0000460524900000031.png"\; state="\{\{state\}\}">ADJ</figure-callout>}1}=\frac{V_{\mathrm{ADJ}1}}{5}---\left(1\right)$

Wherein, V _iN-V _cST=V _cST1; V _cSTit is the 5th resistance R ₅on pressure drop; V _cST1for peak current detection threshold value.

Described the first Schmidt trigger 102, its input is connected on NMOS pipe M ₁₀₃drain electrode, be connected on the 3rd capacitor C simultaneously ₃positive pole, its output is connected on the input of inverter 103, accesses enable signal V simultaneously _eN1; Its power end meets respectively internal electric source V _dDand ground.

Described the second Schmidt trigger 104, its input is connected on the output of inverter 103, connects PMOS pipe M simultaneously ₁₀₄with NMOS pipe M ₁₀₅drain electrode; Its output is connected to the enable signal V of an input of NAND gate 306 in constant turn-off time control unit 3 _eN2on; Its power end is connected on respectively internal electric source V _dDand on the ground.

Described inverter 103, its input is connected on the output of Schmidt trigger 102, and its output is connected to PMOS pipe M ₁₀₄grid on; PMOS manages M ₁₀₂, its source electrode connects internal electric source V _dD, its grid directly arrives ground; PMOS manages M ₁₀₄, its source electrode access internal electric source V _dD; NMOS manages M ₁₀₃, its grid connection enables input signal V _eN, its source class ground connection; NMOS manages M ₁₀₅, its source class ground connection, its grid access enables input signal V _eN; The 3rd capacitor C ₃, its minus earth.

With reference to figure 4, the peak current detection sampling unit 2 of the present embodiment, comprises inverter 201, current source I _s2, the 4th resistance R ₄, the 5th resistance R ₅, the 6th resistance R ₆, the 7th resistance R ₇, high voltage PMOS pipe M ₂₀₃, high voltage PMOS pipe M ₂₀₅, high pressure NMOS pipe M ₂₀₄, high pressure NMOS pipe M ₂₀₆, NMOS manages M ₂₀₁, NMOS manages M ₂₀₂, NMOS manages M ₂₀₇, NMOS manages M ₂₀₈, NMOS manages M ₂₀₉, NMOS manages M ₂₁₀, NMOS manages M ₂₁₁, NMOS manages M ₂₁₂, NMOS manages M ₂₁₅, NMOS manages M ₂₂₀, NMOS manages M ₂₂₁, NMOS manages M ₂₂₃, NMOS manages M ₂₂₄, NMOS manages M ₂₂₆, PMOS manages M ₂₁₃, PMOS manages M ₂₁₄, PMOS manages M ₂₁₆, PMOS manages M ₂₁₇, PMOS manages M ₂₁₈, PMOS manages M ₂₁₉, PMOS manages M ₂₂₂with PMOS pipe M ₂₂₅.Wherein:

Described inverter 201, its input connection enables input signal V _eN1, its output termination NMOS pipe M ₂₀₇;

Described current source I _s2, its input termination internal electric source V _dD, its output is connected on NMOS pipe M ₂₀₇and M ₂₀₈drain electrode on, be connected on NMOS pipe M simultaneously ₂₀₈and M ₂₀₉grid on; Described NMOS pipe M ₂₀₈, M ₂₀₉, M ₂₁₀, M ₂₁₁, M ₂₁₂structure current mirror in a row, NMOS manages M ₂₀₈, M ₂₀₉, M ₂₁₀, M ₂₁₁, M ₂₁₂grid be all connected to NMOS pipe M ₂₀₈grid on, source electrode is ground connection all; NMOS manages M ₂₀₈, M ₂₀₉, M ₂₁₀, M ₂₁₁, M ₂₁₂the size of upper current flowing is calculated according to each NMOS pipe size:

${\mathrm{<figure-callout\; id="2"\; label="I\; D"\; filenames="HDA0000460524900000022.png"\; state="\{\{state\}\}">I</figure-callout>}}_D=I_{S2}\&times;\frac{{\left(\frac{W}{L}\right)}_{M209}}{{\left(\frac{W}{L}\right)}_{M208}}---\left(2\right)$

${\mathrm{<figure-callout\; id="3"\; label="I\; D"\; filenames="HDA0000460524900000012.png,HDA0000460524900000031.png"\; state="\{\{state\}\}">I</figure-callout>}}_D=I_{S2}\&times;\frac{{\left(\frac{W}{L}\right)}_{M210}}{{\left(\frac{W}{L}\right)}_{M208}}---\left(3\right)$

$I_{D4}=I_{S2}\&times;\frac{{\left(\frac{W}{L}\right)}_{M211}}{{\left(\frac{W}{L}\right)}_{M208}}---\left(4\right)$

$I_{D5}=I_{S2}\&times;\frac{{\left(\frac{W}{L}\right)}_{M212}}{{\left(\frac{W}{L}\right)}_{M208}}---\left(5\right)$

Described NMOS pipe M ₂₀₉drain electrode be connected on the NMOS pipe M of composition differential pair ₂₀₁, M ₂₀₂source electrode on; Wherein NMOS pipe M ₂₁₀drain electrode be connected on high pressure NMOS pipe M ₂₀₄source electrode on; NMOS manages M ₂₁₁drain electrode be connected on high pressure NMOS pipe M ₂₀₆source electrode on, NMOS manages M ₂₁₂drain electrode be connected on PMOS pipe M ₂₁₃drain electrode on.

Described NMOS pipe M ₂₀₁and M ₂₀₂form differential pair, their drain electrode is respectively by the 6th resistance R ₆with the 7th resistance R ₇be connected on input voltage V _iNupper, their grid is respectively by the 4th resistance R ₄with the 5th resistance R ₅be connected to input voltage V ₁and V _iNon.

Described high voltage PMOS pipe M ₂₀₃, M ₂₀₅with NMOS pipe M ₂₀₄, M ₂₀₆drain electrode high-voltage tube, wherein, high voltage PMOS pipe M ₂₀₃, M ₂₀₅source electrode be connected on respectively differential pair NMOS pipe M ₂₀₁, M ₂₀₂drain electrode on, their drain electrode is connected to NMOS pipe M ₂₀₄, M ₂₀₆drain electrode on, their grid all connects input voltage V _b1; High pressure NMOS pipe M ₂₀₄, M ₂₀₆grid all connect input voltage V _b2, their source class is connected to the NMOS pipe M of composition differential pair ₂₁₉, M ₂₁₈grid on, the input of serving as this differential pair.

Described PMOS pipe M ₂₁₃, M ₂₁₆form current mirror, their source electrode is all received internal electric source V _dD, PMOS manages M ₂₁₆drain electrode be connected to the PMOS pipe M of composition differential pair ₂₁₈, M ₂₁₉source electrode; PMOS manages M ₂₁₇source electrode connects internal electric source V _dD, grid connects enable signal V _eN1, drain electrode connects PMOS pipe M ₂₁₃drain electrode.

Described PMOS pipe M ₂₁₄and M ₂₂₂form current mirror, their source electrode meets internal electric source V _dD, wherein PMOS pipe M ₂₁₄drain electrode meet NMOS pipe M ₂₁₅drain electrode, PMOS manages M ₂₂₂drain electrode meet NMOS pipe M ₂₂₃drain electrode; Described NMOS pipe M ₂₁₅and M ₂₂₀also form current mirror, all ground connection of its source class, wherein NMOS pipe M ₂₂₀drain electrode be connected on the PMOS pipe M of composition differential pair ₂₁₈drain electrode on; Described NMOS pipe M ₂₂₁and M ₂₂₃also form current mirror, all ground connection of their source electrode, NMOS manages M ₂₂₁drain electrode be connected on the PMOS pipe M of composition differential pair ₂₁₉drain electrode on.

Described NMOS pipe M ₂₂₄, its grid connects enable signal V _eN1, for controlling its on off state, its drain electrode is connected on NMOS pipe M ₂₂₃drain electrode on, source ground; Described PMOS pipe M ₂₂₅with NMOS pipe M ₂₂₆form inverter, the input of this inverter is connected on NMOS pipe M ₂₂₃drain electrode on, its output termination output signal V ₃, wherein PMOS pipe M ₂₂₅source electrode meet internal electric source V _dD, NMOS manages M ₂₂₆source ground.

With reference to figure 5, the constant turn-off time control unit 3 of the present embodiment, comprises amplifier 301, comparator 302, rest-set flip-flop 303, inverter 304, inverter 305, NAND gate 306, the 4th capacitor C ₄, the 8th resistance R ₈, PMOS manages M ₃₀₁, PMOS manages M ₃₀₂, PMOS manages M ₃₀₃with PMOS pipe M ₃₀₄, NMOS manages M ₃₀₅with NMOS pipe M ₃₀₆.Wherein:

Described amplifier 301, its in-phase input end connects input voltage V _aDJ2, reverse input end is by the 8th resistance R ₈ground connection, its output termination NMOS pipe M ₃₀₅grid; Described comparator 302, its in-phase input end connects reference voltage V _rEF, its anti-phase termination PMOS pipe M ₃₀₃drain electrode, the reset terminal R of its output termination rest-set flip-flop; Described rest-set flip-flop is made up of two NAND gate, and it is put number end S and is connected on the output of inverter 304, and its output is connected on the input of inverter 305; Described inverter 304, the output signal V of its input termination peak current detection sampling unit 2 ₃, described inverter 305, in an input of its output termination NAND gate 306; Another input termination enable signal V of described NAND gate 306 _eN2, its output termination output voltage V ₂.

Described PMOS pipe M ₃₀₁, M ₃₀₂, M ₃₀₃and M ₃₀₄form current mirror, wherein, PMOS manages M ₃₀₁and M ₃₀₂source electrode be connected on internal electric source V _dDupper, and drain electrode is connected on respectively PMOS pipe M ₃₀₄and M ₃₀₃source electrode on; By getting identical pipe sizing, obtain current relationship and be: I _d6=i _d7=i _d8=i _d9.

Described PMOS pipe M ₃₀₄drain electrode connect NMOS pipe M ₃₀₅drain electrode, PMOS manages M ₃₀₃drain electrode by the 4th capacitor C ₄ground connection; Described NMOS pipe M ₃₀₅source electrode by the 8th resistance R ₈ground connection, NMOS manages M ₃₀₆grid meet the output signal V of peak current detection sampling unit 2 ₃, its drain electrode connects the inverting input of comparator 302, source ground.

The LED drive circuit of the present embodiment, its turn-off time T _oFFconstant, mainly by the 8th resistance R ₈, the 4th capacitor C ₄, a constant output voltage V _aDJ2regulate in advance.T _oFFinitial time, the 4th capacitor C ₄on voltage be zero, current mirror will provide electric charge to electric capacity subsequently, electric capacity start charging, charge constant is by R ₈and C ₄determine.When the 4th capacitor C ₄voltage (the V at two ends _cOFF) charge to and reference voltage V _rEFwhile equating, the turn-off time finishes, capacitor discharge to zero.Power switch pipe Q ₁turn-off time T _oFFcomputing formula be:

$T_{\mathrm{OFF}}=\frac{C_4{V}_{\mathrm{REF}}{R}_8}{V_{\mathrm{ADJ}2}}---\left(6\right)$

In addition, this circuit is subject to the control of peak current detection sampling unit 2, when the first resistance R ₁when peak current detected, system ON time T _oNfinish turn-off time T _oFFstart.Once can know and peak current be detected, output signal V by analysis ₃for high level, by this output signal V ₃be connected to the NMOS pipe M in turn-off time control circuit ₃₀₆grid, guarantee at T _oFFthe initial time of time period, the 4th capacitor C ₄on electric charge be zero.

Embodiment 2:

Identical with embodiment 1 of the dimming control unit 1 of the present embodiment and constant turn-off time control unit 3.

With reference to Fig. 6, the peak current detection sampling unit 2 of the present embodiment comprises inverter 201, the 4th resistance R ₄, the 5th resistance R ₅, PMOS manages M ₂₀₁, PMOS manages M ₂₀₂, PMOS manages M ₂₀₅, PMOS manages M ₂₀₆, PMOS manages M ₂₀₉, PMOS manages M ₂₁₂, PMOS manages M ₂₁₃, NMOS manages M ₂₀₃, NMOS manages M ₂₀₄, NMOS manages M ₂₀₇, NMOS manages M ₂₀₈, NMOS manages M ₂₁₀, NMOS manages M ₂₁₁, NMOS manages M ₂₁₄with NMOS pipe M ₂₁₅.Wherein:

Described inverter 201, its input connects PMOS pipe M ₂₁₃drain electrode, output connects in constant turn-off time control unit 3 NMOS pipe M ₃₀₆grid, for controlling its switch.Described PMOS pipe M ₂₁₂and M ₂₁₃form current mirror, their source electrode all connects internal electric source V _dD, PMOS manages M ₂₁₂drain electrode connect NMOS pipe M ₂₁₄drain electrode, PMOS manages M ₂₁₃drain electrode connect NMOS pipe M ₂₁₅drain electrode.

Described NMOS pipe M ₂₁₅, its grid connects high pressure NMOS pipe M ₂₁₀source class, its source ground; NMOS manages M ₂₁₄, M ₂₁₁, M ₂₀₈grid be all connected on NMOS pipe M ₂₀₇grid on, all ground connection of their source electrode, wherein NMOS pipe M ₂₁₁drain electrode meet high pressure NMOS pipe M ₂₁₀source electrode, NMOS manages M ₂₀₈drain electrode connect high pressure NMOS pipe M ₂₀₆source electrode, NMOS manages M ₂₀₇drain electrode connect high pressure NMOS pipe M ₂₀₅source electrode; High pressure NMOS pipe M ₂₁₀grid connect internal electric source V _dD, its drain electrode connects high voltage PMOS pipe M ₂₀₉drain electrode; Described PMOS pipe M ₂₀₉source electrode connect input voltage V _iN, its grid connects PMOS pipe M ₂₀₂with high pressure NMOS pipe M ₂₀₄drain electrode.

Described PMOS pipe M ₂₀₁and M ₂₀₂form current mirror, their source electrode connects input voltage V _iN, wherein PMOS pipe M ₂₀₁, M ₂₀₂drain electrode connect respectively NMOS pipe M ₂₀₃, M ₂₀₄drain electrode; Described high pressure NMOS pipe M ₂₀₄, its grid connects the output threshold voltage V of analog light-adjusting circuit in dimming control unit 1 _cST, and by the 5th resistance R ₅connect input voltage V _iN, its source electrode and NMOS pipe M ₂₀₃source electrode be all connected to high pressure NMOS pipe M ₂₀₆drain electrode; Described NMOS pipe M ₂₀₃, its grid is by the 4th resistance R ₄connect input voltage V ₁; Described high pressure NMOS pipe M ₂₀₅and M ₂₀₆form current mirror, wherein NMOS pipe M ₂₀₅drain electrode connect current source I _s2.

Its current relationship is: $I_{D10}=I_{\mathrm{<figure-callout\; id="2"\; label="S"\; filenames="HDA0000460524900000022.png"\; state="\{\{state\}\}">S</figure-callout>}2}\&times;\frac{{\left(\frac{W}{L}\right)}_{M206}}{{\left(\frac{W}{L}\right)}_{M205}}---\left(7\right)$

Wherein, I _s2for current source current, I _d10for high pressure NMOS pipe M ₂₀₆drain current, the breadth length ratio that W/L is metal-oxide-semiconductor.

In the present embodiment, utilize the first resistance R ₁the differential voltage signal of upper generation detects.By by the first resistance R ₁on pressure drop V _sNSwith current peak detection threshold voltage V _cSTcompare to realize the detection of peak current.The voltage of comparator anode input is V _iN-V _cST, the voltage of negative terminal input is V _iN-V _sNS.Once peak current be detected, i.e. V _sNSbe greater than V _cST, Q ₁turn-off, ON time finishes, now comparator output high level.

V _cSTvalue be the input voltage V by the amplifier in-phase end in dimming control unit 1 _aDJ1voltage decision, amplifier adopts degenerative connected mode, due to R ₂=5R ₅therefore switch NMOS manages M ₁₀₁on the electric current that flows through can be expressed as:

${\mathrm{<figure-callout\; id="1"\; label="I\; D"\; filenames="HDA0000460524900000021.png,HDA0000460524900000031.png"\; state="\{\{state\}\}">I</figure-callout>}}_D=\frac{{\mathrm{<figure-callout\; id="1"\; label="V\; ADJ"\; filenames="HDA0000460524900000021.png,HDA0000460524900000031.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{ADJ}}}{{5R}_5}---\left(8\right)$

Therefore, peak current detection threshold value V _cSTbe expressed as:

$V_{\mathrm{CST}}={\mathrm{<figure-callout\; id="1"\; label="I\; D"\; filenames="HDA0000460524900000021.png,HDA0000460524900000031.png"\; state="\{\{state\}\}">I</figure-callout>}}_D\&times;R_5=\frac{{\mathrm{<figure-callout\; id="1"\; label="V\; ADJ"\; filenames="HDA0000460524900000021.png,HDA0000460524900000031.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{ADJ}}}{5}---\left(9\right)$

In addition, this circuit also provides two kinds to regulate detection threshold voltage V _cSTmethod, be all by change V _aDJ1magnitude of voltage is realized.

1, V _aDJ1disconnect, directly by reference voltage V _rEFbe provided as driving voltage.

$V_{\mathrm{CST}}=\frac{{\mathrm{<figure-callout\; id="1"\; label="V\; ADJ"\; filenames="HDA0000460524900000021.png,HDA0000460524900000031.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{ADJ}}}{{5R}_4}\&times;R_4=\frac{{\mathrm{<figure-callout\; id="1"\; label="V\; ADJ"\; filenames="HDA0000460524900000021.png,HDA0000460524900000031.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{ADJ}}}{5}=\frac{1.20V}{5}=240\mathrm{mV}---\left(10\right)$

The V of 0～1.20V is directly provided _aDJ1voltage is realized, in this way, and the V setting _cSTvalue between 0～240mV, change.

2, hold in the same way contact resistance R between ground in amplifier ₂realize electric current I _s1can flow through resistance R ₂thereby, produce V _aDJ1voltage, now, V _cSTvoltage can be expressed as:

${V_{\mathrm{CST}}}^{\text{'}}=\frac{{\mathrm{<figure-callout\; id="1"\; label="V\; ADJ"\; filenames="HDA0000460524900000021.png,HDA0000460524900000031.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{ADJ}}}{5}=\frac{{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="HDA0000460524900000022.png"\; state="\{\{state\}\}">R</figure-callout>}}_2\&times;I_{S1}}{5}---\left(11\right)$

The peak current detection sampling unit 2 of the LED drive circuit of above two embodiment can be found out, the core design of this element is comparator, the conversion speed of comparator directly affects the order of accuarcy of system ON time and turn-off time, and then can affect the working point of system, therefore require designed comparator should there is fast as far as possible conversion speed.Here adopt two-stage comparator circuit to realize, particular circuit configurations as shown in Figure 6.

The DC-DC transducer that the present embodiment adopts simultaneously, by comparing the first resistance R ₁on pressure drop V _sNSpeak current detection threshold voltage V with comparator circuit _cSTtrigger main switch Q ₁shutoff, and do not need error amplifier and feedback network, therefore, compared with traditional voltage mode control, there is faster response speed.

Embodiment 3:

The dimming control unit 1 of the present embodiment and peak current detection sampling unit 2 are identical with embodiment's 1.

With reference to Fig. 7, the constant turn-off time control unit 3 of the present embodiment comprises comparator 301, rest-set flip-flop 302, inverter 303 and inverter 304, NAND gate 305, the 4th capacitor C ₄, the 8th resistance R ₈with NMOS pipe M ₃₀₁.Wherein:

Described comparator 301, its in-phase input end connects reference voltage V _rEF, its inverting input connects NMOS pipe M ₃₀₁drain electrode, and by the 8th resistance R ₈be connected to output voltage V _aDJ2upper or by the 4th capacitor C ₄ground connection, the reset terminal R of its output termination rest-set flip-flop; Described rest-set flip-flop is made up of two NAND gate, and it is put number end S and is connected on the output of inverter 303, and its output is connected on the input of inverter 304; Described inverter 303, the output signal V of its input termination peak current detection sampling unit 2 ₃; Described inverter 304, in an input of its output termination NAND gate 305; Another input termination enable signal V of described NAND gate 305 _eN2, its output termination output voltage V ₂; Described NMOS pipe M ₃₀₁, its grid connects the output signal V of peak current detection sampling unit 2 ₃, its source ground.

The LED drive circuit of the present embodiment, its turn-off time T _oFFconstant, mainly by the 8th resistance R ₈, the 4th capacitor C ₄, output voltage V _aDJ2regulate in advance.Due to circuit adopt be constant current drive mode, I _lEDcan well control, so output voltage V _aDJ2will be a constant value, can not change with the variation of input voltage and temperature.

T _oFFthe initial time in moment, the 4th capacitor C ₄on voltage be zero, output voltage V subsequently _aDJ2to provide electric charge to electric capacity, electric capacity starts charging, and charge constant is by R ₈and C ₄determine.As the voltage (V at electric capacity two ends _cOFF) charge to and reference voltage V _rEFwhile equating, the turn-off time finishes, capacitor discharge to zero.T _oFFcomputing formula be:

${T_{\mathrm{OFF}}}^{\text{'}}={-R}_8\&times;C_4\&times;\ln (1-\frac{V_{\mathrm{REF}}}{V_{\mathrm{ADJ}2}})---\left(12\right)$

By the turn-off time T in above-described embodiment 1 and embodiment 3 _oFFand T _oFF＇ can find out: it is by the 8th resistance R ₈, the 4th capacitor C ₄with a constant voltage V _aDJ2determine, once therefore determine their parameter value, the turn-off time of circuit is invariable.Meanwhile, the constant turn-off time control model LED drive circuit proposing in the present invention is without external compensating network, and loop compensation is succinct, is easy to realize, and it is convenient to control; And switching frequency is only with V _iNincrease and increase, the stability of a system is good.

Below be only three preferred example of the present invention, do not form any limitation of the invention, obviously, under design of the present invention, can carry out different changes and improvement to its circuit, but these are all at the row of protection of the present invention.

Claims (7)

1. A digital-analog hybrid dimming LED drive circuit, characterized in that it comprises the following units: The dimming control unit (1) includes an analog dimming circuit (11) and a digital dimming circuit (12), wherein the analog dimming circuit (11) is used to receive the driving voltage V _ADJ1 and adjust the driving voltage V _ADJ1 voltage value to output the peak current detection threshold voltage V _CST1 , and input to the peak current detection sampling unit (2); the digital dimming circuit (12) is used to receive the enable signal V _EN , and when the enable signal Under the control of V _EN , the enable signal V EN1 is output to the peak current detection sampling unit (2) and the constant off-time control _unit (3), and the enable signal V _EN2 is output to the constant off-time control unit (3); The peak current detection sampling unit (2) is used for receiving the peak current detection threshold voltage V _CST1 sent by the receiving analog dimming circuit (11) in the dimming control unit (1) and the output signal sent by the digital dimming circuit (12). Enable signal V _EN1 ; and under the control of enable signal V _EN1 , compare the input voltage V _IN and the voltage V ₁ obtained by the input voltage V _IN through the voltage drop V _SNS with the peak detection threshold voltage V _CST1 to achieve the peak value detection of the current, and inputting the output signal V ₃ into the constant off-time control unit (3); Constant off-time control unit (3): used to receive the enable signal V _EN1 and enable signal V _EN2 sent by the digital dimming circuit (12) in the dimming control unit (1), and simultaneously receive the peak current detection sampling unit ( 2) The output signal V ₃ is sent; and under the control of the enable signal V _EN1 and the enable signal V _EN2 , when the peak current is detected, the input voltage V _ADJ2 is adjusted to obtain an output voltage V ₂ , and the output voltage V ₂ delivered to the power switch tube _Q1 ; Power switch tube Q ₁ : used to receive the output voltage V ₂ sent by the constant off-time control unit (3), and generate a constant off-time T _OFF according to the output voltage V ₂ ; The input DC power supply is connected in parallel with the first capacitor C ₁ to obtain the input voltage V _IN , the input voltage V _IN and the voltage V ₁ at both ends of the first resistor R ₁ are connected to the peak current detection unit (2); the constant off-time control unit (3 ) output voltage V ₂ is connected to a driver Driver for controlling the turn-on and turn-off of the power switch tube Q ₁ ; the power switch tube Q ₁ is connected in parallel with the Schottky diode D ₁ and the second capacitor C ₂ , and is connected with The first inductor _L1 is connected in series. 2. The digital-analog hybrid dimming LED drive circuit according to claim 1, characterized in that the dimming control unit (1) comprises an analog dimming circuit (11) and a digital dimming circuit (12). 3. The digital-analog hybrid dimming LED drive circuit according to claim 2, characterized in that the analog dimming circuit (11) includes an amplifier (101), an NMOS transistor M ₁₀₁ , a second resistor R ₂ , a second Three resistors R ₃ and a current source _IS1 ; the digital dimming circuit (12) includes a first Schmitt trigger (102) and a second Schmitt trigger (104), an inverter (103), a PMOS Tube M ₁₀₂ , PMOS tube M ₁₀₄ , NMOS tube M ₁₀₃ , NMOS tube M ₁₀₅ and the third capacitor C ₃ ; wherein: The amplifier (101), its non-inverting input terminal is connected to the driving voltage V _ADJ1 , and grounded through the third resistor _R3 ; its inverting terminal is grounded through the second resistor _R2 ; its output terminal is connected to the gate of the NMOS transistor _M101 The drain of the NMOS transistor M ₁₀₁ is connected to the input threshold voltage V _CST1 of the peak current detection sampling unit (2), and its source is grounded through the second resistor R ₂ ; the input terminal of the current source I _S1 is connected to the internal power supply V _DD , Its output terminal is connected to the ground through the third resistor _R3 , and connected to V _ADJ1 ; The input terminal of the first Schmitt trigger (102) is connected to the drain of the NMOS transistor M ₁₀₃ , and at the same time connected to the anode of the third capacitor _C3 , and its output terminal is connected to the input terminal of the inverter (103) , and at the same time access the enable signal V _EN1 ; its power supply terminals are respectively connected to the internal power supply V _DD and ground; The input terminal of the second Schmitt trigger (104) is connected to the output terminal of the inverter (103), and the drains of the PMOS transistor M ₁₀₄ and the NMOS transistor M ₁₀₅ are connected at the same time; its output terminal is connected to a constant On the enable signal V _EN2 of an input terminal of the NAND gate (306) in the off-time control unit (3); its power supply terminals are respectively connected to the internal power supply V _DD and ground; The input of the inverter (103) is connected to the output of the Schmitt trigger (102), and its output is connected to the gate of the PMOS transistor M ₁₀₄ ; the source of the PMOS transistor M ₁₀₂ is connected to The internal power supply V _DD , whose gate is directly connected to the ground; the PMOS transistor M ₁₀₄ , whose source is connected to the internal power supply V _DD ; the NMOS transistor M ₁₀₃ , whose gate is connected to the enable input signal V _EN , and whose source is grounded; the NMOS transistor M 104 The source of M ₁₀₅ is grounded, and the gate is connected to the enable input signal V _EN ; the negative pole of the third capacitor C ₃ is grounded. 4. The digital-analog hybrid dimming LED drive circuit according to claim 1, characterized in that the peak current detection sampling unit (2) includes an inverter (201), a current source I _S2 , a fourth resistor R ₄ , fifth resistor R ₅ , sixth resistor R ₆ , seventh resistor R ₇ , high voltage PMOS transistor M ₂₀₃ , high voltage PMOS transistor M ₂₀₅ , high voltage NMOS transistor M ₂₀₄ , high voltage NMOS transistor M ₂₀₆ , NMOS transistor M ₂₀₁ , NMOS tube M ₂₀₂ , NMOS tube M ₂₀₇ , NMOS tube M ₂₀₈ , NMOS tube M ₂₀₉ , NMOS tube M ₂₁₀ , NMOS tube M ₂₁₁ , NMOS tube M ₂₁₂ , NMOS tube M ₂₁₅ , NMOS tube M ₂₂₀ , NMOS tube M ₂₂₁ , NMOS tube M ₂₂₃ , NMOS tube M ₂₂₄ , NMOS tube M ₂₂₆ , PMOS tube M _{213 , PMOS tube M 214} , PMOS tube M ₂₁₆ , PMOS tube M ₂₁₇ , PMOS tube M ₂₁₈ , PMOS tube _{M 219 ,} PMOS tube M ₂₂₂ and PMOS tube M ₂₂₅ ; wherein: The input terminal of the inverter (201) is connected to the enable input signal V _EN1 , and its output terminal is connected to the NMOS transistor M ₂₀₇ ; The input terminal of the current source _IS2 is connected to the internal power supply V _DD , and its output terminal is connected to the drains of the NMOS transistors M ₂₀₇ and M ₂₀₈ , and connected to the gates of the NMOS transistors M ₂₀₈ and M ₂₀₉ ; NMOS transistors M ₂₀₈ , M ₂₀₉ , M ₂₁₀ , M ₂₁₁ , and M ₂₁₂ form a row of current mirrors, and the gates of NMOS transistors M ₂₀₈ , M ₂₀₉ , M ₂₁₀ , M ₂₁₁ , and M ₂₁₂ are all connected to the gate of NMOS transistor M ₂₀₈ Both poles and sources are grounded; The drain of the NMOS transistor M ₂₀₉ is connected to the sources of the NMOS transistors M ₂₀₁ and M ₂₀₂ forming a differential pair; the drain of the NMOS transistor M ₂₁₀ is connected to the source of the high-voltage NMOS transistor M ₂₀₄ ; the NMOS transistor M The drain of ₂₁₁ is connected to the source of the high-voltage NMOS transistor M ₂₀₆ , and the drain of the NMOS transistor M ₂₁₂ is connected to the drain of the PMOS transistor M ₂₁₃ ; The NMOS transistors _M201 and _M202 form a differential pair, their drains are respectively connected to the input voltage V _IN through the sixth resistor _R6 and the seventh resistor _R7 , and their gates are respectively connected through the fourth resistor R ₄ and the fifth resistor R ₅ are connected to the input voltage V ₁ and V _IN ; The high-voltage PMOS transistors M ₂₀₃ and M ₂₀₅ and the NMOS transistors M ₂₀₄ and M ₂₀₆ are high-voltage drain transistors, wherein the sources of the high-voltage PMOS transistors M ₂₀₃ and M ₂₀₅ are connected to the differential pair of NMOS transistors M ₂₀₁ and M ₂₀₂ respectively. On the drains, their drains are respectively connected to the drains of the NMOS transistors M ₂₀₄ and M ₂₀₆ , and their gates are connected to the input voltage V _B1 ; the gates of the high-voltage NMOS transistors M ₂₀₄ and M ₂₀₆ are connected to the input voltage V _B2 , their sources are respectively connected to the gates of NMOS transistors M ₂₁₉ and M ₂₁₈ forming a differential pair; The PMOS transistors M ₂₁₃ and M ₂₁₆ constitute a current mirror, their sources are connected to the internal power supply V _DD , and the drain of the PMOS transistor M ₂₁₆ is connected to the sources of the PMOS transistors M ₂₁₈ and M ₂₁₉ that form a differential pair; The source of the tube M ₂₁₇ is connected to the internal power supply V _DD , the gate is connected to the enable signal V _EN1 , and the drain is connected to the drain of the PMOS tube M ₂₁₃ ; The PMOS transistors M ₂₁₄ and M ₂₂₂ form a current mirror, and their sources are connected to the internal power supply V _DD , wherein the drain of the PMOS transistor M ₂₁₄ is connected to the drain of the NMOS transistor M ₂₁₅ , and the drain of the PMOS transistor M ₂₂₂ is connected to the NMOS transistor The drain of M ₂₂₃ ; the NMOS transistors M ₂₁₅ and M ₂₂₀ also constitute a current mirror, and their sources are all grounded, wherein the drain of the NMOS transistor M ₂₂₀ is connected to the drain of the PMOS transistor M ₂₁₈ forming a differential pair; The above-mentioned NMOS transistors M ₂₂₁ and M ₂₂₃ also constitute a current mirror, their sources are all grounded, and the drain of the NMOS transistor M ₂₂₁ is connected to the drain of the PMOS transistor M ₂₁₉ that forms a differential pair; The gate of the NMOS transistor M ₂₂₄ is connected to the enable signal V _EN1 for controlling its switching state, its drain is connected to the drain of the NMOS transistor M ₂₂₃ , and its source is grounded; the PMOS transistor M ₂₂₅ and the NMOS The tube M ₂₂₆ constitutes an inverter, the input terminal of the inverter is connected to the drain of the NMOS tube M ₂₂₃ , and the output terminal is connected to the output signal V ₃ , wherein the source of the PMOS tube M 225 is connected to the internal power supply V DD , and the NMOS tube M ₂₂₅ is connected to the internal power supply V _DD . The source of tube M ₂₂₆ is grounded. 5. The digital-analog hybrid dimming LED drive circuit according to claim 1, characterized in that the constant off-time control unit (3) includes an amplifier (301), a comparator (302), an RS flip-flop (303), inverter (304), inverter (305), NAND gate (306), fourth capacitor C ₄ , eighth resistor R ₈ , PMOS transistor M ₃₀₁ , PMOS transistor M ₃₀₂ , PMOS transistor M ₃₀₃ and PMOS tube M ₃₀₄ , NMOS tube M ₃₀₅ and NMOS tube M ₃₀₆ ; wherein: In the amplifier (301), its non-inverting input terminal is connected to the input voltage V _ADJ2 , its inverting input terminal is grounded through the eighth resistor _R8 , and its output terminal is connected to the gate of the NMOS transistor M ₃₀₅ ; the comparator (302), its The non-inverting input terminal is connected to the reference voltage V _REF , its inverting terminal is connected to the drain of the PMOS transistor _M303 , and its output terminal is connected to the reset terminal R of the RS flip-flop; the RS flip-flop is composed of two NAND gates, and its set The terminal S is connected to the output terminal of the inverter (304), and its output terminal is connected to the input terminal of the inverter (305); the input terminal of the inverter (304) is connected to the peak current detection sampling unit ( 2) the output signal V ₃ , the output terminal of the inverter (305) is connected to one input of the NAND gate (306); the other input terminal of the NAND gate (306) is connected to the enabling signal V _EN2 , whose output terminal is connected to the output voltage V ₂ ; The PMOS transistors M ₃₀₁ , M ₃₀₂ , M ₃₀₃ and M ₃₀₄ form a current mirror, wherein the sources of the PMOS transistors M ₃₀₁ and M ₃₀₂ are connected to the internal power supply V _DD , and the drains are respectively connected to the PMOS transistors M ₃₀₄ and On the source of M ₃₀₃ ; by taking the same tube size, the current relationship is: I _D6= I _D7= I _D8= I _D9 ; The drain of the PMOS transistor _M304 is connected to the drain of the NMOS transistor _M305 , the drain of the PMOS transistor _M303 is grounded through the fourth capacitor _C4 ; the source of the NMOS transistor _M305 is grounded through the eighth resistor _R8 , The gate of the NMOS transistor M ₃₀₆ is connected to the output signal V ₃ of the peak current detection sampling unit ( 2 ), its drain is connected to the inverting input terminal of the comparator ( 302 ), and its source is grounded. 6. The digital-analog hybrid dimming LED drive circuit according to claim 1, characterized in that, the peak current detection sampling unit (2) includes an inverter (201), a fourth resistor R ₄ , a fifth resistor R ₅ , PMOS tube M ₂₀₁ , PMOS tube M ₂₀₂ , PMOS tube M ₂₀₅ , PMOS tube M 206 , PMOS tube M _{209 , PMOS tube M 212 ,} PMOS tube M ₂₁₃ , NMOS tube M ₂₀₃ , NMOS tube M ₂₀₄ , NMOS tube M ₂₀₇ , NMOS tube M ₂₀₈ , NMOS tube M ₂₁₀ , NMOS tube M ₂₁₁ , NMOS tube M ₂₁₄ and NMOS tube M ₂₁₅ ; where: In the inverter (201), its input end is connected to the drain of the PMOS transistor M ₂₁₃ , and its output end is connected to the gate of the NMOS transistor M ₃₀₆ in the constant off-time control unit (3), for controlling its switch; The PMOS transistors M ₂₁₂ and M ₂₁₃ form a current mirror, their sources are connected to the internal power supply V _DD , the drain of the PMOS transistor M ₂₁₂ is connected to the drain of the NMOS transistor M ₂₁₄ , and the drain of the PMOS transistor M ₂₁₃ is connected to the NMOS transistor M ₂₁₅ the drain; The gate of the NMOS transistor M215 is connected to the source of the high-voltage NMOS transistor M210, and its source is grounded; the gates of the NMOS transistors M214, M211, and M208 are all connected to the gate of the NMOS transistor M207, and their sources are all grounded , wherein the drain of the NMOS transistor M211 is connected to the source of the high-voltage NMOS transistor M210, the drain of the NMOS transistor M208 is connected to the source of the high-voltage NMOS transistor M206, the drain of the NMOS transistor M207 is connected to the source of the high-voltage NMOS transistor M205; the high-voltage NMOS transistor The gate of M210 is connected to the internal power supply VDD, and its drain is connected to the drain of the high-voltage PMOS transistor M209; the source of the PMOS transistor M209 is connected to the input voltage VIN, and its gate is connected to the drains of the PMOS transistor M202 and the high-voltage NMOS transistor M204; The PMOS transistors M ₂₀₁ and M ₂₀₂ constitute a current mirror, and their sources are connected to the input voltage V _IN , wherein the drains of the PMOS transistors M ₂₀₁ and M ₂₀₂ are respectively connected to the drains of the NMOS transistors M ₂₀₃ and M ₂₀₄ ; the high voltage The gate of the NMOS transistor _M204 is connected to the output threshold voltage V _CST of the analog dimming circuit in the dimming control unit 1, and is connected to the input voltage V _IN through the fifth resistor _R5 , and its source is connected to the source of the NMOS transistor _M203 Both are connected to the drain of the high-voltage NMOS transistor _M206 ; the gate of the NMOS transistor _M203 is connected to the input voltage _V1 through the fourth resistor _R4 ; the high-voltage NMOS transistors _M205 and _M206 form a current mirror, wherein, The drain of the NMOS transistor M ₂₀₅ is connected to the current source I _S2 . 7. The digital-analog hybrid dimming LED drive circuit according to claim 1, characterized in that, the constant off-time control unit (3) includes a comparator (301), an RS flip-flop (302), an inverting device (303) and inverter (304), NAND gate (305), fourth capacitor C ₄ , eighth resistor R ₈ and NMOS tube M ₃₀₁ ; where: In the comparator (301), its non-inverting input terminal is connected to the reference voltage V _REF , its inverting input terminal is connected to the drain of the NMOS transistor M ₃₀₁ , and is connected to the output voltage V _ADJ2 through the eighth resistor R ₈ or through the fourth Capacitor _C4 is grounded, and its output terminal is connected to the reset terminal R of the RS flip-flop; the RS flip-flop is composed of two NAND gates, and its setting terminal S is connected to the output terminal of the inverter (303), and its output The terminal is connected to the input terminal of the inverter (304); the input terminal of the inverter (303) is connected to the output signal V ₃ of the peak current detection sampling unit (2); the inverter (304), Its output terminal is connected to one input of the NAND gate (305); the other input terminal of the NAND gate (305) is connected to the enabling signal V _EN2 , and its output terminal is connected to the output voltage V ₂ ; the NMOS transistor M ₃₀₁ , the gate of which is connected to the output signal V ₃ of the peak current detection sampling unit (2), and the source of which is grounded.

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