CN205377666U - Direct current - direct current converter circuit - Google Patents

Abstract

The utility model discloses a direct current - direct current converter circuit, produce circuit, current sample unit including fixed TON, diode D1 and diode D2, fixed TON produce the circuit, the VPWM as a result that produces through pulse width modulation comparator PWM and carry out the comparison through clock control signal VREF clocking for control produces synchronizing power pipe Q1 and main switch pipe Q2's drive signal VDH, the current sample unit for sampling synchronizing power pipe Q1's drain voltage VOUT and the pressure differential between the source electrode switching node voltage VSW, and carry sample current's voltage signal VLOAD to the pulse width modulation comparator PWM in. The utility model discloses a feedback and response output's change when the load changes, can be made with the fastest speed to fixed TON mode, has promoted the response speed of loop effectively, adopted valley point current type TON mode, this mode need not the harmonic compensation circuit, has the advantage that the loop control is simplified, the reliability is high.

Description

A DC-DC Converter Circuit

technical field

The utility model belongs to the technical field of electronic circuits and relates to an analog integrated circuit, in particular to a DC-DC converter circuit.

Background technique

With the rapid development of semiconductor technology and the continuous expansion of application fields, booster circuits are widely used in daily life. Traditional boost circuits generally use voltage mode control, in which there is only one voltage feedback path, and pulse width modulation is accomplished by comparing the voltage error signal with a constant harmonic waveform. Not only does current limiting have to be performed separately, but any change in voltage or load must be sensed as a change in output voltage and then corrected by a feedback loop, resulting in a slow response. The voltage-mode output filter adds two poles to the control loop, so designing the error amplifier for compensation requires attenuating the dominant pole at low frequencies, or adding a zero in the compensation to compensate for phase loss. Compensation is further complicated by the fact that the loop gain varies with input voltage.

Now some also use current mode control. Current mode control is a control method with fixed clock on and peak current off. Although it improves the shortcoming of slow voltage mode response, there is still an error between peak current and average current that is difficult to correct. , prone to sub-harmonic oscillation, and poor interactive adjustment performance for multiple output power supplies.

Contents of the invention

The utility model aims at the disadvantages of the above-mentioned slow response speed of the traditional voltage mode and the need to increase harmonic compensation and poor load regulation in the peak current mode, and proposes a DC-DC converter circuit, which can effectively improve the loop response speed and simplify The loop compensation structure is especially suitable for occasions requiring high power and fast response speed.

In order to achieve the above object, the utility model adopts the following technical solutions to solve it:

A DC-DC converter circuit, comprising a synchronous power transistor Q1, a main switch transistor _Q2 , a dead zone control driver and a pulse width modulation comparator PWM, wherein the main switch transistor _Q2 is connected in parallel between the synchronous power transistor Q1 and the ground, The output terminal of the dead zone control driver is connected to the gate of the synchronous power transistor Q1 and the gate of the main switching transistor _Q2 , and the converter circuit also includes a fixed T _ON generating circuit, a current sampling unit, a diode D1 and _a diode D ₂ , where:

Diode D ₁ and diode D ₂ are reversely connected in parallel with the source and drain of the synchronous power transistor Q ₁ ; the fixed T _ON generating circuit includes two input ends a and b, one output end c, and the current sampling unit includes three Input terminals d, e and f, an output terminal g; input terminal a is connected to the output terminal of the pulse width modulation comparator PWM, input terminal b is connected to the clock control signal V _REF , and output terminal c is connected to the dead zone control driver Input terminals; input terminals d, e and f are respectively connected to the source, gate and drain _of the synchronous power transistor Q1, and the output terminal g is connected to the non-inverting terminal of the pulse width modulation comparator PWM.

Further, the fixed T _ON generation circuit includes a comparator, an inverter, a first NAND gate, a second NAND gate, a current source Is ₁₀₁ , an NMOS transistor M ₁₀₁ and a capacitor C ₁₀₁ ; wherein:

The input end of the current source Is ₁₀₁ is connected to the internal power supply V _DD , the output end of the current source Is ₁₀₁ is connected to the capacitor C ₁₀₁ and the drain of the NMOS transistor M ₁₀₁ , and the other end of the capacitor C ₁₀₁ is connected to the source of the NMOS transistor M ₁₀₁ and ground, The gate of the NMOS transistor _M101 is connected to QN;

The inverting terminal of the comparator is connected with the output terminal of the current source Is ₁₀₁ , the inverting terminal of the comparator is connected with the clock control signal V _REF , the output terminal of the comparator is connected with the input terminal of the first NAND gate and the second NAND gate The output terminals of the NOT gates are all connected, the output terminals of the first NAND gate are connected with QN, the input terminals of the inverter are connected with the output terminals of the pulse width modulation comparator PWM, and the output terminals of the inverter are connected with the second AND The input terminals of the NOT gate are connected with the output terminals of the first NAND gate, and the output terminals of the second NAND gate are connected with the input terminals of the dead zone control driver.

Further, the current sampling unit includes a current source IS201, a current source _IS202 , a PMOS transistor _M203 , a PMOS transistor _M204 , a PMOS transistor _M205 , a PMOS transistor _M207 , an NMOS transistor _M201 , an NMOS transistor _M202 , and an NMOS transistor _M202 . Tube M ₂₀₆ , resistor R ₂₀₁ and resistor R ₂₀₂ ; where:

The input end of the current source I _S201 is connected to the internal power supply V _DD , the output end of the current source I _S201 is connected to the drain and gate of the NMOS transistor M ₂₀₁ , the source of the NMOS transistor M ₂₀₁ is grounded, the NMOS transistor M ₂₀₁ and the NMOS transistor M ₂₀₂ Form a row of current mirrors with the NMOS tube M ₂₀₆ ;

The source of the PMOS transistor _M203 is connected to the drain of the synchronous power transistor Q1, the drain _of the PMOS transistor _M203 is connected to the drain of the NMOS transistor _M202 and the gate of the PMOS transistor _M207 , and the gate of the PMOS transistor _M203 The gate is connected to the drain and gate of the PMOS transistor M ₂₀₅ ; the source of the PMOS transistor M ₂₀₄ is connected to the source _of the synchronous power transistor Q1, and the gate of the PMOS transistor M ₂₀₄ is connected to the synchronous power transistor Q ₁ , the drain of the PMOS transistor _M204 is connected to the source of the PMOS transistor _M205 and the source of the PMOS transistor _M207 ; the drain of the PMOS transistor _M205 is connected to the drain of the NMOS transistor _M206 , and the PMOS The drain of the tube M ₂₀₇ is grounded through the resistor R ₂₀₁ ;

The input terminal of the current source _IS202 is connected to the internal power supply _VDD , the output terminal of the current source _IS202 is connected to the resistor _R202 and the non-inverting terminal of the pulse width modulation comparator PWM, and the resistor _R202 is connected to the drain of the PMOS transistor _M207 .

Further, the current sampling unit includes a current source IS301, a current source _IS302 , a PMOS transistor _M302 , a PMOS transistor _M303 , a PMOS transistor _M307 , a PMOS transistor _M308 , an NMOS transistor _{M301, an NMOS transistor M304 ,} and an NMOS transistor _M304 . Tube M ₃₀₅ , NMOS tube M ₃₀₆ , resistor R ₃₀₁ , resistor R ₃₀₂ , resistor R ₃₀₃ and capacitor C ₃₀₁ ; where:

The input end of the current source _IS301 is connected to the internal power supply V _DD , the output end of the current source _IS301 is connected to the drain and gate of the NMOS transistor _M301 , the source of the NMOS transistor _M301 is grounded, and the NMOS transistor _M301 and the NMOS transistor _M306 constitute a current mirror;

The source of the PMOS transistor _{M302 and the source of the PMOS transistor M303 are} both connected to the internal power supply V _DD , the gate and drain of the PMOS transistor _M302 are connected to the gate of the PMOS transistor _M303 , and the drain of the PMOS transistor _M302 connected to the drain of the NMOS transistor _M304 ; the drain of the PMOS transistor _M303 is connected to the drain of the NMOS transistor _M305 ; the source of the NMOS transistor _M304 and the source of the NMOS transistor _M305 are both connected to the drain of the NMOS transistor _M306 The gate of the NMOS transistor _M304 is connected to the drain _of the synchronous power transistor Q1, the gate of the NMOS transistor _M305 is connected to the drain of the PMOS transistor _M307 and the source of the PMOS transistor _M308 ;

The resistor R ₃₀₁ and the capacitor C ₃₀₁ are connected in series between the internal power supply V _DD and the drain of the PMOS transistor M ₃₀₃ ; the source of the PMOS transistor M ₃₀₇ is connected to the source of the synchronous power transistor Q ₁ , and the gate of the PMOS transistor M ₃₀₇ The pole is connected with the gate of the synchronous power transistor Q1 _; the gate of the PMOS transistor _{M308 is connected with the drain of the PMOS transistor M303 ,} and the drain of the PMOS transistor _M308 is grounded through the resistor _R302 ;

The input terminal of the current source _IS302 is connected to the internal power supply V _DD , the output terminal of the current source _IS302 is connected to the resistor _R303 and the non-inverting terminal of the pulse width modulation comparator PWM, and the resistor _R303 is connected to the drain of the PMOS transistor _M308 .

Compared with the prior art, the utility model has the following technical effects:

1. The utility model adopts the fixed TON mode. When the load changes, it can make feedback and respond to the change of the output at the fastest speed, which effectively improves the response speed of the loop.

2. The utility model adopts the valley current type TON mode, which does not need a harmonic compensation circuit, and has the advantages of simplified loop control and high reliability.

Description of drawings

Fig. 1 is a system block diagram of a conventional boost circuit;

Fig. 2 is a block diagram of the utility model;

Fig. 3 is the schematic diagram of the fixed T _ON generating circuit in embodiment 1;

Fig. 4 is the schematic diagram of the current sampling unit in embodiment 1;

FIG. 5 is a schematic diagram of the current sampling unit in Embodiment 2.

The symbols in the figure represent: 1—fixed T _ON generating circuit, 101—comparator, 102—inverter, 103—first NAND gate, 104—second NAND gate, 2—current sampling unit.

Below in conjunction with accompanying drawing and embodiment, the scheme of the utility model is further explained and described in detail.

detailed description

Example 1:

According to the above technical solution, referring to FIG. 2, the DC-DC converter circuit of this embodiment includes a synchronous power transistor Q1, a main switch transistor _Q2 , a dead zone control driver and a pulse width modulation comparator PWM, wherein the synchronous power transistor Q1 The main switching tube _Q2 is connected in parallel with the ground, the output terminal of the dead zone control driver is connected to the grid of the synchronous power tube Q1 and the grid of the main switching tube _Q2 , and the converter circuit also includes a fixed T _ON generating circuit 1. Current sampling unit 2, diode D ₁ and diode D ₂ , wherein:

Diode D ₁ and diode D ₂ are reversely connected in parallel with the source and drain of the synchronous power transistor Q ₁ ; the fixed T _ON generation circuit 1 includes two input ends a and b, one output end c, and the current sampling unit 2 includes Three input terminals d, e and f, and one output terminal g; the input terminal a is connected to the output terminal of the pulse width modulation comparator PWM, and the output terminal of the pulse width modulation comparator PWM outputs a pulse width modulation signal V _PWM , and the input terminal b is connected to the clock control signal V _REF , the output terminal c is connected to the input terminal of the dead zone control driver, and the output terminal c outputs the driving control signal V _DH ; the input terminals d, e and f are respectively connected to the source _of the synchronous power transistor Q1 pole, gate and drain, the input terminals d, e and f respectively input the source switching node voltage V _SW , the gate control signal V _GATE and the drain output voltage V _OUT , and the output terminal g is connected to the pulse width modulation The non-inverting terminal of the comparator PWM, the output terminal g outputs the voltage signal V _LOAD of the sampling current.

The converter circuit of this embodiment also includes a DC power supply, a capacitor C ₁ , an inductor L ₁ , a capacitor C ₂ , a sampling resistor R _SNS1 , a sampling resistor _RSNS2 , a compensation network, and an error amplifier EA, wherein the input DC power supply is connected in parallel with a capacitor C ₁ to get the input voltage V _IN , the inductance L ₁ is connected in series between the capacitor C ₁ and the synchronous power transistor Q _{1 ;} the main switch Q ₂ is connected in parallel between the source of the synchronous power transistor Q ₁ and the ground, and the A capacitor C ₂ is connected in parallel between the drain and the ground; the voltage V _FB formed after the output voltage V _OUT is divided by the sampling resistors R _SNS1 and R _SNS2 is connected to the inverting terminal of the error amplifier EA, and the non-inverting terminal of the error amplifier EA is connected to the reference signal V _R , the output of the error amplifier EA is connected to the compensation network;

Two reversely connected diodes D ₁ and D ₂ are connected in parallel to the source and drain of the synchronous power transistor Q ₁ , the source switching node voltage V _SW , the drain output voltage V _OUT and the gate control signal of the synchronous power transistor Q ₁ V _GATE is connected to the input terminal of the current sampling unit; the inverting terminal of the pulse width modulation comparator PWM is connected to the output terminal of the compensation network, the non-inverting terminal of the pulse width modulation comparator PWM is connected to the output terminal g, and the output terminal of the pulse width modulation comparator PWM The output pulse width modulation signal V _PWM is input to the input terminal a of the fixed T _ON generating circuit.

The fixed T _ON generation circuit ₁ compares the result V _{PWM generated by the pulse width modulation comparator PWM} with the clock signal generated by the clock control signal V _REF , and is used to control the generation of synchronous power transistor Q1 and main switch transistor _Q2 The driving signal V _DH ; the current sampling unit 2 is used to sample the voltage difference between the drain voltage V _OUT of the synchronous power transistor Q ₁ and the source switching node voltage V _SW , and the voltage signal V _LOAD of the sampling current Send to the pulse width modulation comparator PWM.

When the main switch Q ₂ is turned on, the DC power flows to the inductor L ₁ , the synchronous power tube Q ₁ prevents the discharge of the capacitor C ₂ to the ground, and the current on the inductor L ₁ increases linearly at a certain rate. As the current of the inductor L 1 increases, the inductor L ₁ Some energy is stored in L1 _; when the main switch tube _Q2 is turned off, due to the current retention characteristics _of the inductor L1, the current flowing through the inductor L1 will not immediately become zero, but slowly change from the value at the end _of charging becomes zero, and the original circuit has been disconnected, so the inductor L ₁ starts to charge the capacitor C ₂ , and the output voltage V _OUT at both ends of the capacitor C ₂ rises, and the output voltage V _OUT is already higher than the input voltage V _IN at this time.

Specifically, referring to FIG. 3, the fixed T _ON generation circuit 1 includes a comparator 101, an inverter 102, a first NAND gate 103, a second NAND gate 104, a current source Is ₁₀₁ , an NMOS transistor M ₁₀₁ and a capacitor C ₁₀₁ ; where:

The input end of the current source Is ₁₀₁ is connected to the internal power supply V _DD , the output end of the current source Is ₁₀₁ is connected to the capacitor C ₁₀₁ and the drain of the NMOS transistor M ₁₀₁ , and the other end of the capacitor C ₁₀₁ is connected to the source of the NMOS transistor M ₁₀₁ and ground, The gate of the NMOS transistor _M101 is connected to QN;

The inverting terminal of the comparator 101 is connected with the output terminal of the current source Is ₁₀₁ , the inverting terminal of the comparator 101 is connected with the clock control signal V _REF , the output terminal of the comparator 101 is connected with the input terminal of the first NAND gate 103 The output ends of the second NAND gate 104 are connected, the output end of the first NAND gate 103 is connected with QN, the input end of the inverter 102 is connected with the output end of the pulse width modulation comparator PWM, and the inverter The output terminal of 102 is connected to the input terminal of the second NAND gate 104 and the output terminal of the first NAND gate 103 , and the output terminal of the second NAND gate 104 is connected to the input terminal of the dead zone control driver.

At this time, current source _IS101 , comparator ₁₀₁ , capacitor _C101 and NMOS transistor M101 form a one-shot circuit. First, current source _IS101 charges capacitor _C101 . When the voltage is equal to the clock control signal V _REF , then The output of comparator 101 sets the QN of the RS flip-flop formed by the first NAND gate 103 and the second NAND gate 104 to high level (that is, the output of comparator 101 is the clearing terminal of RS flip-flop), and starts to give The capacitor C ₁₀₁ is discharged to generate a constant on-time T _ON , that is, to generate a driving control signal V _DH .

The on-time T _ON is determined by the clock control signal V _REF , the value of the current source _IS101 and the value of the capacitor _C101 , namely:

${\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; N</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}\mathrm{<span\; class="notranslate">\; 101</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 101</span>}}<span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; E.</span>}\mathrm{<span\; class="notranslate">\; f</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

The conduction time T _ON and the switching time T determine the duty cycle D, thereby determining the boost result:

$\mathrm{<span\; class="notranslate">\; D.</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; N</span>}}}{\mathrm{<span\; class="notranslate">\; T</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

$\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; u</span>}\mathrm{<span\; class="notranslate">\; T</span>}}}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; I</span>}\mathrm{<span\; class="notranslate">\; N</span>}}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; D.</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

When the pulse width modulation signal V _PWM is high, it means that the output voltage V _OUT has reached the requirement at this time, so the boosting action should be turned off, so the output terminal of the inverter 102 is the set terminal of the RS flip-flop.

Specifically, referring to FIG. 4 , the current sampling unit 2 includes a current source IS201, a current source _IS202 , a PMOS transistor _M203 , a PMOS transistor _M204 , a PMOS transistor _M205 , a PMOS transistor _M207 , an NMOS transistor _M201 , and an NMOS transistor _M201 . Tube M ₂₀₂ , NMOS tube M ₂₀₆ , resistor R ₂₀₁ and resistor R ₂₀₂ ; where:

The input end of the current source I _S201 is connected to the internal power supply V _DD , the output end of the current source I _S201 is connected to the drain and gate of the NMOS transistor M ₂₀₁ , the source of the NMOS transistor M ₂₀₁ is grounded, the NMOS transistor M ₂₀₁ and the NMOS transistor M ₂₀₂ Form a row of current mirrors with the NMOS tube M ₂₀₆ ;

The source of the PMOS transistor _M203 is connected to the drain of the synchronous power transistor Q1, the drain _of the PMOS transistor _M203 is connected to the drain of the NMOS transistor _M202 and the gate of the PMOS transistor _M207 , and the gate of the PMOS transistor _M203 The gate is connected to the drain and gate of the PMOS transistor M ₂₀₅ ; the source of the PMOS transistor M ₂₀₄ is connected to the source _of the synchronous power transistor Q1, and the gate of the PMOS transistor M ₂₀₄ is connected to the synchronous power transistor Q ₁ , the drain of the PMOS transistor _M204 is connected to the source of the PMOS transistor _M205 and the source of the PMOS transistor _M207 ; the drain of the PMOS transistor _M205 is connected to the drain of the NMOS transistor _M206 , and the PMOS The drain of the tube M ₂₀₇ is grounded through the resistor R ₂₀₁ ;

The input terminal of the current source _IS202 is connected to the internal power supply _VDD , the output terminal of the current source _IS202 is connected to the resistor _R202 and the non-inverting terminal of the pulse width modulation comparator PWM, and the resistor _R202 is connected to the drain of the PMOS transistor _M207 .

The sampling current I _LOAD is realized by sampling the PMOS transistor M ₂₀₄ . The relationship between the sampling current I _LOAD and the operating current _{I Q1} of the synchronous power transistor Q1 is determined by the conduction impedance _of the synchronous power transistor Q1 and the PMOS transistor _M204 , and the specific relationship is:

$\begin{array}{c}\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; A</span>}\mathrm{<span\; class="notranslate">\; D.</span>}}}{{\mathrm{<span\; class="notranslate">\; I</span>}}_{{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}}<span\; class="notranslate">\; =</span>\frac{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; u</span>}\mathrm{<span\; class="notranslate">\; T</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}\mathrm{<span\; class="notranslate">\; W</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{{\mathrm{<span\; class="notranslate">\; m</span>}}_{\mathrm{<span\; class="notranslate">\; 204</span>}}}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; u</span>}\mathrm{<span\; class="notranslate">\; T</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}\mathrm{<span\; class="notranslate">\; W</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}}\\ <span\; class="notranslate">\; =</span>\frac{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; u</span>}\mathrm{<span\; class="notranslate">\; T</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}\mathrm{<span\; class="notranslate">\; W</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; /</span><span\; class="notranslate">\; \&lsqb;</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; x</span>}}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{{\mathrm{<span\; class="notranslate">\; m</span>}}_{\mathrm{<span\; class="notranslate">\; 204</span>}}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; G</span>}\mathrm{<span\; class="notranslate">\; S</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}\mathrm{<span\; class="notranslate">\; h</span>}}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&rsqb;</span>}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; u</span>}\mathrm{<span\; class="notranslate">\; T</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}\mathrm{<span\; class="notranslate">\; W</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; /</span><span\; class="notranslate">\; \&lsqb;</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; x</span>}}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; G</span>}\mathrm{<span\; class="notranslate">\; S</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}\mathrm{<span\; class="notranslate">\; h</span>}}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&rsqb;</span>}\\ <span\; class="notranslate">\; =</span>\frac{{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{{\mathrm{<span\; class="notranslate">\; m</span>}}_{\mathrm{<span\; class="notranslate">\; 204</span>}}}}{{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}}\end{array}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

Among them, W/L is the width-to-length ratio of the MOS transistor, where μ _p is the hole mobility, C _OX is the gate oxide capacitance per unit area, V _GS is the gate-source voltage, and V _TH is the threshold voltage.

It can be seen from the above formula that the sampling current I _LOAD is only related to the size of the synchronous power transistor Q ₁ and the PMOS transistor M ₂₀₄ , and has nothing to do with other parameters such as temperature. In the above formula, the relationship between the sampling current I _LOAD and the voltage signal V _LOAD of the sampling current is:

V _LOAD ＝(I _LOAD +I _S202 )×R ₂₀₁ +I _S202 ×R ₂₀₂ (5)

Among them, the purpose of adding the current source _IS202 is to generate a DC bias voltage to provide a suitable working point for the pulse width modulation comparator PWM.

Example 2:

The T _ON generating circuit 1 of this embodiment is the same as that in Embodiment 1.

Referring to FIG. 5 , the current sampling unit 2 of this embodiment includes a current source I _S301 , a current source I _S302 , a PMOS transistor M ₃₀₂ , a PMOS transistor M ₃₀₃ , a PMOS transistor M ₃₀₇ , a PMOS transistor M ₃₀₈ , an NMOS transistor M ₃₀₁ , NMOS transistor M ₃₀₄ , NMOS transistor M ₃₀₅ , NMOS transistor M ₃₀₆ , resistor R ₃₀₁ , resistor R ₃₀₂ , resistor R ₃₀₃ and capacitor C ₃₀₁ ; where:

The input end of the current source _IS301 is connected to the internal power supply V _DD , the output end of the current source _IS301 is connected to the drain and gate of the NMOS transistor _M301 , the source of the NMOS transistor _M301 is grounded, and the NMOS transistor _M301 and the NMOS transistor _M306 constitute a current mirror;

The source of the PMOS transistor _{M302 and the source of the PMOS transistor M303 are} both connected to the internal power supply V _DD , the gate and drain of the PMOS transistor _M302 are connected to the gate of the PMOS transistor _M303 , and the drain of the PMOS transistor _M302 connected to the drain of the NMOS transistor _M304 ; the drain of the PMOS transistor _M303 is connected to the drain of the NMOS transistor _M305 ; the source of the NMOS transistor _M304 and the source of the NMOS transistor _M305 are both connected to the drain of the NMOS transistor _M306 The gate of the NMOS transistor _M304 is connected to the drain _of the synchronous power transistor Q1, the gate of the NMOS transistor _M305 is connected to the drain of the PMOS transistor _M307 and the source of the PMOS transistor _M308 ;

The resistor R ₃₀₁ and the capacitor C ₃₀₁ are connected in series between the internal power supply V _DD and the drain of the PMOS transistor M ₃₀₃ ; the source of the PMOS transistor M ₃₀₇ is connected to the source of the synchronous power transistor Q ₁ , and the gate of the PMOS transistor M ₃₀₇ The pole is connected with the gate of the synchronous power transistor Q1 _; the gate of the PMOS transistor _{M308 is connected with the drain of the PMOS transistor M303 ,} and the drain of the PMOS transistor _M308 is grounded through the resistor _R302 ;

The input terminal of the current source _IS302 is connected to the internal power supply V _DD , the output terminal of the current source _IS302 is connected to the resistor _R303 and the non-inverting terminal of the pulse width modulation comparator PWM, and the resistor _R303 is connected to the drain of the PMOS transistor _M308 .

The sampling current I _LOAD is realized by sampling the PMOS transistor M ₃₀₇ . The relationship between the sampling current I _LOAD and the operating current _{I Q1} of the synchronous power transistor Q1 is determined by the conduction impedance _of the synchronous power transistor Q1 and the PMOS transistor _M307 , and the specific relationship is:

$\begin{array}{c}\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; A</span>}\mathrm{<span\; class="notranslate">\; D.</span>}}}{{\mathrm{<span\; class="notranslate">\; I</span>}}_{{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}}<span\; class="notranslate">\; =</span>\frac{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; u</span>}\mathrm{<span\; class="notranslate">\; T</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}\mathrm{<span\; class="notranslate">\; W</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{{\mathrm{<span\; class="notranslate">\; m</span>}}_{\mathrm{<span\; class="notranslate">\; 307</span>}}}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; u</span>}\mathrm{<span\; class="notranslate">\; T</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}\mathrm{<span\; class="notranslate">\; W</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}}\\ <span\; class="notranslate">\; =</span>\frac{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; u</span>}\mathrm{<span\; class="notranslate">\; T</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}\mathrm{<span\; class="notranslate">\; W</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; /</span><span\; class="notranslate">\; \&lsqb;</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; x</span>}}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{{\mathrm{<span\; class="notranslate">\; m</span>}}_{\mathrm{<span\; class="notranslate">\; 307</span>}}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; G</span>}\mathrm{<span\; class="notranslate">\; S</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}\mathrm{<span\; class="notranslate">\; h</span>}}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&rsqb;</span>}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; u</span>}\mathrm{<span\; class="notranslate">\; T</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}\mathrm{<span\; class="notranslate">\; W</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; /</span><span\; class="notranslate">\; \&lsqb;</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; x</span>}}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; G</span>}\mathrm{<span\; class="notranslate">\; S</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}\mathrm{<span\; class="notranslate">\; h</span>}}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&rsqb;</span>}\\ <span\; class="notranslate">\; =</span>\frac{{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{{\mathrm{<span\; class="notranslate">\; m</span>}}_{\mathrm{<span\; class="notranslate">\; 307</span>}}}}{{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}}\end{array}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; )</span>$

It can be seen from the above formula that the sampling current I _LOAD is only related to the size of Q ₁ and the PMOS transistor M ₃₀₇ , and has nothing to do with other parameters such as temperature. In the formula, the relationship between the sampling current I _LOAD and the voltage signal V _LOAD of the sampling current is:

V _LOAD ＝(I _LOAD +I _S302 )×R ₃₀₂ +I _S302 ×R ₃₀₃ (7)

Among them, the purpose of adding the current source _IS302 is to generate a DC bias voltage to provide a suitable working point for the pulse width modulation comparator PWM.

The PMOS transistors M ₃₀₂ , M ₃₀₃ , the NMOS transistors M ₃₀₄ , M ₃₀₅ and the PMOS transistor M ₃₀₂ form a two-stage current sampling amplifier, and the resistor R ₃₀₁ and capacitor C ₃₀₁ function as loop compensation for the current sampling amplifier.

Claims (4)

1. a DC/DC convertor circuitry, including synchronizing power pipe Q1, main switch Q₂, dead zone function driver and pwm comparator PWM, wherein, main switch Q in parallel between synchronizing power pipe Q1 and ground₂, the grid of the outfan of dead zone function driver and synchronizing power pipe Q1 and main switch Q₂Grid be all connected with, it is characterised in that described converter circuit also includes fixing T_ONProduce circuit (1), current sampling unit (2), diode D₁With diode D₂, wherein:

Diode D₁With diode D₂Reversal connection is connected in parallel on described synchronizing power pipe Q₁Source electrode and drain electrode；Fixing T_ONProducing circuit (1) and include two input a and b, an outfan c, current sampling unit (2) includes three input d, e and f, an outfan g；Input a connects the outfan of described pwm comparator PWM, and input b connects clock control signal V_REF, outfan c connects the input of described dead zone function driver；Input d, e and f connect described synchronizing power pipe Q respectively₁Source electrode, grid and drain electrode, outfan g connects the in-phase end of described pwm comparator PWM.

2. DC/DC convertor circuitry as claimed in claim 1, it is characterised in that described fixing T_ONProduce circuit (1) and include comparator (101), phase inverter (102), the first NAND gate (103), the second NAND gate (104), current source Is₁₀₁, NMOS tube M₁₀₁With electric capacity C₁₀₁；Wherein:

Current source Is₁₀₁Input connect internal electric source V_DD, current source Is₁₀₁Outfan connect electric capacity C₁₀₁With NMOS tube M₁₀₁Drain electrode, electric capacity C₁₀₁The other end and NMOS tube M₁₀₁Source electrode be connected to the ground, NMOS tube M₁₀₁Grid be connected with QN；

The backward end of comparator (101) and current source Is₁₀₁Outfan be connected, the backward end of comparator (101) and described clock control signal V_REFIt is connected, the outfan of the outfan of comparator (101) and the input of the first NAND gate (103) and the second NAND gate (104) is all connected, the outfan of the first NAND gate (103) is connected with QN, the input of phase inverter (102) is connected with the outfan of described pwm comparator PWM, the outfan of the outfan of phase inverter (102) and the input of the second NAND gate (104) and the first NAND gate (103) is all connected, and the outfan of the second NAND gate (104) is connected with the input of described dead zone function driver.

3. DC/DC convertor circuitry as claimed in claim 1, it is characterised in that described current sampling unit (2) includes current source I_S201, current source I_S202, PMOS M₂₀₃, PMOS M₂₀₄, PMOS M₂₀₅, PMOS M₂₀₇, NMOS tube M₂₀₁, NMOS tube M₂₀₂, NMOS tube M₂₀₆, resistance R₂₀₁With resistance R₂₀₂；Wherein:

Current source I_S201Input connect internal electric source V_DD, current source I_S201Outfan connect NMOS tube M₂₀₁Drain and gate, NMOS tube M₂₀₁Source ground, NMOS tube M₂₀₁, NMOS tube M₂₀₂With NMOS tube M₂₀₆Structure current mirror in a row；

PMOS M₂₀₃Source electrode connect described synchronizing power pipe Q₁Drain electrode, PMOS M₂₀₃Drain electrode and NMOS tube M₂₀₂Drain electrode and PMOS M₂₀₇Grid all connected, PMOS M₂₀₃Grid and PMOS M₂₀₅Drain and gate all connected；PMOS M₂₀₄Source electrode and described synchronizing power pipe Q₁Source electrode be connected, PMOS M₂₀₄Grid and described synchronizing power pipe Q₁Grid be connected, PMOS M₂₀₄Drain electrode and PMOS M₂₀₅Source electrode and PMOS M₂₀₇Source electrode all connected；PMOS M₂₀₅Drain electrode and NMOS tube M₂₀₆Drain electrode be connected, PMOS M₂₀₇Drain electrode by resistance R₂₀₁Ground connection；

Current source I_S202Input connect internal electric source V_DD, current source I_S202Outfan connect resistance R₂₀₂With the in-phase end of described pwm comparator PWM, resistance R₂₀₂With PMOS M₂₀₇Drain electrode be connected.

4. DC/DC convertor circuitry as claimed in claim 1, it is characterised in that described current sampling unit (2) includes current source I_S301, current source I_S302, PMOS M₃₀₂, PMOS M₃₀₃, PMOS M₃₀₇, PMOS M₃₀₈, NMOS tube M₃₀₁, NMOS tube M₃₀₄, NMOS tube M₃₀₅, NMOS tube M₃₀₆, resistance R₃₀₁, resistance R₃₀₂, resistance R₃₀₃With electric capacity C₃₀₁；Wherein:

Current source I_S301Input connect internal electric source V_DD, current source I_S301Outfan connect NMOS tube M₃₀₁Drain and gate, NMOS tube M₃₀₁Source ground, NMOS tube M₃₀₁With NMOS tube M₃₀₆Constitute current mirror；

PMOS M₃₀₂Source electrode and PMOS M₃₀₃Source electrode be all connected with internal electric source V_DD, PMOS M₃₀₂Grid and drain electrode all with PMOS M₃₀₃Grid be connected, PMOS M₃₀₂Drain electrode and NMOS tube M₃₀₄Drain electrode be connected；PMOS M₃₀₃Drain electrode and NMOS tube M₃₀₅Drain electrode be connected；NMOS tube M₃₀₄Source electrode and NMOS tube M₃₀₅Source electrode all with NMOS tube M₃₀₆Drain electrode be connected, NMOS tube M₃₀₄Grid and described synchronizing power pipe Q₁Drain electrode be connected, NMOS tube M₃₀₅Grid and PMOS M₃₀₇Drain electrode and PMOS M₃₀₈Source electrode all connected；

Resistance R₃₀₁With electric capacity C₃₀₁It is connected on internal electric source V_DDWith PMOS M₃₀₃Drain electrode between；PMOS M₃₀₇Source electrode and described synchronizing power pipe Q₁Source electrode be connected, PMOS M₃₀₇Grid and described synchronizing power pipe Q₁Grid be connected；PMOS M₃₀₈Grid and PMOS M₃₀₃Drain electrode be connected, PMOS M₃₀₈Drain electrode by resistance R₃₀₂Ground connection；

Current source I_S302Input termination internal electric source V_DD, current source I_S302Outfan connect resistance R₃₀₃With the in-phase end of described pwm comparator PWM, resistance R₃₀₃With PMOS M₃₀₈Drain electrode be connected.