CN103794561A - Manufacturing method of semiconductor device - Google Patents

Abstract

The present invention provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, the semiconductor substrate includes a first region and a second region, a first gate is formed on the first region, and a first gate is formed on the second region forming a second gate; performing a metallization process to form a metal silicide layer on the first gate, the second gate and the semiconductor substrate; performing thin film oxidation treatment to form a thin film on the metal silicide layer an oxide layer; forming a tensile stress layer on the second region; forming a compressive stress layer on the first region; performing an annealing process. In the present invention, the thin film oxidation treatment is carried out after the metallization process to form a thin film oxide layer on the metal silicide layer, thereby avoiding damage due to the necessary etching steps in the subsequent process of forming the tensile stress layer and the compressive stress layer. The metal silicide layer protects the metal silicide layer, thereby improving the performance of the semiconductor device.

Description

Manufacturing method of semiconductor device

technical field

The invention relates to an integrated circuit manufacturing method, in particular to a semiconductor device manufacturing method for reducing etching damage of a metal silicide layer.

Background technique

As the integration of semiconductor devices becomes higher and higher, the voltage and current required for the operation of semiconductor devices continue to decrease, and the switching speed of transistors is also accelerated, and the requirements for various aspects of semiconductor technology have been greatly increased. The prior art process has made transistors and other types of semiconductor device components as thick as several molecules and atoms, and the materials that make up semiconductors have reached the limit of physical and electrical characteristics.

The industry has proposed a material with a higher dielectric constant and better field effect characteristics than silicon dioxide - High-K Material, which is used to better separate the gate and other parts of the transistor, greatly Reduce leakage. At the same time, in order to be compatible with high dielectric constant materials, metal materials are used to replace the original polysilicon as the material of the gate conductive layer, thereby forming a new gate structure. During the high-temperature annealing process of the gate structure of metal materials, its work function (Work Function) will change greatly, resulting in problems such as gate depletion and RC delay, which will affect the performance of semiconductor devices. In order to solve the problem of the gate structure of the above-mentioned metal materials, a gate-last process (Gate-Last Process) is formed, that is, a dummy gate of polysilicon material is formed first, and after source/drain implantation and high-temperature annealing process, the dummy gate is removed. Extremely polysilicon layer, and deposit metal material, and finally form the metal gate.

Metal-oxide-semiconductor (CMOS) devices include a core device layer and an interconnection layer. Structures such as gates, sources, and drains are formed in the core device layer. Structures such as electrode, source and drain are electrically drawn out. As the size of the device continues to decrease, the contact area between the metal interconnection and the gate, source and drain continues to shrink, and the influence of the parasitic resistance at the contact on the device increases accordingly. In order to reduce the parasitic resistance, the metal silicide process (Salicide) came into being. Because the metal silicide (Silicide) has the characteristics of high melting point, stability and low resistivity, it can improve the driving current and operating speed of the entire semiconductor device, so The application in integrated circuit technology is more and more common.

In addition, in order to reduce the problems caused by size reduction, stress technology can be used to improve the stress of the channel region of the device, thereby increasing the mobility of carriers and improving the performance of the device. One method in the prior art is to introduce biaxial strain or uniaxial strain to the channel region of a metal-oxide-semiconductor field effect transistor (MOSFET) to increase the mobility of carriers in the channel region and improve the MOSFET's Device response speed, improve the performance of MOSFET devices, known as stress memory technology (SMT, Stress MemorizationTechnique). The specific stress memory technology is to form an inherently strained material layer, that is, a stress layer, above the semiconductor device, and perform a high-temperature annealing process so that the stress is memorized on the semiconductor device, such as in the gate polysilicon or diffusion region or in the silicon substrate. , by changing the spacing of silicon atoms in the channel under the gate of the FET through stress, reducing the obstruction of the passage of carriers, which is equivalent to reducing the resistance, so the heat generation and energy consumption of the semiconductor device will be reduced. The strained material is then removed, allowing the stress to be preserved and improving the mobility of electrons or holes, thereby improving the performance of the semiconductor as a whole. Different stresses have different effects on N-type devices and P-type devices, among which Tensile Stress can increase the spacing of silicon atoms in the channel under the gate of N-type devices, and the operating speed is improved; Compressive Stress (Compressive Stress) Stress) can reduce the spacing of silicon atoms in the channel under the gate of the P-type device, so that the operating speed can be improved. Therefore, different stress layers need to be formed on the NFET and the PFET to improve the performance of the semiconductor device.

However, when forming different stress layers, it is necessary to use a deposition method to cover a layer of stress layer film, and then use an etching method to remove the unretained area. In the necessary etching process, there is a certain delay due to the etching stop. Therefore, the etching process often damages the metal silicide layer, affects various properties such as the resistance of the metal silicide layer, and then affects the overall performance of the semiconductor device.

Contents of the invention

The object of the present invention is to provide a manufacturing method of a semiconductor device capable of protecting a metal silicide layer from etching damage.

The invention provides a method for manufacturing a semiconductor device, comprising the following steps:

providing a semiconductor substrate, the semiconductor substrate comprising a first region and a second region, a first gate is formed on the first region, and a second gate is formed on the second region;

performing a metallization process to form a metal silicide layer on the first gate, the second gate and the semiconductor substrate;

performing thin film oxidation treatment to form a thin film oxide layer on the metal silicide layer;

forming a tensile stress layer on the second region;

forming a compressive stress layer on the first region;

An annealing process is performed to generate stress on the first region and the second region respectively.

Further, in the step of performing film oxidation treatment, the metal silicide layer is rinsed with deionized water filled with ozone.

Further, the concentration of the ozone in the deionized water is 200PPM-2000PPM, and the time for washing the metal silicide layer with the deionized water is 5s-600s.

Further, in the step of performing film oxidation treatment, the ozone ions are sputtered onto the surface of the metal silicide layer by sputtering.

Further, in the process of sputtering the ozone ions onto the surface of the metal silicide layer by sputtering, the ambient temperature is 150°C-600°C, the time is 5s-120s, the radio frequency power is 50W-1000W, and the ozone passes through The intake amount is 1000sccm～20000sccm.

Further, the step of forming a tensile stress layer on the second region includes:

covering the tensile stress layer on the semiconductor substrate, and covering the first blocking photoresist on the tensile stress layer on the second region;

removing the tensile stress layer on the first region by etching;

removing the first blocking photoresist.

Further, the step of forming a compressive stress layer on the first region includes:

Covering a compressive stress layer on the semiconductor substrate, and covering a second blocking photoresist on the compressive stress layer on the first region;

removing the compressive stress layer on the second region by etching;

removing the second blocking photoresist.

Further, the first gate includes a first gate conductive layer, a first gate dielectric layer, and a first gate spacer located on sidewalls of the first gate conductive layer and the first gate dielectric layer, The second gate includes a second gate conductive layer, a second gate dielectric layer, and a second gate spacer located on sidewalls of the second gate conductive layer and the second gate dielectric layer.

Further, in the step of performing the metallization process, a metal silicide layer is formed on the first gate conductive layer, the second gate conductive layer and the semiconductor substrate.

Further, between the step of performing film oxidation treatment and the step of forming a tensile stress layer on the first region, it also includes performing a pressure approach treatment process to thin the first gate sidewall and the second gate sidewall wall.

Further, the first region is a P-type region, the first gate is a P-type gate; the second region is an N-type region, and the second gate is an N-type gate.

In summary, the present invention performs thin film oxidation treatment after the metallization process to form a thin film oxide layer on the metal silicide layer, thereby avoiding subsequent etching steps in the process of forming the tensile stress layer and the compressive stress layer The metal silicide layer is damaged, thereby protecting the metal silicide layer, thereby improving the performance of the semiconductor device.

Description of drawings

FIG. 1 is a schematic flowchart of a method for manufacturing a semiconductor device in an embodiment of the present invention.

2 to 9 are structural schematic diagrams of a manufacturing process of a semiconductor device in an embodiment of the present invention.

Detailed ways

In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be further described below in conjunction with the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also covered within the protection scope of the present invention.

Secondly, the present invention is described in detail by means of schematic diagrams. When describing the examples of the present invention in detail, for the convenience of explanation, the schematic diagrams are not partially enlarged according to the general scale, which should not be used as a limitation of the present invention.

The invention provides a method for manufacturing a semiconductor device, comprising the following steps:

Step S01: providing a semiconductor substrate, the semiconductor substrate includes a first region and a second region, a first gate is formed on the first region, and a second gate is formed on the second region;

Step S02: performing a metallization process to form a metal silicide layer on the first gate, the second gate and the semiconductor substrate;

Step S03: performing thin film oxidation treatment to form a thin film oxide layer on the metal silicide layer;

Step S04: forming a tensile stress layer on the second region;

Step S05: forming a compressive stress layer on the first region;

Step S06: performing an annealing process to generate stress on the first region and the second region respectively.

2 to 9 are structural schematic diagrams of a manufacturing process of a semiconductor device in an embodiment of the present invention. The manufacturing method of a semiconductor device in an embodiment of the present invention will be described in detail below with reference to FIGS. 2 to 9 .

As shown in FIG. 2, in step S01, a semiconductor substrate 100 is provided, the semiconductor substrate 100 includes a first region 10 and a second region 20, and the first region 10 and the second region 20 are isolated by a trench 103 , a first gate 101 is formed on the first region 10, and a second gate 102 is formed on the second region 20; the first gate 101 includes a first gate conductive layer 101a, a first gate A dielectric layer 101c and a first gate spacer 101b, the second gate 102 includes a second gate conductive layer 102a, a second gate dielectric layer 102c and a second gate spacer 102b. In this embodiment, the material of the semiconductor substrate 100 can be simple silicon, silicon-germanium compound, or silicon-on-insulator (SOI), and other semiconductor materials can also be used as the material of the semiconductor substrate 100 .

The specific formation process of the first gate 101 and the second gate 102 includes: covering the gate dielectric layer film (not shown in the figure) and the gate conductive layer film on the semiconductor substrate, using photolithography and etching etching process, forming a first gate dielectric layer 101c and a first gate conductive layer 101a on the first region 10, and forming a second gate dielectric layer 102c and a second gate electrode on the second region 20 Conductive layer 102a. Next, cover the sidewall film (not shown in the figure) on the semiconductor substrate 100; the material of the sidewall film can be silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon nitride or amorphous carbon One or a combination thereof, in this embodiment, the material of the sidewall film is silicon nitride, the sidewall film can be formed by chemical vapor deposition (CVD), and the thickness of the sidewall film is 100 angstroms to 200 angstroms. Next, etch the spacer film to form a first spacer 101b on the sidewalls of the first gate dielectric layer 101c and the first gate conductive layer 101a, and form a first spacer 101b on the sidewalls of the second gate dielectric layer 102c The first sidewall 102b is formed on the sidewall of the second gate conductive layer 102a.

In step S02, a metallization process is performed to form a metal silicide layer 106 on the first gate 101, the second gate 102 and the semiconductor substrate 100; usually the metal silicide layer 106 can be evaporated. ) or sputtering (sputtering) on the first grid 101, the second grid 102 and the semiconductor substrate 100, and then through the furnace tube or rapid thermal annealing, and in a gas with high purity (nitrogen or Argon), the metal silicide layer 106 as shown in FIG. 2 is formed by the reaction between the metal and the silicide interface. The metal silicide layer 106 can well improve the electrical connection characteristics of the semiconductor device.

As shown in Figure 3, in step S03, the key of the present invention is to perform thin film oxidation treatment to form a thin film oxide layer 105 on the metal silicide layer 106; Wash the metal silicide layer with deionized water with ozone, wherein the concentration of ozone in the deionized water is 200PPM～2000PPM, and the time for rinsing the metal silicide layer with deionized water is 5s～600s; in another implementation In an example, the ozone ions can also be sputtered onto the surface of the metal silicide layer by sputtering, wherein the ambient temperature during the sputtering process is 150°C-600°C, the time is 5s-120s, and the radio frequency power is 50W- 1000W, ozone flux is 1000sccm～20000sccm.

As shown in FIG. 4 , between step S03 and step S04 , it may also include performing a pressure approach process to thin the first gate spacer 101 b and the second gate spacer 102 b. This method can make the stress generated by the subsequently formed compressive stress layer or tensile stress layer better approach and act on the first gate dielectric layer 101c of the first gate 101 and the second gate dielectric of the second gate 102. layer 102c and the semiconductor substrate 100, thereby better improving the performance of the semiconductor device.

Continuing to take the structure shown in FIG. 3 as an example, in combination with FIG. 5 and FIG. 6, in step S04, the step of forming the tensile stress layer 107 on the second region 20 includes: as shown in FIG. Cover the tensile stress layer 107 on the substrate 100, and cover the first blocking photoresist 109 on the tensile stress layer 107 on the second region 20, the reaction gas forming the tensile stress layer 107 can be silane, ammonia gas , hydrogen and argon; thereafter, etching removes the tensile stress layer 107 on the first region 10, and then removes the first blocking photoresist 109, and the first blocking photoresist 109 can be ion ashed method to remove. During the etching process, the thin film oxide layer 105 can act as an etching barrier layer, and stop the etching process on the metal silicide layer 106 on the first region 10 in time, thereby avoiding etching damage to the first region 10. Metal silicide layer 106 on region 10 .

7 and 8, in step S05, the step of forming the compressive stress layer 111 on the first region 10 includes: as shown in FIG. 7, covering the compressive stress layer 111 on the semiconductor substrate 100, forming The reaction gas of the compressive stress layer 111 can be silane, ammonia, hydrogen and argon; and the compressive stress layer 111 on the first region 10 is covered with a second barrier photoresist 113, and the second barrier photoresist 113 ; then, etching removes the compressive stress layer 111 on the second region 20 ; thereafter, the second blocking photoresist 113 may be removed by ion ashing. Similarly, during the etching process, the thin film oxide layer 105 can act as an etching stopper to stop the etching process on the metal silicide layer 106 on the second region 20 in time, thereby avoiding etching damage to the second region 20. Metal silicide layer 106 on region 20 .

Of course, in the present invention, the sequence of step S04 and step S05 is not limited, step S04 can be performed first and then step S05 can be performed, or step S05 can be performed first and then step S04 can be performed.

Finally, in step S06 , an annealing process is performed to generate stress on the first region 10 and the second region 20 respectively. The compressive stress layer 111 on the first region 10 generates tensile stress, and the tensile stress layer 107 on the second region 20 generates compressive stress. In this embodiment, the first region 10 is a P-type region, the first gate 101 is a P-type gate, the second region 20 is an N-type region, and the second gate 102 is an N-type region. type grid. Therefore, it is realized that different stresses generate stresses on different types of regions, and then correspondingly play a role in improving the performance of the semiconductor device.

Referring to FIG. 9 , the following process steps may be removing the tensile stress layer 107 and the compressive stress layer 111 , and forming multiple interlayer dielectric layers and interconnection layers on the semiconductor substrate 100 to complete the manufacturing process of all semiconductor devices. The process steps are technical means well known to those skilled in the art, so details are not repeated here.

In summary, the present invention performs thin film oxidation treatment after the metallization process to form a thin film oxide layer on the metal silicide layer, thereby avoiding the subsequent process of forming the tensile stress layer and the compressive stress layer due to necessity. The etching step damages the metal silicide layer, thereby protecting the metal silicide layer, thereby improving the performance of the semiconductor device.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and changes without departing from the spirit and scope of the present invention. modification, so the scope of protection of the present invention should be defined by the claims.

Claims (11)

1. a manufacture method for semiconductor device, comprises,

Semiconductor substrate is provided, and described Semiconductor substrate comprises first area and second area, on described first area, is formed with first grid, on described second area, forms second grid;

Carry out metallization process, to form metal silicide layer in described first grid, second grid and Semiconductor substrate;

Carry out film oxidation processing, with in described metal silicide layer upper film oxide layer;

On described second area, form tension stress layer;

On described first area, form compressive stress layer;

Carry out annealing process, so that described first area and second area are produced respectively to effect of stress.

2. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, carrying out in the step of film oxidation processing, adopts metal silicide layer described in the deionized water rinsing that is filled with ozone.

3. the manufacture method of semiconductor device as claimed in claim 2, is characterized in that, the concentration of described ozone in deionized water is 200PPM～2000PPM, and the time of metal silicide layer is 5s～600s described in deionized water rinsing.

4. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, carrying out in the step of film oxidation processing, adopts sputtering method that described ozone ion is sputtered onto to described metal silicide layer surface.

5. the manufacture method of semiconductor device as claimed in claim 4, it is characterized in that, described ozone ion is sputtered onto in the process on described metal silicide layer surface at employing sputtering method, ambient temperature is 150 ℃～600 ℃, time is 5s～120s, radio-frequency power is 50W～1000W, and ozone intake is 1000sccm～20000sccm.

6. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, the step that forms tension stress layer on described second area comprises:

In described Semiconductor substrate, cover tension stress layer, and on tension stress layer on described second area, cover first and stop photoresist;

Etching is removed the tension stress layer on described first area;

Remove described first and stop photoresist.

7. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, the step that forms compressive stress layer on described first area comprises:

In described Semiconductor substrate, cover compressive stress layer, and on compressive stress layer on described first area, cover second and stop photoresist;

Etching is removed the compressive stress layer on described second area;

Remove described second and stop photoresist.

8. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, described first grid comprises first grid conductive layer, first grid dielectric layer and is positioned at described first grid conductive layer and the first grid side wall of first grid dielectric layer sidewall, and described second grid comprises second grid conductive layer, second grid dielectric layer and is positioned at described second grid conductive layer and the second grid side wall of second grid dielectric layer sidewall.

9. the manufacture method of semiconductor device as claimed in claim 8, is characterized in that, carrying out, in the step of metallization process, forming metal silicide layer in first grid conductive layer, second grid conductive layer and Semiconductor substrate.

10. the manufacture method of semiconductor device as claimed in claim 8, it is characterized in that, carry out film oxidation treatment step and on described first area, form between the step of tension stress layer, also comprising that carrying out pressure approaches processing procedure, with first grid side wall described in attenuate and second grid side wall.

The manufacture method of 11. semiconductor device as described in any one in claim 1 to 10, is characterized in that, described first area is p type island region, and described first grid is P type grid; Described second area WeiNXing district, described second grid is N-type grid.

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