CN103684364A - Self-timing four-phase clock generator - Google Patents
Self-timing four-phase clock generator Download PDFInfo
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- CN103684364A CN103684364A CN201310636407.9A CN201310636407A CN103684364A CN 103684364 A CN103684364 A CN 103684364A CN 201310636407 A CN201310636407 A CN 201310636407A CN 103684364 A CN103684364 A CN 103684364A
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Abstract
A self-timing four-phase clock generator can be used for operating a charge pump, and is configured by the aid of coupling elements so that overlapping of four phases is avoided. Two phases created through a delay buffer has substantive delay and is mainly used for determining clock frequency. The delay buffer and the coupling element together generate variable delay to respond to control current. A clock signal is provided, and frequency thereof is in proportion to the control current.
Description
Technical field:
The present invention relates to charge pump widely, and it generally adopts electricity online to wipe integrated circuit (IC) chip with electronically written memory (EEPROM).
Background technology:
Basic circuit is operated in relatively low voltage, and for example 3 volts or 5 volts, but some circuit functions need quite high voltage, and for example a builtin voltage is 15 volts.This higher voltage normally, with the form of voltage multiplier, provides by charge pump in a sheet.A plurality of driving stages that this charge pump is driven by a plurality of phase clocks form.Described phase clock, operates in a predetermined frequency continuous operation conventionally, thereby the highest effective value of the voltage after making to boost exists.Then, adopt a voltage regulator to reduce the voltage to required level.The electric current required due to the voltage after boosting is normally very low, can adopt a shunt regulator.
The chip high-voltage generator waste power consumption of this form, because stable current drain makes unnecessary lower voltage.Circuit start is slow, because must adopt a large amount of clock cycle to produce high voltage.
Summary of the invention:
An object of the present invention is to produce a plurality of phase clock signals, be suitable for driving a charge pump.
A further object of the present invention is to produce four phase clock signals, for operating a charge pump, and has the frequency that can change in the mode of input current.
Develop four phase clock signals, its clock conversion has the relation of regulation, and frequency can change, respond an input current, thereby when high electric current, produce pump startup, therefore when high-frequency, reduce start-up time to greatest extent, this is further object of the present invention.
Technical solution of the present invention:
These objects and other object obtain by develop four phase clocks in circuit, and this circuit comprises CMOS grid, under control electric current, operate.Due to the electric current increase of grid, latency reduction of its intrinsic level.A pair of delay buffer also receives control electric current, changes delay time lag.Two clock phases relate to delay element, and four all clock phases relate to voltage transitions, trigger the conversion of other phase places.Operate basic gate delay, to avoid the pulse overlap at various clock phases.Adopt a simple logical circuit, carry out the state of four clock phases of sensing, switch grid, to produce required clock signal.Consequently, the control of current response carrys out modulating clock frequency.When zero current, clock stops (frequency is zero), when maximum current, produces maximum clock frequency.Owing to realizing required high voltage, need a large periodicity, when maximum current, this system starts peak frequency.This can reduce start-up time effectively.In this process, do not relate to current loss, once realize the output of charge pump, just can close clock.When voltage drop, clock restarts, and voltage turns back to rapidly its required value, thus regulation voltage level.If there is a stable current drain, clock will be worked under a certain frequency, obtain a stable magnitude of voltage, thereby stablize this voltage, prevent current loss.The mode of any increase current loss, all can cause the raising of clock frequency, and extra-pay is provided.
Contrast patent documentation: CN202424651U adjustable non-overlapping clock signal generator 201220004969.2
Accompanying drawing explanation:
Figure 1 shows that a curve chart of 4 required clock phase signals.
Figure 2 shows that a block diagram of the wave sequence conversion of Fig. 1.
Figure 3 shows that the schematic diagram of a circuit, this circuit produces Fig. 1 and the clock phase A of Fig. 2 and the input of C and Current Control.
Figure 4 shows that the block diagram of a logical circuit, this circuit and Fig. 3, the circuit in Fig. 5 and Fig. 6 is associated.
Figure 5 shows that the schematic diagram of a circuit, this circuit produces clock phase B.
Figure 6 shows that the schematic diagram of a circuit, this circuit produces clock phase D.
Embodiment:
Figure 1 shows that the sequential relationship of four phasetophases of required clock signal.Waveform 10 to 13, describes respectively clock waveform A to D.
Figure 2 shows that a block diagram, represent the conversion sequence in clock signal.Rising transformation on 14 occurs in TO, the transformation of the first phase place A in representative graph 1.This rising is for setting up the transformation on 15, and this is that first of phase place C changes downwards.Then apply the transformation that this transformation makes progress for phase place B generation on 16, on 17, call the first delay, on 18, produce the downward transformation of phase place B.This transformation, the transformation making progress that then produces phase place C on 19.This will cause the downward transformation of the phase place A on 20.Then on 21, produce the transformation making progress of phase place D.After calling the second delay 22, the downward transformation of the phase place D on 23 has completed the clock cycle.It should be noted, continuous transformation is opposite polarity, and postpone a little.Little delay is present between adjacent clock transformation, is that the intrinsic delay existing on the grid by CMOS inverter obtains.Generally, this delay is that order with several nanoseconds carries out.In circuit below, this delay along with 17 with modulated together with the delay of first and second on 22, to determine clock frequency.
Circuit in Fig. 3 to Fig. 6 operates together, produces above-mentioned sequence.The circuit that will describe is comprised of traditional cmos element, and various functions can realize in the design of other equivalence, and this will be understandable.
Fig. 3 is the schematic diagram of a cmos circuit, produces clock phase A and C in Fig. 1.This circuit is from V
dDpower supply connects+arrives terminal 24, connect-to earth terminal 25.Clock A is on lead-out terminal 26, and clock C is on lead-out terminal 27.The title used of adjacent transistorized emitter represents relative size.
The input of circuit is an electric current I as shown in power supply 28.But should be understood that, this input current has determined clock frequency.When I=0, clock stops, and occurs a zero frequency.When I starts to flow, clock will start, and be operated under a frequency being directly proportional to electric current.
Input current I flows through N channel transistor 29, and this transistorized grid turns back to its drain electrode.This will produce a N bias generator on node 30, and this surpasses a more than ground threshold value slightly.Node 30 is directly connected to the grid of N channel transistor 31, forms a current mirror.As shown in the figure, if transistor 29 and 31 matches, electric current I will flow through transistor 31, therefore also flow through p channel transistor 32.Because the grid of transistor 32 is connected to its drain electrode, node 33 will be formulated a P biasing, slightly lower than at+V
dDunder a threshold value.Due to input current, I changes, and the voltage on node 30 and node 33 can change slightly to some extent, thereby makes bias node reflect this variation.
P channel transistor 38,39 and 40 be coupled in series in transistor 35 drain electrode and+V
dDbetween.When waveform D and logic Q are high level, transistor 39 and 40 will conduct, and due to transistor 38, it will conduct I/2.
N channel transistor 48 is driven outside frequency converter 45 with clock A.By the tandem compound of N channel transistor 49 and 50, the source-coupled of transistor 48 is to ground.Therefore,
when signal makes transistor 49 become conducting, transistor 48 conductings, when switch open, because the grid of transistor 50 is connected to node 30, transistor 48 flows through the electric current that has I/2.
Due to the series coupled of p channel transistor 51,52 and 53, arrive+V of the drain coupled of transistor 48
dDon.When transistor 51 and 52 is opened because of signal Q and clock B respectively, due to the cause of transistor 53, the electric current that these transistors will conduction I/2, therefore, there is clock C signal in transistor 48 and 51 drain electrode.This signal is added to the grid of p channel transistor 54 and N channel transistor 55, and it comprises a frequency converter grid.The grid of transistor 56 turns back to node 33, and the On current of controlling transistor 54 is I/2.The grid of transistor 57 turns back to node 30, and the On current of controlling transistor 55 is I/2.
Figure 4 shows that the block diagram of a simple logical circuit, this circuit produce Q and
signal, and may be used on Fig. 3, in 5 and 6 circuit.The function of this circuit is to determine half of clock cycle, the delay 1 of half of this clock cycle in Fig. 1 and postponing between time interval of 2.Dual input NOT-AND gate 61 and 62 forms a latch.Four input NOT-AND gates 63 provide latch to set pulse, and four input NOT-AND gates 64 provide reset pulse.When A and B level are all very high, Q set, when C and D level are all very high, Q resets.In circuit, add extra control inputs, to prevent any unnecessary logic state, can lock the clock oscillator of free-running operation.On terminal 65, there is Q output, on terminal 66, occur
output.Terminal 65 driving transistorss 36 and 40(Fig. 3), and terminal 66 driving transistorss 49 and 51.
Figure 5 shows that the circuit diagram of a clock phase B, this circuit has a lead-out terminal 68.Input terminal 69 is driven by frequency converter 58.+ V
dDbiasing, those elements in Fig. 3 are also taken from P and N biasing input.Clock C signal on terminal 69 is applied on p channel transistor 70.Transistor 70 and N channel transistor 73 and 75 series connection.These transistors can make level on node 72 uprise, but are subject to the I/2 current limit on transistor.Due to the tandem compound of N channel transistor 74,76 and 77, the level of node 72 also can step-down, but is subject to the I/2 current limit on transistor 77.Transistor 74 is inputted node 69 and is controlled, and transistor 76 is subject to the control of the signal Q in Fig. 4 logical circuit.
Node 72 forms the input of frequency converter grid, and it is comprised of together with current limit transistor 80 and 81 with N channel transistor 79 p channel transistor 78, and p channel transistor 80 returns to the arrive+V of source electrode of transistor 78
dD, and control the On current of I/2.N channel transistor 81 returns to the source electrode of transistor 79 to ground, and controls the On current of I/2. Transistor 78 and 79 drain electrode comprise a clock phase
circuit node, drives frequency converter 82 on terminal 68, to produce clock phase B.
This circuit comprises a delay buffer 84, its objective is the delay 1 producing in Fig. 1, and the operation of delay buffer 84 is as follows.P channel transistor 85 and N channel transistor 86, and with current limit transistor 87 and 88, form the grid of frequency converter, by the drain drives of transistor 78 and 79.Arrive+V of the source electrode of p channel transistor 87 coupled transistors 85
dDgo up, and the On current of I/2 is set.The source electrode of N channel transistor 88 coupled transistors 86 arrives ground, and the On current of I/2 is set, and p channel transistor 89 and N channel transistor 90 connect into shunt capacitor element, thus and the drain electrode of transistor 85 and 86 parallel connection.For the voltage swing in the output of frequency converter grid, capacitor must be recharged (or electric discharge).Because time of charging (or electric discharge) is the function of an electric current being applied in, the time will be a variable, and be the function of I/2.When maximum current, time delay will be minimum, and is the inverse function of the electric current I on the source electrode 28 of Fig. 3.Just now described delay-level, followed an identical delay-level 91, and therefore, element 84 is noninverting delay buffers.The output of buffer 84 is applied on the inverter 92 of quick response, and its output is connected to the grid of transistor 73 and 74.
In clock operation, the downward transformation of the clock signal C on terminal 69 (referring to the element 15 in Fig. 2) can (element 16 in Fig. 2) produce a transformation making progress on node 72.This transformation is again to reverse, and is applied to delay buffer 84, to produce the element 17 postponing in #1(Fig. 2).Therefore, the downward transformation of a delay is applied on frequency converter 92, and this produces again the downward transformation (element 18 in Fig. 2) postponing conversely on clock phase B.
Fig. 6 is the schematic diagram of clock signal D waveform generator.Its operation is identical with the operation of clock signal B in Fig. 5 circuit, except the operation to signal source and output symbol.Clock signal D is on terminal 94, and clock signal A is applied on input terminal 95,
be applied on terminal 96.As depicted in figs. 1 and 2, the downward transformation of clock A can start clock signal D and change downwards, and this transformation produces and postpones #2, and this causes again clock signal D to decline conversely, has so just caused clock signal A upwards to change.
The long and is that four phase clock signal generators produce continuous clock signal, and this is useful at driving voltage multiplication charge pump circuit.Clock frequency and control electric current and be directly proportional, in an actual example, it is 40MHz that four phase clocks are operated in a frequency, input is that under the state of 100 microamperes,, when zero current, frequency drops to zero.
The detailed description of a preferred embodiment of the present invention has been described.When a those skilled in the art is during in the description of reading above, within object of the present invention and intention, substitute and equivalent will be apparent.Therefore, scope of the present invention is only limited by claims.
Claims (7)
1. four phase clock generators of self-timing, is characterized in that: comprise first device, be used for producing a transformation making progress in the first phase place; The second device, response, in the transformation making progress described in the first phase place, is used for producing in third phase position a downward transformation; The 3rd device, the downward transformation that response produces in third phase position, is used for producing a transformation making progress in the second phase place; The first deferred mount, the transformation making progress that response produces in the second phase place, to produce the high level part of the second phase place, the first described deferred mount, can be used to produce the downward transformation of the delay of the second phase place; The 4th device, responds the downward transformation of the second phase place, is used for producing the transformation making progress of a third phase position; The 5th device, the transformation making progress of response third phase position, for generation of the downward transformation of first phase place; The 6th device, the downward transformation of response the first phase place, for generation of the transformation making progress of the 4th phase place; The second deferred mount, the transformation making progress that response produces in the 4th phase place, the second described deferred mount, can be used to produce the downward transformation of the delay of the 4th phase place; First device, the downward transformation of the 4th phase place of response, to produce the transformation making progress of the first phase place, thereby makes clock generator start a new clock cycle.
2. four phase clock generators of a kind of self-timing according to claim 1, is characterized in that: each first to the 6th device in four phase clock generators, all comprise inverse gate, and thereby make the transformation in four phase places, be all time delay.
3. four phase clock generators of a kind of self-timing according to claim 1, is characterized in that: the first and second deferred mounts in four phase clock generators are variable, thereby clock frequency is also variable.
4. four phase clock generators of a kind of self-timing according to claim 3, is characterized in that: the first and second deferred mounts in four phase clock generators are variable, response current input.
5. four phase clock generators of a kind of self-timing according to claim 2, is characterized in that: each first to the 6th inverse gate in four phase clock generators, comprises the device that changes its delay performance.
6. four phase clock generators of a kind of self-timing according to claim 5, is characterized in that: each first to the 6th inverse gate in four phase clock generators is variable, response current input.
7. four phase clock generators of a kind of self-timing according to claim 6, is characterized in that: the electric current input in four phase clock generators, also produces the first and second deferred mounts.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310636407.9A CN103684364A (en) | 2013-11-27 | 2013-11-27 | Self-timing four-phase clock generator |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310636407.9A CN103684364A (en) | 2013-11-27 | 2013-11-27 | Self-timing four-phase clock generator |
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| CN103684364A true CN103684364A (en) | 2014-03-26 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104941068A (en) * | 2015-06-17 | 2015-09-30 | 美敦力公司 | Implantable medical device with clock and self-timing component |
| CN105336368A (en) * | 2014-07-18 | 2016-02-17 | 北京兆易创新科技股份有限公司 | Non-overlapping four-phase clock generation circuit |
| CN106301291A (en) * | 2015-06-01 | 2017-01-04 | 中芯国际集成电路制造(上海)有限公司 | Clock signal generating circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5398001A (en) * | 1993-06-02 | 1995-03-14 | National Semiconductor Corporation | Self-timing four-phase clock generator |
-
2013
- 2013-11-27 CN CN201310636407.9A patent/CN103684364A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5398001A (en) * | 1993-06-02 | 1995-03-14 | National Semiconductor Corporation | Self-timing four-phase clock generator |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105336368A (en) * | 2014-07-18 | 2016-02-17 | 北京兆易创新科技股份有限公司 | Non-overlapping four-phase clock generation circuit |
| CN105336368B (en) * | 2014-07-18 | 2022-11-18 | 兆易创新科技集团股份有限公司 | Non-overlapping four-phase clock generation circuit |
| CN106301291A (en) * | 2015-06-01 | 2017-01-04 | 中芯国际集成电路制造(上海)有限公司 | Clock signal generating circuit |
| CN106301291B (en) * | 2015-06-01 | 2019-07-30 | 中芯国际集成电路制造(上海)有限公司 | Clock signal generating circuit |
| CN104941068A (en) * | 2015-06-17 | 2015-09-30 | 美敦力公司 | Implantable medical device with clock and self-timing component |
| CN104941068B (en) * | 2015-06-17 | 2021-02-09 | 美敦力公司 | Implantable medical device with clock and self-timing component |
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