CN105336368A

CN105336368A - Non-overlapping four-phase clock generation circuit

Info

Publication number: CN105336368A
Application number: CN201410345853.9A
Authority: CN
Inventors: 张现聚; 丁冲; 苏志强; 张君宇
Original assignee: GigaDevice Semiconductor Beijing Inc
Current assignee: GigaDevice Semiconductor Beijing Inc
Priority date: 2014-07-18
Filing date: 2014-07-18
Publication date: 2016-02-17
Anticipated expiration: 2034-07-18
Also published as: CN105336368B

Abstract

The invention discloses a non-overlapping four-phase clock generation circuit. The circuit comprises a bias voltage circuit, an enable control circuit, a non-overlapping delay circuit and a clock frequency circuit, wherein the bias voltage circuit comprises a first bias voltage circuit and a second bias voltage circuit; the first bias voltage circuit is used for providing a first bias voltage for the non-overlapping delay circuit and the clock frequency circuit; the second bias voltage circuit is used for providing a second bias voltage for the non-overlapping delay circuit and the clock frequency circuit; the enable control circuit is used for controlling the non-overlapping delay circuit according to an enable signal and a clock frequency output by the clock frequency circuit; the non-overlapping delay circuit is used for generating a non-overlapping four-phase signal; and the clock frequency circuit is used for generating the clock frequency of controlling the non-overlapping four-phase clock signal. The non-overlapping four-phase clock signal provided by the invention has better stability and does not fluctuate with power voltage fluctuation.

Description

A kind of non-overlapping four phase clock produces circuit

Technical field

The present invention relates to technical field of memory, be specifically related to a kind of non-overlapping four phase clock and produce circuit.

Background technology

Nonvolatile memory (FlashMemory) usually needs high pressure erasable when designing, and generally produce high pressure by charge pump, this charge pump is driven by non-overlapping four phase clock signal, to ensure that charge pump can normally work.

Usually using CMOS tube to produce non-overlapping four phase clock in prior art, when non-overlapping time requirement is longer, be only difficult to meet the demands by the stray capacitance that CMOS tube itself is less, therefore normally ensureing the longer non-overlapping time by inserting CMOS time delay.But when wide-voltage range works, such as 1.6V ~ 3.8V, the electric current of CMOS tube device can have greatly changed, thus the delay causing CMOS tube and CMOS time delay to produce differs greatly, cause non-overlapping four phase clock to change along with the fluctuation of supply voltage, thus be difficult to the correct work ensureing charge pump.

Fig. 1 is the structural drawing that in prior art, non-overlapping four phase clock produces circuit, as shown in Figure 1, this non-overlapping four phase clock produces circuit and is produced by metal-oxide-semiconductor, and described non-overlapping time and clock frequency is controlled by same input end φ, and by four output terminal φ ₁, φ ₂, φ ₃and φ ₄export non-overlapping four phase clock signal respectively.But, can not independently arrange between the non-overlapping time and clock frequency of this non-overlapping four phase clock generation circuit, within a clock period, when there is fluctuation in supply voltage, four phase place non-overlapping times changed due to the change of clock frequency, and non-overlapping four phase clock signal is changed along with the fluctuation of supply voltage.

Summary of the invention

In view of this, the invention provides a kind of non-overlapping four phase clock and produce circuit, to solve the problem of non-overlapping four phase clock signal along with mains fluctuations.

The invention provides a kind of non-overlapping four phase clock and produce circuit, described circuit comprises bias voltage circuit, enable control circuit, non-overlapping delay circuit and circuit of clock frequency, wherein,

Described bias voltage circuit comprises the first bias voltage circuit and the second bias voltage circuit, described first bias voltage circuit is connected with described non-overlapping delay circuit and described circuit of clock frequency all respectively with described second bias voltage circuit, described first bias voltage circuit is used for providing the first bias voltage for described non-overlapping delay circuit and described circuit of clock frequency, and described second bias voltage circuit is used for providing the second bias voltage for described non-overlapping delay circuit and described circuit of clock frequency;

The input end of described enable control circuit is connected with described circuit of clock frequency, output terminal is connected with described non-overlapping delay circuit, and described enable control circuit is for non-overlapping delay circuit according to the clock frequency control of enable signal and the output of described circuit of clock frequency;

The first end of described non-overlapping delay circuit is connected with described bias voltage circuit, and the second end is connected with the output terminal of described enable control circuit, and the 3rd end is connected with described circuit of clock frequency, and described non-overlapping delay circuit is for generation of non-overlapping four phase signal;

The first end of described circuit of clock frequency is connected with described bias voltage circuit, second end is connected with described enable control circuit, 3rd end is connected with described non-overlapping delay circuit, and described circuit of clock frequency is for generation of the clock frequency controlling non-overlapping four phase signal.

Further, described non-overlapping delay circuit comprises first order circuit, second level circuit, tertiary circuit, fourth stage circuit, the second phase inverter, the 3rd phase inverter, the 4th phase inverter, the 5th phase inverter, hex inverter, the 7th phase inverter, the 8th phase inverter, the 9th phase inverter, the tenth phase inverter, the 11 phase inverter, the 12 phase inverter, the 13 phase inverter, the 14 phase inverter, the 15 phase inverter, the first OR-NOT circuit, the second OR-NOT circuit, the second NAND gate circuit and the 3rd NAND gate circuit, wherein

Described first order circuit is connected between the output terminal of described second level circuit and described enable control circuit, and the mid point of described first order circuit and described second level circuit connection is first order node;

Described second level circuit is connected between described first order circuit and described tertiary circuit, and the mid point of described second level circuit and described tertiary circuit line is second level node;

Described tertiary circuit is connected between described second level circuit and described fourth stage circuit, and the mid point of described tertiary circuit and described fourth stage circuit connection is third level node;

Described fourth stage circuit is connected between described tertiary circuit and described circuit of clock frequency, and the mid point of described fourth stage circuit and described circuit of clock frequency line is fourth stage node;

The input end of described second phase inverter is connected with described first order node, the output terminal of described second phase inverter is for exporting the first reverse clock signal, the output terminal of the second phase inverter is connected with the input end of described 3rd phase inverter, the output terminal of described 3rd phase inverter is for exporting the first clock signal, and the output terminal of described 3rd phase inverter is connected with the first input end of the first input end of described second OR-NOT circuit and described 3rd NAND gate circuit;

The input end of described 4th phase inverter is connected with described second level node, the output terminal of described 4th phase inverter is for exporting the second reverse clock signal, the output terminal of described 4th phase inverter is connected with the input end of described 5th phase inverter, and the output terminal of described 4th phase inverter is connected with the first input end of the first input end of described first OR-NOT circuit and described second NAND gate circuit, the output terminal of described 5th phase inverter is for exporting second clock signal;

The input end of described hex inverter is connected with described third level node, the output terminal of described hex inverter is for exporting the 3rd reverse clock signal, the output terminal of described hex inverter is connected with the input end of described 7th phase inverter, the output terminal of described 7th phase inverter is for exporting the 3rd clock signal, and the output terminal of described 7th phase inverter is connected with the second input end of the second input end of described first OR-NOT circuit and described second NAND gate circuit;

The input end of described 8th phase inverter is connected with described 4th node, the output terminal of described 8th phase inverter is for exporting the 4th reverse clock signal, the output terminal of described 8th phase inverter is connected with the input end of described 9th phase inverter, and be connected with the second input end of described second OR-NOT circuit and the second input end of described 3rd NAND gate circuit, the output terminal of described 9th phase inverter is for exporting the 4th clock signal;

The output terminal of described first OR-NOT circuit is connected with the input end of described tenth phase inverter, and the output terminal of described tenth phase inverter is for exporting the one or four phase clock signal;

The output terminal of described second NAND gate circuit is connected with the input end of described 11 phase inverter, the output terminal of described 11 phase inverter is connected with the input end of described 12 phase inverter, and the output terminal of described 12 phase inverter is for exporting second phase clock signal;

The output terminal of described second OR-NOT circuit is connected with the input end of described 13 phase inverter, the output terminal of described 13 phase inverter is connected with the input end of described 14 phase inverter, and the output terminal of described 14 phase inverter is for exporting third phase clock signal;

The output terminal of described 3rd NAND gate circuit is connected with the input end of described 15 phase inverter, and the output terminal of described 15 phase inverter is for exporting the 4th phase clock signal.

Further, described first order circuit comprises the second PMOS, the 3rd PMOS, the second NMOS tube and the 3rd NMOS tube, wherein,

The grid of described second PMOS is for receiving the first bias voltage of the first bias voltage circuit generation, the source electrode of described second PMOS is connected with power supply, the drain electrode of described second PMOS is connected with the source electrode of described 3rd PMOS, the grid of described 3rd PMOS is connected with the output terminal of enable control circuit, the drain electrode of described 3rd PMOS is connected with the drain electrode of described second NMOS tube, the grid of described second NMOS tube is connected with the grid of described 3rd PMOS, the source electrode of described second NMOS tube is connected with the drain electrode of described 3rd NMOS tube, the grid of described 3rd NMOS tube is for receiving the second bias voltage of the second bias voltage circuit generation, the source ground of described 3rd NMOS tube,

Described second level circuit comprises the 4th PMOS, the 5th PMOS, the 4th NMOS tube, the 5th NMOS tube and the 6th NMOS tube, wherein,

The grid of described 4th PMOS is for receiving the first bias voltage of the first bias voltage circuit generation, the source electrode of described 4th PMOS is connected with power supply, the drain electrode of described 4th PMOS is connected with the source electrode of described 5th PMOS, the grid of described 5th PMOS is connected with the grid of described 4th NMOS tube, in the mid point of the grid of described 5th PMOS and the gate trace of described 4th NMOS tube and described first order circuit, the mid point of the mid point line of the drain electrode of the 3rd PMOS and the drain electrode line of described second NMOS tube is as first order node, the drain electrode of described 5th PMOS is connected with the drain electrode of the 4th NMOS tube, the source electrode of described 4th NMOS tube is connected with the source electrode of described 6th NMOS tube, the grid of described 5th NMOS tube is for receiving reverse enable signal, the drain electrode of described 5th NMOS tube is connected with the grid of the grid of described 4th NMOS tube and described 5th PMOS, the grid of described 6th NMOS tube is for receiving the second bias voltage of the second bias voltage circuit generation,

Described tertiary circuit comprises the 6th PMOS, the 7th PMOS, the 8th PMOS, the 7th NMOS tube and the 8th NMOS tube, wherein,

The grid of described 6th PMOS is for receiving enable signal, the source electrode of described 6th PMOS is connected with power supply, the drain electrode of described 6th PMOS is connected with the grid of described 8th PMOS, the source electrode of described 7th PMOS is connected with power supply, the grid of described 7th PMOS is for receiving the first bias voltage of the first bias voltage circuit generation, the drain electrode of described 7th PMOS is connected with the source electrode of described 8th PMOS, the drain electrode of described 8th PMOS is connected with the drain electrode of described 7th NMOS tube, the mid point that the mid point of the drain electrode of described 8th PMOS and the mid point of the drain electrode line of described 7th NMOS tube and the drain electrode of the 5th PMOS in the circuit of the described second level and the drain electrode line of the 4th NMOS tube is connected is as second level node, the grid of described 7th NMOS tube is connected with the grid of described 8th PMOS, the source electrode of described 7th NMOS tube is connected with the drain electrode of described 8th NMOS tube, the grid of described 8th NMOS tube is for receiving the second bias voltage of the second bias voltage circuit generation, the source ground of described 8th NMOS tube,

Described fourth stage circuit comprises the 9th PMOS, the tenth PMOS, the 9th NMOS tube, the tenth NMOS tube and the 11 NMOS tube, wherein,

The grid of described 9th PMOS is for receiving the first bias voltage of the first bias voltage circuit generation, the source electrode of described 9th PMOS is connected with power supply, the drain electrode of described 9th PMOS is connected with the source electrode of described tenth PMOS, the grid of described tenth PMOS is connected with the grid of described tenth NMOS tube, the mid point that the mid point of the grid of described tenth PMOS and the drain electrode of the 8th PMOS in the mid point of the gate trace of described tenth NMOS tube and described tertiary circuit and the drain electrode line of described 7th NMOS tube is connected is as third level node, the drain electrode of described tenth PMOS is connected with the drain electrode of described tenth NMOS tube, described tenth NMOS tube source electrode is connected with the drain electrode of described 11 NMOS tube, the mid point of the source electrode of described tenth PMOS and the drain electrode line of described 11 NMOS tube and the mid point of described circuit of clock frequency line are as fourth stage node, the grid of described 9th NMOS tube is for receiving reverse enable signal, the drain electrode of described 9th NMOS tube is connected with the grid of described tenth NMOS tube, the source ground of described 9th NMOS tube, the source electrode of described 9th NMOS tube connects, the grid of described 11 NMOS tube is for receiving the second bias voltage of the second bias voltage circuit generation, the source ground of described 11 NMOS tube.

Further, described circuit of clock frequency comprises level V circuit and the 6th grade of circuit, wherein,

Described level V circuit is connected between described fourth stage circuit and described 6th grade of circuit, and the mid point of described level V circuit and described 6th grade of circuit connection is level V node;

Described 6th grade of circuit is connected between described level V circuit and described enable control circuit, and the mid point of described 6th grade of circuit and described enable control circuit line is the 6th grade of node.

Further, described level V circuit comprises the 11 PMOS, the 12 PMOS, the 13 PMOS, the 12 NMOS tube, the 13 NMOS tube and the first electric capacity, wherein,

The grid of described 11 PMOS is for receiving enable signal, the source electrode of described 11 PMOS is connected with power supply, the drain electrode of described 11 PMOS is connected with the grid of described 13 PMOS, the grid of described 12 PMOS is connected with the grid of described first PMOS, the source electrode of described 12 PMOS is connected with power supply, the drain electrode of described 12 PMOS is connected with the source electrode of described 13 PMOS, the drain electrode of described 13 PMOS is connected with the drain electrode of described 12 NMOS tube, the source electrode of described 12 NMOS tube is connected with the drain electrode of described 13 NMOS tube, the grid of described 13 NMOS tube is for receiving the second bias voltage of the second bias voltage circuit generation, the source ground of described 13 NMOS tube, the first end of described first electric capacity is connected with described level V node, second end ground connection of described first electric capacity,

Described 6th grade of circuit comprises the 14 PMOS, the 15 PMOS, the 16 PMOS, the 14 NMOS tube, the 15 NMOS tube, the 16 NMOS tube and the second electric capacity, wherein,

The grid of described 14 PMOS is for receiving the first bias voltage of the first bias voltage circuit generation, the source electrode of described 14 PMOS is connected with power supply, the drain electrode of described 14 PMOS is connected with the source electrode of described 15 PMOS, the grid of described 15 PMOS is connected with the grid of described 15 NMOS tube, the mid point that the grid of described 15 PMOS and the line of the grid of described 15 NMOS tube and the drain electrode of the 13 PMOS in described level V circuit are connected with the line of the source electrode of described 12 NMOS tube is as level V node, the grid of described 14 NMOS tube is for receiving reverse enable signal, the drain electrode of described 14 NMOS tube is connected with the grid of described 15 NMOS tube, the source ground of described 14 NMOS tube, the source electrode of described 15 NMOS tube is connected with the drain electrode of described 16 NMOS tube, the grid of described 16 NMOS tube is for receiving the second bias voltage of the second bias voltage circuit generation, the source ground of described 16 NMOS tube, the mid point of the drain electrode of described 15 PMOS and the drain electrode line of described 15 NMOS tube and the mid point of described enable control circuit line are the 6th grade of node, the first end of described second electric capacity is connected with the 6th grade of node, second end ground connection of described second electric capacity, the source electrode of described 16 PMOS is connected with power supply, the grid of described 16 PMOS is for receiving enable signal, the drain electrode of described 16 PMOS is connected with the mid point of described 6th grade of node and described enable control circuit line.

Further, described first order circuit, second level circuit, tertiary circuit and fourth stage circuit also comprise at least one electric capacity respectively, the first end of described at least one electric capacity is connected with any first nodes in described first order node, second level node, third level node and fourth stage node, the second end ground connection of described at least one electric capacity.

Further, described first electric capacity, the second electric capacity and at least one electric capacity comprise any one in mos capacitance, MIM capacitor, PIP capacitor and MIP electric capacity.

Further, described circuit of clock frequency also comprises at least stage circuit, and described at least stage circuit is connected between described level V circuit and the 6th grade of circuit in turn.

Non-overlapping four phase clock provided by the invention produces circuit, the time delay of non-overlapping four phase clock signal is controlled by non-overlapping delay circuit, the clock frequency of non-overlapping four phase clock signal is controlled by circuit of clock frequency, make can separately to set between non-overlapping time and clock frequency, as long as clock frequency is stablized, the non-overlapping time between four phase places just can keep good stability, do not fluctuate with mains fluctuations, thus produce stable non-overlapping four phase clock signal do not changed with mains fluctuations.

Accompanying drawing explanation

Exemplary embodiment of the present invention will be described in detail by referring to accompanying drawing below, the person of ordinary skill in the art is more clear that above-mentioned and other feature and advantage of the present invention, in accompanying drawing:

Fig. 1 is the structural drawing that in prior art, non-overlapping four phase clock produces circuit;

Fig. 2 is the structural drawing of a kind of non-overlapping four phase clock generation circuit that the embodiment of the present invention one provides;

Fig. 3 is the structural drawing that a kind of non-overlapping four phase clock of providing of second embodiment of the invention produces bias voltage circuit described in circuit;

Fig. 4 is the structural drawing that a kind of non-overlapping four phase clock of providing of second embodiment of the invention produces enable control circuit described in circuit;

Fig. 5 a-Fig. 5 c is the structural drawing that a kind of non-overlapping four phase clock of providing of the embodiment of the present invention two produces non-overlapping delay circuit described in circuit;

Fig. 6 is the structural drawing of a kind of non-overlapping four phase clock of providing of the embodiment of the present invention two frequency circuit when producing described in circuit;

Fig. 7 is the sequential chart that a kind of non-overlapping four phase clock of providing of the embodiment of the present invention two produces each clock signal and each phase clock signal in circuit.

Embodiment

Below in conjunction with drawings and Examples, the present invention is described in further detail.Be understandable that, specific embodiment described herein is only for explaining the present invention, but not limitation of the invention.It also should be noted that, for convenience of description, illustrate only part related to the present invention in accompanying drawing but not full content.

Embodiment one

Fig. 2 is the structural drawing of a kind of non-overlapping four phase clock generation circuit that the embodiment of the present invention one provides, as shown in Figure 2, this non-overlapping four phase clock produces circuit and can be applicable in the integrated circuit (IC) chip of online electricity erasing and electronically written nonvolatile memory, and described non-overlapping four phase clock produces circuit and comprises bias voltage circuit 11, enable control circuit 12, non-overlapping delay circuit 13 and circuit of clock frequency 14.

Described bias voltage circuit 11 comprises the first bias voltage circuit 111 and the second bias voltage circuit 112, described first bias voltage circuit 111 is connected with described non-overlapping delay circuit 13 and described circuit of clock frequency 14 all respectively with described second bias voltage circuit 112, described first bias voltage circuit 111 is for providing the first bias voltage VBP for described non-overlapping delay circuit 13 and described circuit of clock frequency 14, and described second bias voltage circuit 112 is for providing the second bias voltage VBN for described non-overlapping delay circuit 13 and described circuit of clock frequency 14.

In the present embodiment, the size of the first bias voltage VBP and the second bias voltage VBN, can by arranging a constant current source in described first biasing circuit 111, a constant current source is also set at described second biasing circuit 112, and the size controlling the steady current that these two constant current sources produce realizes.By controlling the size of the first bias voltage VBP and the second bias voltage VBN, the size of charging and discharging currents in circuit at different levels in non-overlapping delay circuit 13 can be controlled, and then according to the size of stray capacitance in non-overlapping delay circuit 13 circuit at different levels, thus non-overlapping time delay can be determined.

The input end of described enable control circuit 12 is connected with described circuit of clock frequency 14, output terminal is connected with described non-overlapping delay circuit 13, and described enable control circuit 12 is for non-overlapping delay circuit 13 according to the clock frequency control of enable signal and described circuit of clock frequency 14 output.

In the present embodiment, the clock frequency that described circuit of clock frequency 14 exports can determine the discharge and recharge time by the node capacitor changed in circuit of clock frequency 14 in circuit at different levels, thus obtains the clock frequency in clock frequency 14.

The first end of described non-overlapping delay circuit 13 is connected with described bias voltage circuit 11, second end is connected with the output terminal of described enable control circuit 12,3rd end is connected with described circuit of clock frequency 14, and described non-overlapping delay circuit 13 is for generation of non-overlapping four phase signal.

In the present embodiment, by the size controlling stray capacitance in circuit at different levels in the size of constant current source in bias voltage circuit 11 and non-overlapping delay circuit 13, described non-overlapping delay circuit 13 determines that non-overlapping postpones jointly, clock frequency is obtained by circuit of clock frequency 14, described clock frequency and non-overlapping postpone separate, therefore, as long as clock frequency is stablized, the non-overlapping time between four phase places just can keep stable, thus produces stable non-overlapping four phase clock signal.

The first end of described circuit of clock frequency 14 is connected with described bias voltage circuit 11, second end is connected with described enable control circuit 12,3rd end is connected with described non-overlapping delay circuit 13, and described circuit of clock frequency is for generation of the clock frequency controlling non-overlapping four phase signal.

Described circuit of clock frequency 14 by changing the electric capacity of circuit interior joint at different levels, can change the discharge and recharge time of the node of circuit at different levels in clock frequency, thus controls clock frequency.

Non-overlapping four phase clock that the embodiment of the present invention one provides produces circuit, the time delay of non-overlapping four phase signal is controlled by non-overlapping delay circuit, the clock frequency that non-overlapping four phase clock produces circuit is controlled by circuit of clock frequency, make can separately to set between non-overlapping time and clock frequency, as long as clock frequency is stablized, the non-overlapping time between four phase places just can keep good stability, do not fluctuate with mains fluctuations, thus produce stable non-overlapping four phase clock signal do not changed with mains fluctuations.

Embodiment two

Fig. 3-Fig. 6 is the structural drawing of a kind of non-overlapping four phase clock generation circuit that the embodiment of the present invention two provides, this embodiment is based on above-described embodiment, described non-overlapping four phase clock produces circuit and comprises bias voltage circuit 11, enable control circuit 12, non-overlapping delay circuit 13 and circuit of clock frequency 14, wherein, described bias voltage circuit 11 comprises the first bias voltage circuit 111 and the second bias voltage circuit 112.

In the present embodiment, first bias voltage circuit 111 is for providing the first bias voltage VBP for non-overlapping delay circuit 13 and circuit of clock frequency 14, second bias voltage circuit 112 is for providing the second bias voltage VBN for non-overlapping delay circuit 13 and circuit of clock frequency 14, each bias voltage circuit can be made up of metal-oxide-semiconductor and constant current source, to improve bias voltage.The form of described first bias voltage circuit and the second bias voltage circuit has multiple, Fig. 3 is the structural drawing that a kind of non-overlapping four phase clock of providing of second embodiment of the invention produces bias voltage circuit described in circuit, as shown in Figure 3, the first bias voltage circuit 111 in described bias voltage circuit 11 can comprise the first PMOS P1 and the first constant current source D1, wherein

The source electrode of described first PMOS P1 is connected with power vd D, the drain electrode of the first PMOS P1 is connected with the first end of the first constant current source D1, the grid of the first PMOS P1 is connected with non-overlapping delay circuit 13 and circuit of clock frequency 14, the substrate of described first PMOS P1 meets power vd D, the second end ground connection of described first constant current source D1, described first bias voltage circuit 111 is for exporting the first bias voltage VBP.

Described second bias voltage circuit 112 can comprise the first NMOS tube N1 and the second constant current source D2, wherein,

The drain electrode of described first NMOS tube N1 is connected with second end of the second constant current source D2, the source electrode of the first NMOS tube N1 and Substrate ground, the grid of the first NMOS tube N1 is connected with non-overlapping delay circuit 13 and circuit of clock frequency 14, and the first end of the second constant current source D2 is connected with power vd D.

Because the first constant current source D1 and the second constant current source D2 can provide fixed current, there is again very big internal resistance, therefore, be often used in electronic circuit and be used to provide stable bias voltage, greatly can improve stability and the output gain of circuit.

By controlling the size of current of the first constant current source D1 and the second constant current source D2, the first bias voltage VBP of the first bias voltage circuit 111 and the generation of the second bias voltage circuit 112 and the size of the second bias voltage VBN can be controlled.

It should be noted that, the mode that described first constant current source D1 and the second constant current source D2 produces steady current can have multiple method, and be not restricted to a certain concrete circuit form, as long as steady current required for the present invention can be produced, such as, the circuit of the first constant current source D1 and the second constant current source D2 can pass through bipolar junction transistor (BipolarJunctionTransistor, be called for short BJT) or metal-oxide layer semiconductcor field effect transistor (Metal-Oxide-SemiconductorField-EffectTransistor, be called for short MOSFET) realize, the technology that constant current source produces steady current is prior art, do not repeat them here.

In the present embodiment, enable control circuit is used for the clock frequency control non-overlapping delay circuit exported according to enable signal and circuit of clock frequency, Fig. 4 is the structural drawing that a kind of non-overlapping four phase clock of providing of second embodiment of the invention produces enable control circuit described in circuit, as shown in Figure 4, described enable control circuit 12 can comprise first input end IN1, the second input end EN, the first NAND gate circuit AND1, the first phase inverter INVO1, the first output terminal OUT1 and the second output terminal ENB, wherein

Described first input end IN1 is connected with the first input end of circuit of clock frequency 14 and the first NAND gate circuit AND1, second input end EN is connected with second input end of the first NAND gate circuit AND1 and the input end of the first phase inverter INVO1, second input end EN is enable signal input end, for inputting enable signal, the output terminal of the first phase inverter INVO is the second output terminal ENB, for exporting reverse enable signal, the output terminal of the first NAND gate circuit AND1 is the first output terminal OUT1, is connected with described non-overlapping delay circuit 13.

It should be noted that, the second input end EN in described enable control circuit 12 is used for the enable signal that input control non-overlapping four phase clock produces circuit, when the circuit is operating, described second input end EN input high level, when circuit does not work, described second input end EN input low level, and the clock period of non-overlapping delay circuit is controlled by described circuit of clock frequency 14.

In the present embodiment, described non-overlapping delay circuit 13 is for generation of non-overlapping four phase signal, Fig. 5 a-Fig. 5 c is the structural drawing that a kind of non-overlapping four phase clock of providing of the embodiment of the present invention two produces non-overlapping delay circuit described in circuit, as shown in Figure 5 a, described non-overlapping delay circuit 13 can comprise first order circuit 131, second level circuit 132, tertiary circuit 133, fourth stage circuit 134, second phase inverter INVO2, 3rd phase inverter INVO3, 4th phase inverter INVO4, 5th phase inverter INVO5, hex inverter INVO6, 7th phase inverter INVO7, 8th phase inverter INVO8, 9th phase inverter INVO9, tenth phase inverter INVO10, 11 phase inverter INVO11, 12 phase inverter INVO12, 13 phase inverter INVO13, 14 phase inverter INVO14, 15 phase inverter INVO15, first OR-NOT circuit OR1, second OR-NOT circuit OR2, second NAND gate circuit AND2 and the 3rd NAND gate circuit AND3.

A kind of non-overlapping four phase clock that Fig. 5 a provides for the embodiment of the present invention two produces the structural drawing of circuit at different levels in non-overlapping delay circuit described in circuit, as shown in Figure 5 a, described first order circuit 131 is connected between the output terminal of second level circuit 132 and enable control circuit 12, particularly, between the first output terminal OUT1 that can be connected to enable control circuit in second level circuit 132 and Fig. 4, the mid point of first order circuit 131 and second level circuit 132 line is first order node NI1; Described second level circuit 132 is connected between first order circuit 131 and tertiary circuit 133, and the mid point of second level circuit 132 and tertiary circuit 133 line is second level node NI2; Described tertiary circuit 133 is connected between second level circuit 132 and fourth stage circuit 134, and the mid point of tertiary circuit 133 and fourth stage circuit 134 line is third level node NI3; Described fourth stage circuit 134 is connected between tertiary circuit 133 and circuit of clock frequency 14, and the mid point of fourth stage circuit 134 and circuit of clock frequency 14 line is fourth stage node NI4.

A kind of non-overlapping four phase clock that Fig. 5 b provides for the embodiment of the present invention two produces circuit at different levels in non-overlapping delay circuit described in circuit and exports the circuit structure diagram of each clock signal, as shown in Figure 5 b, described first node NI1 is connected with two phase inverters of connecting, the first reverse clock signal clk B1 is generated through the second phase inverter INVO2, the first clock signal clk 1 is generated through the 3rd phase inverter INVO3, second level node NI2 is by being connected with two phase inverters of connecting, the second reverse clock signal clk B2 is generated through the 4th phase inverter INVO4, second clock signal CLK2 is generated through the 5th phase inverter INVO5, third level node NI3 is connected with the input end of hex inverter INVO6, the output terminal of hex inverter INVO6 is for exporting the 3rd reverse clock signal clk B3, the output terminal of hex inverter INVO6 is connected with the input end of the 7th phase inverter INVO7, the output terminal of the 7th phase inverter INVO7 is for exporting the 3rd clock signal clk 3, fourth stage node NI4 is connected with the input end of the 8th phase inverter INVO8, the output terminal of the 8th phase inverter INVO8 is for exporting the 4th reverse clock signal clk B4, the output terminal of the 8th phase inverter INVO8 is connected with the input end of the 9th phase inverter INVO9, the output terminal of the 9th phase inverter is for exporting the 4th clock signal clk 4.

A kind of non-overlapping four phase clock that Fig. 5 c provides for the embodiment of the present invention two produces circuit at different levels in non-overlapping delay circuit described in circuit and exports the circuit structure diagram of four phase clock signals, as shown in Figure 5 c, the first input end of described first OR-NOT circuit OR1 is connected with the output terminal of the 4th phase inverter INVO4, second input end of the first OR-NOT circuit OR1 is connected with the output terminal of the 7th phase inverter INVO7, the output terminal of the first OR-NOT circuit OR1 is connected with the input end of the tenth phase inverter INVO10, the output terminal of the tenth phase inverter INVO10 is for exporting the one or four phase clock signal PCLK1.Namely the second reverse clock signal clk B2 of second level node NI2 output and the 3rd clock signal clk 3 of third level node NI3 output export first phase clock signal PCLK1 after the first OR-NOT circuit OR1.

The first input end of described second NAND gate circuit AND2 is connected with the output terminal of the 4th phase inverter INVO4, second input end of the first OR-NOT circuit OR1 is connected with the output terminal of the 7th phase inverter INVO7, the output terminal of the second NAND gate circuit AND2 is connected with the input end of the 11 phase inverter INVO11, the output terminal of the 11 phase inverter INVO11 is connected with the input end of described 12 phase inverter INVO12, and the output terminal of the 12 phase inverter INVO12 is for exporting the two or four phase clock signal PCLK2.Namely the second reverse clock signal clk B2 of second level node NI2 output and the 3rd clock signal clk 3 of third level node NI3 output export second phase clock signal PCLK2 after the second NAND gate circuit AND2.

The first input end of described second OR-NOT circuit OR2 is connected with the output terminal of the 3rd phase inverter INVO3, second input end of the second OR-NOT circuit OR2 is connected with the output terminal of the 8th phase inverter INVO8, the output terminal of the second OR-NOT circuit OR2 is connected with the input end of the 13 phase inverter INVO13, the output terminal INVO13 of the 13 phase inverter is connected with the input end of the 14 phase inverter INVO14, and the output terminal of the 14 phase inverter INVO14 is for exporting third phase clock signal PCLK3.Namely the first clock signal clk 1 of first order node NI1 output and the 4th reverse clock signal clk B4 of fourth stage node NI4 output export third phase clock signal PCLK3 after the second OR-NOT circuit OR2.

The first input end of described 3rd NAND gate circuit AND3 is connected with the output terminal of the 3rd phase inverter INVO3, second input end of the 3rd NAND gate circuit AND3 is connected with the output terminal of the 8th phase inverter INVO8,3rd NAND gate circuit AND3 output terminal is connected with the input end of the 15 phase inverter INVO15, and the output terminal of the 15 phase inverter INVO15 is for exporting the 4th phase clock signal PCLK4.Namely the first clock signal clk 1 of first order node NI1 output and the 4th reverse clock signal clk B4 of fourth stage node NI4 output export the 4th phase clock signal PCLK4 after the 3rd NAND gate circuit AND3.

It should be noted that, above by the size of stray capacitance in the size of constant current source in change first biasing circuit 111 and the second biasing circuit 112 and/or first order node NI1, second level node NI2, third level node NI3 and fourth stage node NI4 circuit at different levels, decide the time delay of the clock signal that node at different levels exports.

Concrete preferred, described first order circuit 131 can comprise the second PMOS P2, the 3rd PMOS P3, the second NMOS tube N2 and the 3rd NMOS tube N3.

Wherein, the grid of described second PMOS P2 is for receiving the first bias voltage VBP of the first bias voltage circuit 111 generation, particularly, the grid of the second PMOS can be connected with the grid of the first PMOS in the first bias voltage circuit in Fig. 1, the source electrode of described second PMOS P2 is connected with power vd D, the drain electrode of the second PMOS P2 is connected with the source electrode of the 3rd PMOS P3, the substrate of the second PMOS P2 is connected with the substrate of the 3rd PMOS P3 and power vd D, the grid of the 3rd PMOS P3 is connected with the output terminal of enable control circuit 22, particularly, can be connected with the first output terminal OUT1 of control circuit 22 enable in Fig. 4, the drain electrode of the 3rd PMOS P3 is connected with the drain electrode of the second NMOS tube N2, the grid of the second NMOS tube N2 is connected with the grid of the 3rd PMOS P3, the source electrode of the second NMOS tube N2 is connected with the drain electrode of the 3rd NMOS tube N3, the Substrate ground of the second NMOS tube N2, the grid of the 3rd NMOS tube N3 is for receiving the second bias voltage VBN of the second bias voltage circuit 112 generation, particularly, can be connected with the grid of the first NMOS tube N1, the source ground of the 3rd NMOS tube N3, the Substrate ground of described 3rd NMOS tube N3,

Described second level circuit 132 comprises the 4th PMOS P4, the 5th PMOS P5, the 4th NMOS tube N4, the 5th NMOS tube N5 and the 6th NMOS tube N6, wherein,

The grid of the 4th PMOS N4 is for receiving the first bias voltage VBP, particularly, can be connected with the grid of the first PMOS in Fig. 1, for inputting the first bias voltage VBP, the source electrode of the 4th PMOS P4 is connected with power vd D, the drain electrode of the 4th PMOS P4 is connected with the source electrode of the 5th PMOS P5, the substrate of the 4th PMOS P4 is connected with the substrate of the 5th PMOS P5 and power vd D, the grid of the 5th PMOS P5 is connected with the grid of the 4th NMOS tube N4, in the mid point of the grid of the 5th PMOS P5 and the gate trace of the 4th NMOS tube N4 and first order circuit 231, the mid point of the mid point line of the drain electrode of the 3rd PMOS P3 and the drain electrode line of the second NMOS tube N2 is as first order node NI1, the drain electrode of the 5th PMOS P5 is connected with the drain electrode of the 4th NMOS tube N4, the source electrode of the 4th NMOS tube N4 is connected with the source electrode of the 6th NMOS tube N6, the Substrate ground of the 4th NMOS tube N4, the grid of the 5th NMOS tube N5 is for receiving the reverse enable signal ENB of enable control circuit 22 output, particularly, can be connected with the second output terminal ENB of control circuit enable in Fig. 4, the drain electrode of the 5th NMOS tube N5 is connected with the grid of the grid of the 4th NMOS tube N4 and the 5th PMOS P5, the source electrode of the 5th NMOS tube N5 and Substrate ground, the grid of the 6th NMOS tube N6 is for receiving the second bias voltage VBN of the second bias voltage circuit 112 generation, particularly, can be connected with the grid of the first NMOS tube N1 in the second bias voltage circuit 112 in Fig. 1, the source electrode of the 6th NMOS tube N6 and Substrate ground,

Described tertiary circuit 133 comprises the 6th PMOS P6, the 7th PMOS P7, the 8th PMOS P8, the 7th NMOS tube N7 and the 8th NMOS tube N8, wherein,

The grid of the 6th PMOS P6 is for receiving enable signal EN, particularly, can be connected with the second input end EN of control circuit enable in Fig. 4, the source electrode of the 6th PMOS P6 is connected with power vd D, the drain electrode of the 6th PMOS P6 is connected with the grid of the 8th PMOS P8, the Substrate ground of the 6th PMOS P6, the source electrode of the 7th PMOS P7 is connected with power vd D with substrate, the grid of the 7th PMOS P7 is for receiving the first bias voltage VBP of the first bias voltage circuit 111 generation, particularly, can be connected with the grid of the first PMOS, for inputting the first bias voltage VBP, the drain electrode of the 7th PMOS P7 is connected with the source electrode of the 8th PMOS P8, the substrate of the 7th PMOS P7 is connected with the substrate of the 8th PMOS P8 and power vd D, the drain electrode of the 8th PMOS P8 is connected with the drain electrode of the 7th NMOS tube N7, the mid point that the mid point of the drain electrode of the 8th PMOS P8 and the mid point of the drain electrode line of the 7th NMOS tube N7 and the drain electrode of the 5th PMOS P5 in second level circuit 232 and the drain electrode line of the 4th NMOS tube N4 is connected is as second level node NI2, the grid of the 7th NMOS tube N7 is connected with the grid of the 8th PMOS P8, the source electrode of the 7th NMOS tube N7 is connected with the drain electrode of the 8th NMOS tube N8, the Substrate ground of the 7th NMOS tube N7, the grid of the 8th NMOS tube N8 is for receiving the second bias voltage VBN of the second bias voltage circuit 112 generation, particularly, can the grid of the first NMOS tube N1 in Fig. 1 in the second bias voltage circuit 112 connect, the source electrode of the 8th NMOS tube N8 and Substrate ground,

Described fourth stage circuit 134 comprises the 9th PMOS P9, the tenth PMOS P10, the tenth NMOS tube N10 and the 11 NMOS tube N11, wherein,

The grid of the 9th PMOS N9 is for receiving the first bias voltage VBP of the first bias voltage circuit 111 generation, particularly, can be connected with the grid of the first PMOS in Fig. 1, the source electrode of the 9th PMOS P9 is connected with the substrate of the tenth PMOS P10 and power vd D, the drain electrode of the 9th PMOS P9 is connected with the source electrode of the tenth PMOS P10, the grid of the tenth PMOS P10 is connected with the grid of the tenth NMOS tube N10, the mid point that the mid point of the grid of the tenth PMOS P10 and the drain electrode of the 8th PMOS P8 in the mid point of the gate trace of the tenth NMOS tube N10 and tertiary circuit 133 and the drain electrode line of the 7th NMOS tube P7 is connected is as third level node NI3, the drain electrode of the tenth PMOS P10 is connected with the drain electrode of the tenth NMOS tube N10, tenth NMOS tube N10 source electrode is connected with the drain electrode of the 11 NMOS tube N11, the mid point of the source electrode of the tenth PMOS P10 and the drain electrode line of the 11 NMOS tube N11 and the mid point of described circuit of clock frequency 14 line are as fourth stage node NI4, the Substrate ground of the tenth NMOS tube N10, the grid of the 9th NMOS tube N9 is for receiving the reverse enable signal ENB of enable control circuit 12 output, particularly, can be connected with the second output terminal ENB in Fig. 4, the drain electrode of the 9th NMOS tube N9 is connected with the grid of the tenth NMOS tube N10, the source ground of the 9th NMOS tube N9, the substrate of the 9th NMOS tube N9 is connected with the source electrode of the 9th NMOS tube N9, the grid of the 11 NMOS tube N11 is for receiving the second bias voltage VBN of the second bias voltage circuit 112 generation, particularly, the grid of the 11 NMOS tube can be connected with the grid of the first NMOS tube N1, the source electrode of the 11 NMOS tube N11 and Substrate ground.

It should be noted that, the first clock signal clk 1 that described first order node NI1, second level node NI2, third level node NI3 and fourth stage node NI4 place generate respectively, second clock signal CLK2, time delay between the 3rd clock signal clk 3 and the 4th clock signal clk 4, by regulating the size of current of the first constant current source D1 and the second constant current source D2, thus the size of the first bias voltage VBP and the second bias voltage VBN can be controlled, and then the size of the charging and discharging currents to node NI1, NI2, NI3 and NI4 can be controlled; In addition, in first order circuit 131 to fourth stage circuit 134, in circuit at different levels there is stray capacitance in metal-oxide-semiconductor itself, by controlling the size of current of the first constant current source D1 and the second constant current source, regulate the stray capacitance of metal-oxide-semiconductor in circuit at different levels again, thus the first clock signal clk 1, second clock signal CLK2, time delay between the 3rd clock signal clk 3 and the 4th clock signal clk 4 can be regulated.

Described circuit of clock frequency 14 is for generation of the clock frequency controlling non-overlapping four phase signal, Fig. 6 is the structural drawing of a kind of non-overlapping four phase clock of providing of the embodiment of the present invention two frequency circuit when producing described in circuit, as shown in Figure 6, circuit of clock frequency 14 comprises level V circuit 141 and the 6th grade of circuit 142.

Described level V circuit 141 is connected between fourth stage circuit 134 and the 6th grade of circuit 142, and the mid point of described level V circuit 141 and the 6th grade of circuit 142 line is level V node NI5.

6th grade of circuit 142 is connected between level V circuit 141 and enable control circuit 12, particularly, between the first input end IN1 that can be connected to enable control circuit in level V circuit 141 and Fig. 4, the mid point of the first input end IN1 line of the 6th grade of circuit 142 and enable control circuit 12 is the 6th grade of node NI6.

Described circuit of clock frequency 14 produces clock frequency by level V circuit 141 and the 6th grade of circuit 142 and controls the clock frequency that whole non-overlapping four phase clock produces circuit.

Particularly, described level V circuit 141 and the 6th grade of circuit 142 produce clock frequency by following circuit.Described level V circuit 141 comprises the 11 PMOS P11, the 12 PMOS P12, the 13 PMOS P13, the 12 NMOS tube N12, the 13 NMOS tube N13 and the first electric capacity C1.

The grid of described 11 PMOS P11 is for receiving enable signal EN, particularly, can be connected with the second input end EN of control circuit enable in Fig. 4, the source electrode of the 11 PMOS P11 is connected with the substrate of the 11 PMOS P11 and power vd D, the drain electrode of the 11 PMOS P11 is connected with the grid of the 13 PMOS P13, the grid of the 12 PMOS P12 is connected with the grid of the first PMOS P1, the source electrode of the 12 PMOS P12 is connected with power vd D, the drain electrode of the 12 PMOS P12 is connected with the source electrode of the 13 PMOS P13, the substrate of the 12 PMOS P12 is connected with the substrate of the 13 PMOS P13 and power vd D, the drain electrode of the 13 PMOS P13 is connected with the drain electrode of the 12 NMOS tube N12, the source electrode of the 12 NMOS tube N12 is connected with the drain electrode of the 13 NMOS tube N13, the Substrate ground of the 12 NMOS tube N12, the grid of the 13 NMOS tube N13 is for receiving the second bias voltage VBN of the second bias voltage circuit 112 generation, particularly, can be connected with the grid of the first NMOS tube in Fig. 1, the source electrode of the 13 NMOS tube N13 and Substrate ground, the first end of described first electric capacity C1 is connected with level V node NI5, the second end ground connection of the first electric capacity C1,

Described 6th grade of circuit 142 comprises the 14 PMOS P14, the 15 PMOS P15, the 16 PMOS P16, the 14 NMOS tube N14, the 15 NMOS tube N15, the 16 NMOS tube N16 and the second electric capacity C2.

The grid of described 14 PMOS P14 is for receiving the first bias voltage VBP of the first bias voltage circuit 111 generation, particularly, can be connected with the grid of the first PMOS in Fig. 1, the source electrode of the 14 PMOS P14 is connected with power vd D, the drain electrode of the 14 PMOS P14 is connected with the source electrode of the 15 PMOS P15, the substrate of the 14 PMOS P14 is connected with the substrate of the 15 PMOS P15 and power vd D, the grid of the 15 PMOS P15 is connected with the grid of the 15 NMOS tube N15, the mid point that the grid of the 15 PMOS P15 and the line of the grid of the 15 NMOS tube N15 and the drain electrode of the 13 PMOS P13 in level V circuit 141 are connected with the line of the source electrode of the 12 NMOS tube N12 is as level V node NI5, the grid of the 14 NMOS tube N14 with for receiving the reverse enable signal ENB that enable control circuit exports, particularly, can be connected with the second output terminal ENB of control circuit enable in Fig. 4, the drain electrode of the 14 NMOS tube N14 is connected with the grid of the 15 NMOS tube N15, the source ground of the 14 NMOS tube N14, the substrate of the 14 NMOS tube N14 is connected with the source electrode of the 14 NMOS tube N14, the source electrode of the 15 NMOS tube N15 is connected with the drain electrode of the 16 NMOS tube N16, the Substrate ground of the 15 NMOS tube N15, the grid of the 16 NMOS tube N16 is for receiving the second bias voltage VBN of the second bias voltage circuit 112 generation, particularly, can be connected with the grid of the first NMOS tube in Fig. 1, the source electrode of the 16 NMOS tube N16 and Substrate ground, the mid point of the drain electrode of the 15 PMOS P15 and the drain electrode line of the 15 NMOS tube N15 and the mid point of enable control circuit 12 line are the 6th grade of node NI6, particularly, the mid point of the mid point of the drain electrode of the 15 PMOS P15 and the drain electrode line of the 15 NMOS tube N15 and the first input end IN1 line of enable control circuit 12 is the 6th grade of node NI6, the first end of the second electric capacity C2 is connected with the 6th grade of node NI6, the second end ground connection of the second electric capacity C2, the source electrode of the 16 PMOS P16 is connected with substrate and power vd D, the grid of the 16 PMOS P16 is for receiving enable signal EN, particularly, can be connected with the second input end EN in Fig. 4, the drain electrode of the 16 PMOS P16 is connected with the mid point of the 6th grade of node NI6 and enable control circuit 12 line.

Described first electric capacity C1 and the second electric capacity C2 can comprise in mos capacitance, MIM capacitor, PIP capacitor or MIP electric capacity any one.

It should be noted that, in circuit of clock frequency 14, the first electric capacity C1 and the second electric capacity C2 forms oscillator with each metal-oxide-semiconductor in level V circuit 141 and the 6th grade of circuit 142 respectively, by changing the size of the first electric capacity C1 or the second electric capacity C2, just can the clock frequency of regulation output, thus control the cycle of each clock signal in non-overlapping delay circuit 13.

Fig. 7 is the sequential chart that a kind of non-overlapping four phase clock of providing of the embodiment of the present invention two produces each clock signal and each phase clock signal in circuit, as shown in Figure 7.

First clock signal clk 1, second clock signal CLK2, occurred delay between the 3rd clock signal clk 3 and the 4th clock signal clk 4, this time delay is determined by the size of the stray capacitance of the first constant current source D1 and the second constant current source TD and first order node NI1, second level node NI2, third level node NI3 and fourth stage node NI4; The clock frequency of the first clock signal clk 1, second clock signal CLK2, the 3rd clock signal clk 3 and the 4th clock signal clk 4 is decided by the first electric capacity C1 of level V node NI5 and the 6th grade node NI6 and the size of the second electric capacity C2, therefore, by changing the size of the electric capacity at level V node NI5 and the 6th grade of node NI6 place, the clock frequency of the first clock signal clk 1 to the four clock signal clk 4 just can be regulated.

See Fig. 7, within the T1 time period, first clock signal clk 1 is high level, second clock signal CLK2, 3rd clock signal clk 3 and the 4th clock signal clk 4 are low level, therefore the one or the four phase clock signal PCLK1 that the first reverse clock signal clk B1 and the 3rd clock signal clk 3 export after the first OR-NOT circuit OR1 is low level, the two or the four phase clock signal PCLK2 exported after the second NAND gate circuit AND2 is high level, the three or the four phase clock signal PCLK3 that first clock signal clk 1 and the 4th reverse clock signal clk B4 export after the second OR-NOT circuit OR2 is low level, the four or the four phase clock signal PCLK4 exported after the 3rd NAND gate circuit AND3 is low level.

In the T2 time period, described second clock signal CLK2 becomes high level after the delay of T1 time, corresponding, one or four phase clock signal PCLK1 and the two or four phase clock signal PCLK2 becomes high level, and the three or four phase clock signal PCLK3 and the four or four phase clock signal PCLK4 keeps the waveform in the T1 time period constant.

In the T3 time period, described 3rd clock signal clk 3 becomes high level after the delay of T2 time, described two or four phase clock signal PCLK2 becomes low level, and the one or four phase clock signal PCLK1, the three or four phase clock signal PCLK3 and the four or four phase clock signal PCLK4 keep the waveform in the T2 time period constant.

In the T4 time period, 4th clock signal clk 4 becomes high level after the delay of T3 time, four or four phase clock signal PCLK4 becomes high level, and the one or four phase clock signal PCLK1, the two or four phase clock signal PCLK2 and the three or four phase clock signal PCLK3 keep the waveform in the T3 time period constant.

The like, when the clock frequency that circuit of clock frequency 14 produces is stablized, non-overlapping time of non-overlapping four phase clock signal that non-overlapping delay circuit 13 produces just can keep stable, and it doesn't matter with the fluctuation of supply voltage.

In a preferred embodiment of the present embodiment, described first order circuit 131, second level circuit 132, tertiary circuit 133 and fourth stage circuit 134 in described non-overlapping delay circuit 13 also comprise at least one electric capacity respectively, the first end of described at least one electric capacity is connected with any first nodes in described first order node NI1, second level node NI2, third level node NI3 and fourth stage node NI4, the second end ground connection of described at least one electric capacity.Preferably, described at least one electric capacity can comprise any one in mos capacitance, MIM capacitor, PIP capacitor or MIP electric capacity.

In the preferred embodiment of the present embodiment, longer when the non-overlapping time required by non-overlapping delay circuit 13, and when in first order circuit 131, second level circuit 132, tertiary circuit 133 and fourth stage circuit 134, the stray capacitance of metal-oxide-semiconductor itself is less, discharge and recharge in circuit at different levels is terminated very soon, thus the longer non-overlapping time can not be ensured, the discharge and recharge time of circuit at different levels can be extended by increasing electric capacity, thus extend the non-overlapping time.

In another preferred embodiment of the present embodiment, described circuit of clock frequency 14 can also comprise at least stage circuit, and described at least stage circuit is connected between described level V circuit 141 and the 6th grade of circuit 142 in turn.

All at least stage circuit are in order to decide the clock frequency of described circuit of clock frequency 14 with described level V circuit 141 and the 6th grade of circuit 142 acting in conjunction.Described at least stage circuit comprises at least one PMOS, at least one NMOS tube and an electric capacity, and circuit structure is identical with the structure of the 6th grade of circuit 142 with level V circuit 141.

Non-overlapping four phase clock that the embodiment of the present invention two provides produces circuit, the time delay of non-overlapping four phase signal is controlled by non-overlapping delay circuit, the clock frequency that non-overlapping four phase clock produces circuit is controlled by circuit of clock frequency, make can separately to set between non-overlapping time and clock frequency, as long as clock frequency is stablized, the non-overlapping time between four phase places just can keep stable, do not fluctuate with mains fluctuations, thus produce stable non-overlapping four phase clock signal do not changed with mains fluctuations.

The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, to those skilled in the art, the present invention can have various change and change.All do within spirit of the present invention and principle any amendment, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims

1. non-overlapping four phase clock produces a circuit, and it is characterized in that, described circuit comprises bias voltage circuit, enable control circuit, non-overlapping delay circuit and circuit of clock frequency, wherein,

2. non-overlapping four phase clock according to claim 1 produces circuit, it is characterized in that, described non-overlapping delay circuit comprises first order circuit, second level circuit, tertiary circuit, fourth stage circuit, second phase inverter, 3rd phase inverter, 4th phase inverter, 5th phase inverter, hex inverter, 7th phase inverter, 8th phase inverter, 9th phase inverter, tenth phase inverter, 11 phase inverter, 12 phase inverter, 13 phase inverter, 14 phase inverter, 15 phase inverter, first OR-NOT circuit, second OR-NOT circuit, second NAND gate circuit and the 3rd NAND gate circuit, wherein,

3. non-overlapping four phase clock according to claim 2 produces circuit, and it is characterized in that, described first order circuit comprises the second PMOS, the 3rd PMOS, the second NMOS tube and the 3rd NMOS tube, wherein,

4. non-overlapping four phase clock according to claim 1 produces circuit, and it is characterized in that, described circuit of clock frequency comprises level V circuit and the 6th grade of circuit, wherein,

5. non-overlapping four phase clock according to claim 4 produces circuit, and it is characterized in that, described level V circuit comprises the 11 PMOS, the 12 PMOS, the 13 PMOS, the 12 NMOS tube, the 13 NMOS tube and the first electric capacity, wherein,

6. non-overlapping four phase clock according to claim 3 produces circuit, it is characterized in that, described first order circuit, second level circuit, tertiary circuit and fourth stage circuit also comprise at least one electric capacity respectively, the first end of described at least one electric capacity is connected with any first nodes in described first order node, second level node, third level node and fourth stage node, the second end ground connection of described at least one electric capacity.

7. non-overlapping four phase clock according to claim 5 or 6 produces circuit, it is characterized in that, described first electric capacity, the second electric capacity and at least one electric capacity comprise in mos capacitance, MIM capacitor, PIP capacitor and MIP electric capacity any one.

8. non-overlapping four phase clock according to claim 4 produces circuit, and it is characterized in that, described circuit of clock frequency also comprises at least stage circuit, and described at least stage circuit is connected between described level V circuit and the 6th grade of circuit in turn.