CN202616995U - Charge pump and liquid crystal display driving chip - Google Patents

Abstract

A charge pump and a liquid crystal display driver chip. The charge pump includes: first and second capacitors; a first charging branch and a second charging branch. When the first clock is valid, the first charging branch charges the first capacitor. When the second clock is valid, the second charging branch charges the second capacitor. Capacitor charging, the first and second clocks are a pair of non-overlapping clocks; the first boost branch and the second boost branch, when the second clock is valid, the first boost branch raises the upper plate voltage of the first capacitor and External output, when the first clock is valid, the second boost branch lifts the upper plate voltage of the second capacitor and outputs it to the outside; the first capacitor connected to the lower plate of the first capacitor and the lower plate of the second capacitor controlled by the third clock Switch, the third clock is valid when both the first and second clocks are invalid, and does not overlap with the first clock and the second clock. When the third clock is valid, the charge can be shared between the first capacitor and the second capacitor . The charge pump has high conversion efficiency and small ripple. The liquid crystal display driver chip includes the above-mentioned charge pump.

Description

Charge pump and LCD driver chip

technical field

The utility model relates to a voltage converter, in particular to a charge pump and a liquid crystal display drive chip. the

Background technique

A charge pump is a DC-DC (converter) that uses so-called "flying" or "pumping" capacitors (rather than inductors or transformers) to store energy. Its internal transistor switch array controls the charging and discharging of the flying capacitor in a certain way, so that the power supply voltage is multiplied or reduced by a certain factor (for example: -1, 2 or 3), so as to obtain the required output voltage. the

Various charge pump circuits are known in the prior art. FIG. 1 is a schematic circuit diagram of a common voltage doubler charge pump in the prior art. The prior art charge pump comprises four switches S1, S2, S3, S4 and a capacitor C1. As shown in Figure 2, the switches S1 and S2 are controlled by the first clock, and the switches S3 and S4 are controlled by the second clock. The first and second clocks are a pair of non-overlapping clocks, which avoids simultaneous A valid situation occurs. One end of the switch S1 inputs the Vcc power supply voltage, and the other end is connected to the upper plate of the capacitor C1. One end of the switch S2 is connected to the lower plate of the capacitor C1, and the other end is grounded. The charging circuit composed of switch S1, capacitor C1, and switch S2, when the first clock is active (when A in Figure 2), switches S1 and S2 are closed, switches S3 and S4 are opened, and capacitor C1 is charged to make its potential reach Vcc . One end of the switch S3 outputs Vout voltage, and the other end is connected to the upper plate of the capacitor C1. One end of the switch S4 is connected to the lower plate of the capacitor C1, and the other end is input with the Vcc power supply voltage. In the boost circuit composed of switch S3, capacitor C1 and switch S4, when the second clock is active (time B in Figure 2), switches S3 and S4 are closed, and switches S1 and S2 are open. Because the potential at both ends of the capacitor C1 cannot be changed immediately, the potential on the capacitor C1 is raised by Vcc, that is, the Vout output voltage jumps to twice the power supply voltage Vcc, realizing voltage doubling. The capacitor C2 is connected in series between the Vout output voltage terminal and the ground terminal, and is used to provide voltage to the load. Using this method can achieve voltage doubling. When the duty cycle of the clock signal is 50%, the energy efficiency conversion is the best. However, in the actual circuit, the first and second clocks will cause delays in the signal conversion and cannot reach So ideal. Moreover, in one clock cycle, only one phase outputs current, the energy efficiency is low, and the output ripple is large. the

At the same time, the reverse current will further reduce the energy efficiency of the charge pump. That is, when the clock signal turns from high to low or from low to high, the current flowing from the Vout output terminal to the Vcc power supply voltage is reversed due to delay. This current will further reduce the efficiency of the voltage doubler circuit. the

The charge pump is usually used to provide the power supply voltage for the internal circuit of the chip. More and more current chips use charge pump circuits with built-in on-chip capacitors to reduce external discrete components and reduce costs. Such a charge pump circuit is more difficult to obtain better energy efficiency and output ripple due to the limitation of the chip area. the

Utility model content

The technical problem to be solved by the utility model is to provide a charge pump with higher energy efficiency and smaller output ripple. the

In order to solve the above problems, the utility model provides a charge pump, including:

the first capacitor and the second capacitor;

The charging circuit includes a first charging branch and a second charging branch; the first charging branch is controlled by the first clock, and when the first clock is valid, the first capacitor is charged; the second charging branch is controlled by The second clock is controlled, and when the second clock is effective, the charging of the second capacitor is realized; the first and second clocks are a pair of non-overlapping clocks. the

And a boost circuit, including a first boost branch and a second boost branch; the first boost branch is controlled by the second clock, and when the second clock is valid, the upper plate of the first capacitor is raised The voltage is output to the outside; the second step-up branch is controlled by the first clock, and when the first clock is valid, the voltage on the upper plate of the second capacitor is raised and output to the outside. the

And the first switch connecting the lower plate of the first capacitor and the lower plate of the second capacitor is controlled by a third clock; the third clock is valid when both the first and second clocks are invalid, and is consistent with the first switch. The first clock and the second clock do not overlap each other; when the third clock is valid, the first switch is closed, so that the first capacitor and the second capacitor realize charge sharing. the

Optionally, the first charging branch includes: a second switch connected to the power supply voltage, a third switch connected to ground, and when the first clock is valid, the second and third switches are closed;

The second charging branch includes: a fourth switch connected to the power supply voltage, and a fifth switch connected to ground. When the second clock is active, the fourth and fifth switches are closed. the

Optionally, the first step-up branch includes: a sixth switch connected to the voltage output terminal of the charge pump, and a seventh switch connected to the power supply voltage. When the second clock is valid, the sixth and seventh switch closed;

The second step-up branch includes: an eighth switch connected to the voltage output terminal of the charge pump, and a ninth switch connected to the power supply voltage. When the first clock is active, the eighth and ninth switches are closed. the

Optionally, the second switch is a PMOS transistor, the source of which is connected to the power supply voltage, the gate receives the first clock, and the drain is connected to the upper plate of the first capacitor; the third switch is a NMOS transistor, its drain is connected to the lower plate of the first capacitor, the gate receives the reverse signal of the first clock, and the source is grounded;

The fourth switch is a PMOS transistor, its source is connected to the power supply voltage, the gate receives the second clock, and the drain is connected to the upper plate of the second capacitor; the fifth switch is an NMOS transistor, its The drain is connected to the lower plate of the second capacitor, the gate receives the reverse signal of the second clock, and the source is grounded. the

Optionally, the sixth switch is a PMOS transistor, its source is connected to the voltage output terminal of the charge pump, its gate receives the second clock, and its drain is connected to the upper plate of the first capacitor; The seven switches are a PMOS transistor, the drain of which is connected to the lower plate of the first capacitor, the gate receives the second clock, and the source is connected to the power supply voltage;

The eighth switch is a PMOS tube, its source is connected to the voltage output terminal of the charge pump, the grid receives the first clock, and the drain is connected to the upper plate of the second capacitor; the ninth switch is a The drain of the PMOS transistor is connected to the lower plate of the second capacitor, the gate receives the first clock, and the source is connected to the power supply voltage. the

Optionally, the sixth switch is a PMOS transistor, its source is connected to the voltage output terminal of the charge pump, its gate receives the second clock, and its drain is connected to the upper plate of the first capacitor; The seven switches are a PMOS transistor, the drain of which is connected to the lower plate of the first capacitor, the gate receives the second pre-stage clock signal, and the source is connected to the power supply voltage. After the second pre-stage clock signal is delayed , the second clock signal is obtained, and the second preceding clock does not overlap with the first clock; when the second clock is valid, the seventh switch is closed earlier than the sixth switch;

The eighth switch is a PMOS transistor, its source is connected to the voltage output terminal of the charge pump, the gate receives the first clock, and the drain is connected to the upper plate of the second capacitor; the ninth switch is a PMOS transistor, its drain is connected to the lower plate of the second capacitor, the gate receives the first previous stage clock signal, and the source is connected to the power supply voltage. After the first previous stage clock signal is delayed, the first stage clock signal is obtained. clock signal, and the first front-stage clock and the second clock do not overlap each other; when the first clock is valid, the ninth switch is closed before the eighth switch;

The third clock is valid when the first, first previous stage, second, and second previous stage clocks are all invalid, and during the effective period of the third clock, the first clock, the first previous stage clock, and the second clock , the second pre-stage clock are invalid. the

The utility model also provides a liquid crystal display driver chip, which includes any one of the above-mentioned charge pumps. the

Compared with the prior art, the utility model has the following advantages:

1. The first and second boost branches take turns to boost the voltage. While improving the energy efficiency of the charge pump and reducing the ripple, through a controlled switch, the first and second charging branches and the first and second charging branches The time gap when the two boost branches are not in an effective state realizes the charge sharing of the first and second capacitors and further improves energy efficiency. the

2. In the optional scheme, through the processing of the clock control signal of the boost branch, the two switches on the boost branch are closed sequentially during the boost, which effectively reduces the reverse current, improves energy efficiency, and reduces ripple. purpose of the wave. the

Description of drawings

FIG. 1 is a circuit diagram of a charge pump in the prior art. the

FIG. 2 is a waveform timing diagram of the clock signal of the charge pump in FIG. 1 . the

Fig. 3 is a circuit diagram of an embodiment of the utility model. the

FIG. 4 is a waveform timing diagram of the clock signal of the embodiment in FIG. 3 . the

Fig. 5 is a circuit diagram of another embodiment of the present utility model. the

FIG. 6 is a timing diagram of waveforms of clock signals in the embodiment of FIG. 5 . the

FIG. 7 is a schematic structural diagram of a liquid crystal display driver chip described in the present invention. the

Detailed ways

The following description and accompanying drawings will make the aforementioned features and advantages of the present utility model more apparent. A preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. the

FIG. 3 is a schematic circuit diagram of an embodiment of the present invention, and FIG. 4 is a waveform timing diagram of a clock signal corresponding to the embodiment of FIG. 3 . the

As shown in Figure 3, this embodiment includes a first charging branch 1a, a first boosting branch 1b, a second charging branch 2a, a second boosting branch 2b, a first capacitor C1, a second capacitor C2, and a connection to the first capacitor The lower plate of C1 and the first switch S1 of the lower plate of the second capacitor C2. The first clock CLK1 controls the first charging branch 1a and the second boosting branch 2b, and the second clock CLK2 controls the first boosting branch 1b and the second charging branch 2a. The third clock CLK3 controls the first switch S1. the

Specifically, the first charging branch 1a includes one end receiving the power supply voltage Vcc, the other end connected to the upper plate of the first capacitor C1 and the second switch S2 controlled by the first clock CLK1; one end connected to the lower electrode of the first capacitor C1 board, the other end is grounded and the third switch S3 is also controlled by the first clock CLK1. the

The first step-up branch 1b includes an output voltage Vout at one end, a sixth switch S6 connected to the upper plate of the first capacitor C1 at the other end and controlled by the second clock CLK2; one end is connected to the lower plate of the first capacitor C1, and the other end is connected to the lower plate of the first capacitor C1 One end is connected to the seventh switch S7 which is also controlled by the second clock CLK2 and is connected to the power supply voltage Vcc. the

The second charging branch 2a includes one end receiving the power supply voltage Vcc, the other end connected to the upper plate of the second capacitor C2 and the fourth switch S4 controlled by the second clock CLK2; one end connected to the lower plate of the second capacitor C2, and the other A fifth switch S5 with one end grounded and also controlled by the second clock CLK2. the

The second boost branch 2b includes an output voltage Vout at one end, an eighth switch S8 connected to the upper plate of the second capacitor C2 and controlled by the first clock CLK1 at the other end; one end is connected to the lower plate of the second capacitor C2, and the other end is connected to the lower plate of the second capacitor C2. One end is connected to the ninth switch S9 which is also controlled by the first clock CLK1 and is connected to the power supply voltage Vcc. the

It can be seen from FIG. 4 that the first and second clocks are a pair of non-overlapping clocks, that is, the two clocks are not valid at the same time. Referring to FIG. 3 , it is impossible for the first charging branch 1 a and the first boosting branch 1 b to work at the same time. Similarly, it is impossible for the second charging branch 2 a and the second boosting branch 2 b to work at the same time. When the first clock CLK1 is valid, the first charging branch 1a charges the first capacitor C1. At the same time, the second boost branch 2b implements a voltage doubled output to the second capacitor C2. When the second clock CLK2 is valid, the first boost branch 1b realizes the double voltage output to the first capacitor C1. At the same time, the second charging branch 2a charges the second capacitor C2. The third clock CLK3 is valid only when both the first and second clocks are invalid, and does not overlap with the first clock and the second clock, that is, when the third clock CLK3 is valid, the first charging branch 1a, the first charging The voltage branch 1b, the second charging branch 2a and the second boosting branch 2b are not working. At this time, the first switch S1 is closed, so that charge sharing is realized between the first capacitor C1 and the second capacitor C2, and the potentials are equalized. That is, when the next first and second clocks are valid, the boost branch does not need to start charging the lower plate of the branch capacitor from the ground potential, but starts charging from the balanced potential reached after the charge sharing between the capacitors, saving part of the power consumption . the

Specifically, at point A in FIG. 4 , the first clock CLK1 is valid, the second clock CLK2 is invalid, and the third clock CLK3 is invalid. At this time, the second switch S2 and the third switch S3 are closed, and the first charging branch 1a charges the first capacitor C1. At the same time, the eighth switch S8 and the ninth switch S9 are also closed, and the second boost branch 2b realizes the voltage doubled output to the second capacitor C2. Both the first boosting branch 1b and the second charging branch 2a are not working at this time. the

At point B in FIG. 4 , the second clock CLK2 is valid, the first clock CLK1 is invalid, and the third clock CLK3 is invalid. At this time, the sixth switch S6 and the seventh switch S7 are closed, and the first charging branch 1b realizes voltage doubled output to the first capacitor C1. At the same time, the fourth switch S4 and the fifth switch S5 are also closed, and the second charging branch 2a charges the second capacitor C2. Both the first charging branch 1a and the second boosting branch 2b are not working at this time. the

It can be seen from this that, unlike the prior art in which only one phase has a voltage doubler output in one clock cycle, the embodiment of the utility model can realize the voltage doubler output by two phases in turn within the same clock cycle, and the energy efficiency High, the output ripple is small. the

At point C in Figure 4, both the first clock CLK1 and the second clock CLK2 are invalid, that is, at this time, the two boost branches have no voltage doubler output, and the third clock CLK3 is valid, and it is the same as the first clock CLK1 and the second clock CLK2 do not overlap each other. At this time, the first switch S1 is closed, and the first capacitor C1 and the second capacitor C2 are connected to realize charge sharing between the two, thereby further improving energy efficiency. the

FIG. 5 is a schematic circuit diagram of another embodiment of the present invention, and FIG. 6 is a waveform timing diagram of a clock signal corresponding to the embodiment of FIG. 5 . the

The same part as the previous example will not be repeated here. the

The difference from the previous example is that in this example, not only the switches of each branch are replaced by transistors, but also the clock control signal of the boost branch is processed, so that the two switches on the boost branch are closed successively during boosting, effectively The reverse current is reduced to achieve the purpose of improving energy efficiency and reducing ripple. the

Specifically, the second switch S2 in the first charging branch 1a is a PMOS transistor, its source receives the power supply voltage Vcc, its gate receives the first clock CLK1, and its drain is connected to the upper plate of the first capacitor C1; The switch S3 is an NMOS transistor, its drain is connected to the lower plate of the first capacitor C1 , its gate receives the reverse signal CLK1b of the first clock, and its source is grounded. the

The fourth switch S4 in the second charging branch 2a is a PMOS transistor, the source of which receives the power supply voltage Vcc, the gate receives the second clock CLK2, and the drain is connected to the upper plate of the second capacitor C2; the fifth switch S5 is An NMOS transistor, the drain of which is connected to the lower plate of the second capacitor C2, the gate receives the reverse signal CLK2b of the second clock, and the source is grounded. the

The sixth switch S6 in the first step-up branch 1b is a PMOS transistor, its source doubles the voltage output Vout, the gate receives the second clock CLK2, and the drain is connected to the upper plate of the first capacitor C1; the seventh switch S7 It is a PMOS transistor, its drain is connected to the lower plate of the first capacitor C1, its gate receives the second pre-stage clock signal CLK2', and its source receives the power supply voltage Vcc. the

The eighth switch S8 in the second step-up branch 2b is a PMOS transistor, its source doubles the voltage output Vout, the gate receives the first clock CLK1, and the drain is connected to the upper plate of the second capacitor C2; the ninth switch S9 It is a PMOS transistor, its drain is connected to the lower plate of the second capacitor C2, its gate receives the first previous stage clock signal CLK1', and its source receives the power supply voltage Vcc. the

Each clock signal will be described below with reference to FIG. 6 . the

CLK1b, CLK1, and CLK1' are homologous signals. the

CLK1b is the signal obtained after inversion processing of CLK1. Because the Vgs of the PMOS transistor is active low and the Vgs of the NMOS transistor is active high, the first clock CLK1 controlling the PMOS transistor S2 is connected to the NMOS transistor S3 after inversion processing, which can ensure that S2 and S3 are turned on or off at the same time. the

CLK1' is the pre-stage signal of CLK1, and CLK1' is obtained after delay processing. This signal is used to control the on or off of the PMOS transistor S9. the

CLK2b, CLK2, and CLK2' are also homologous signals, CLK2b is the signal obtained after inverting CLK2, and CLK2' is the pre-stage signal of CLK2. Its function is similar to the above, and it is also to control the conduction or cut-off of the correspondingly connected MOS transistors, which will not be repeated here. the

CLK3 is valid when the first clock CLK1, the first previous-stage clock CLK1', the second clock CLK2, and the second previous-stage clock CLK2' are invalid, and when the third clock CLK3 is valid, the first clock CLK1, the first previous The stage clock CLK1 ′, the second clock CLK2 , and the second pre-stage clock CLK2 ′ are all invalid. the

Specifically, at point A in FIG. 6 , the first clock CLK1 is low, and the PMOS transistor S2 is turned on. At the same time, the first inverted clock CLK1b is high, and the NMOS transistor S3 is turned on. The first charging branch 1a charges the first capacitor C1. At the same time, the first pre-stage clock CLK1' is low, and the PMOS transistor S9 is turned on. The first clock CLK1 is low, and the PMOS transistor S8 is turned on. The second step-up branch 2b realizes doubled voltage output. Because the first pre-stage clock CLK1' is earlier than the first clock CLK1, the PMOS transistor S9 is turned on earlier than the PMOS transistor S8, that is, before the S8 is turned on to realize the double voltage output, the S9 is turned on, and the potential starts to increase. At that time, the potential difference between S8 and S9 is no longer the power supply voltage Vcc, but will be smaller than the power supply voltage Vcc because the potential is raised in advance. The direct effect is to effectively reduce the current flowing reversely from the Vout output terminal to the Vcc power supply voltage, further improving energy efficiency. At this time, the second clock CLK2 is invalid, and neither the first boosting branch 1b nor the second charging branch 2a work. The third clock CLK3 is invalid, and the first switch S1 is turned on. the

At point B in FIG. 6 , the second clock CLK2 is low, and the PMOS transistor S4 is turned on. At the same time, the first inverted clock CLK2b is high, and the NMOS transistor S5 is turned on. The second charging branch 2a charges the second capacitor C2. At the same time, the second pre-stage clock CLK2' is low, and the PMOS transistor S7 is turned on. The second clock CLK2 is low, and the PMOS transistor S6 is turned on. The first step-up branch 1b implements doubled voltage output. Since the processing of the second pre-stage clock CLK2' is similar to that of the first pre-stage clock CLK1', the same effect of reducing the reverse current will also be produced on the first step-up branch 1b, and details will not be repeated here. At this time, the first clock CLK1 is invalid, and both the first charging branch 1 a and the second boosting branch 2 b are inactive. The third clock CLK3 is invalid, and the first switch S1 is turned on. the

At point C in Figure 6, the first clock CLK1, the first pre-stage clock CLK1', the second clock CLK2, and the second pre-stage clock CLK2' are invalid, that is, the two boost branches have no voltage doubler output at this time. Only the third clock CLK3 is effective, and does not overlap with the first clock CLK1 , the first previous-stage clock CLK1 ′, the second clock CLK2 , and the second previous-stage clock CLK2 ′. At this time, the first switch S1 is closed, similar to the previous example, the charge sharing between the first capacitor C1 and the second capacitor C2 can be realized, and the energy efficiency can be further improved. the

FIG. 7 is a schematic structural diagram of a liquid crystal display driver chip described in the present invention. As shown in the figure, the liquid crystal display driver chip includes the charge pump described in the utility model (input/output signals irrelevant to the utility model are not shown). The charge pump receives the clock signals CLK1, CLK2, and CLK3 generated by the timing controller, and receives the input of the power supply voltage Vcc, outputs the voltage doubled by the charge pump, and delivers it to the TFT source driver module, TFT gate driver module, The common pole drive is used as the input signal of these modules to generate subsequent drive operations. the

Although the utility model has been disclosed as above with preferred embodiments, the utility model is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present utility model, so the protection scope of the present utility model should be based on the scope defined in the claims. the

Claims (7)

1. A charge pump, characterized in that, comprising: a first capacitor and a second capacitor; The charging circuit includes a first charging branch and a second charging branch; the first charging branch is controlled by the first clock, and when the first clock is valid, the first capacitor is charged; the second charging branch is controlled by The second clock is controlled, and when the second clock is effective, the charging of the second capacitor is realized; the first and second clocks are a pair of non-overlapping clocks; The boost circuit includes a first boost branch and a second boost branch; the first boost branch is controlled by the second clock, and when the second clock is valid, the voltage on the upper plate of the first capacitor is raised and output to the outside; the second step-up branch is controlled by the first clock, and when the first clock is valid, the voltage on the upper plate of the second capacitor is raised and output to the outside; The first switch connecting the lower plate of the first capacitor and the lower plate of the second capacitor is controlled by a third clock; the third clock is valid when both the first and second clocks are invalid, and is consistent with the first clock 1. The second clocks do not overlap each other; when the third clock is valid, the first switch is closed, so that the first capacitor and the second capacitor realize charge sharing. 2. The charge pump as claimed in claim 1, characterized in that: The first charging branch includes: a second switch connected to the power supply voltage, a third switch connected to ground, and when the first clock is valid, the second and third switches are closed; The second charging branch includes: a fourth switch connected to the power supply voltage, and a fifth switch connected to ground. When the second clock is active, the fourth and fifth switches are closed. 3. The charge pump as claimed in claim 1, characterized in that: The first step-up branch includes: a sixth switch connected to the voltage output terminal of the charge pump, and a seventh switch connected to the power supply voltage. When the second clock is active, the sixth and seventh switches are closed; The second step-up branch includes: an eighth switch connected to the voltage output terminal of the charge pump, and a ninth switch connected to the power supply voltage. When the first clock is active, the eighth and ninth switches are closed. the 4. The charge pump as claimed in claim 2, characterized in that: The second switch is a PMOS transistor, its source is connected to the power supply voltage, the gate receives the first clock, and the drain is connected to the upper plate of the first capacitor; the third switch is an NMOS transistor, its The drain is connected to the lower plate of the first capacitor, the gate receives the reverse signal of the first clock, and the source is grounded; The fourth switch is a PMOS transistor, its source is connected to the power supply voltage, the gate receives the second clock, and the drain is connected to the upper plate of the second capacitor; the fifth switch is an NMOS transistor, its The drain is connected to the lower plate of the second capacitor, the gate receives the reverse signal of the second clock, and the source is grounded. 5. The charge pump as claimed in claim 3, characterized in that: The sixth switch is a PMOS transistor, its source is connected to the voltage output terminal of the charge pump, the gate receives the second clock, and the drain is connected to the upper plate of the first capacitor; the seventh switch is a A PMOS transistor, the drain of which is connected to the lower plate of the first capacitor, the gate receives the second clock, and the source is connected to the power supply voltage; The eighth switch is a PMOS transistor, its source is connected to the voltage output terminal of the charge pump, the gate receives the first clock, and the drain is connected to the upper plate of the second capacitor; the ninth switch is a The drain of the PMOS transistor is connected to the lower plate of the second capacitor, the gate receives the first clock, and the source is connected to the power supply voltage. 6. The charge pump as claimed in claim 3, characterized in that: The sixth switch is a PMOS transistor, its source is connected to the voltage output terminal of the charge pump, the gate receives the second clock, and the drain is connected to the upper plate of the first capacitor; the seventh switch is a PMOS transistor, its drain is connected to the lower plate of the first capacitor, the gate receives the second previous stage clock signal, and the source is connected to the power supply voltage. After the second previous stage clock signal is delayed, the second clock signal, and the second preceding clock does not overlap with the first clock; when the second clock is valid, the seventh switch is closed earlier than the sixth switch; The eighth switch is a PMOS tube, its source is connected to the voltage output terminal of the charge pump, the grid receives the first clock, and the drain is connected to the upper plate of the second capacitor; the ninth switch is a PMOS transistor, its drain is connected to the lower plate of the second capacitor, the gate receives the first previous stage clock signal, and the source is connected to the power supply voltage. After the first previous stage clock signal is delayed, the first stage clock signal is obtained. clock signal, and the first previous stage clock and the second clock do not overlap each other; when the first clock is valid, the ninth switch is closed earlier than the eighth switch; The third clock is valid when the first, first previous stage, second, and second previous stage clocks are all invalid, and during the effective period of the third clock, the first clock, the first previous stage clock, and the second clock , the second pre-stage clock are invalid. 7. A liquid crystal display driver chip, characterized in that it comprises any one of the charge pumps described in claims 1-6. the

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