CN103681869A - Thin film transistor substrate, manufacturing method for thin film transistor substrate, and display - Google Patents

Abstract

The present invention relates to a thin film transistor substrate and its manufacturing method, and a display. The thin film transistor substrate is suitable for a display, and includes: a first substrate; a protective layer formed on one side of the first substrate, and the The protection layer completely covers the first substrate; and a buffer layer is formed on the protection layer. The aforesaid protective layer may be composed of light-absorbing or light-reflecting materials, and the light-absorbing or light-reflecting materials include metals.

Description

Thin film transistor substrate, manufacturing method thereof, and display

technical field

The invention relates to a flat panel display technology, in particular to a thin film transistor substrate and a manufacturing method thereof which can effectively avoid damage to the substrate during laser processing.

Background technique

In recent years, the demand for active matrix flat panel displays, such as active matrix organic light emitting device (AMOLED) displays, has increased rapidly. Active array organic light emitting devices usually use thin film transistors as switching elements of pixels and driving circuits, and they can be divided into amorphous silicon (a-Si) and polysilicon thin film transistors according to the material used in the active layer. Compared with amorphous silicon thin film transistors, polycrystalline silicon thin film transistors have the advantages of high carrier mobility, high drive circuit integration and low leakage current, and are often used in high-speed operation products. Therefore, low temperature polysilicon (hereinafter referred to as LTPS) has become a new application of flat panel display technology. LTPS can be formed through a simple IC process, and the driving circuit is integrated on the substrate with pixels, which reduces the manufacturing cost.

In addition, some processes of LTPS thin film transistors usually need to be carried out at high temperature (eg, 600° C.), such as hydrogenation, dehydrogenation, dopant activation or laser annealing. The general low-temperature polysilicon process mostly uses laser annealing technology, using laser as a heat source to convert the amorphous silicon structure into a polysilicon structure. Moreover, according to the current laser heat treatment process, the critical point that the substrate can withstand, such as 350° C., will be exceeded, resulting in damage to the substrate.

In view of the fact that the traditional devices cannot effectively solve the damage of the substrate caused by laser processing, it is necessary to propose a novel technology to solve the above problems in an economical and effective manner.

Contents of the invention

In view of the above, one purpose of the embodiments of the present invention is to provide a thin film transistor substrate, its manufacturing method and a display, so as to solve the problem of substrate damage caused by laser processing.

One of the objectives of the embodiments of the present invention is to provide a thin film transistor substrate and a manufacturing method thereof, in which a protective layer is disposed on one side of the substrate to prevent laser damage to the substrate.

In one embodiment, the present invention provides a thin film transistor substrate suitable for a display, comprising: a first substrate; a protective layer formed on one side of the first substrate, and the protective layer covers the entire surface of the first substrate. The first substrate, wherein the protection layer is a material with light absorption or light reflection properties; and a buffer layer is formed on the protection layer.

Wherein, the protective layer is metal.

Wherein, the protective layer is aluminum, molybdenum, copper, titanium, tungsten or a combination thereof.

之间。Wherein, the thickness of the protective layer is between

between.

Wherein, the first substrate is a flexible substrate.

Wherein, the first substrate is polyethylene terephthalate, ethylene naphthalate, polyimide, polyethersulfone, polycarbonate or a combination thereof.

Among them, it also includes:

an active layer formed on the buffer layer;

a gate insulating layer covering the active layer;

a first metal layer disposed on the gate insulating layer;

a dielectric layer on the gate insulating layer;

a plurality of contact holes disposed on the dielectric layer; and

A second metal layer is disposed on the dielectric layer and is in contact with the active layer through the plurality of contact holes.

Wherein, the active layer includes an N+ doped region and an N− doped region.

Wherein, the active layer includes a P+ doped region.

Wherein, the second metal layer is in contact with the N+ doped region.

Wherein, the second metal layer is in contact with the P+ doped region.

In one embodiment, the present invention provides a method for manufacturing a thin film transistor substrate, which is suitable for a display, comprising: providing a first substrate; forming a protective layer on one side of the first substrate, and the protective layer is integrally The surface covers the first substrate, wherein the protection layer is a material with light absorption or light reflection properties; and a buffer layer is formed on the protection layer.

The present invention also provides a display, comprising a thin film transistor substrate as described above; a second substrate disposed opposite to the thin film transistor substrate; and a display medium disposed on the thin film transistor substrate and the second substrate between.

In the present invention, a protective layer is arranged on one side of the flexible substrate to prevent the laser from penetrating the flexible substrate during laser technology, thereby damaging the glass substrate connected to the flexible substrate through the adhesive layer, or even at the same time Damage the physical properties of flexible substrates and bonding layers, thereby improving product yield and efficiency.

Description of drawings

1A-1F show a manufacturing method of a thin film transistor substrate according to an embodiment of the present invention.

Description of reference numerals: 101-first substrate; 102-protective layer; 103-buffer layer; 104-first active layer; 105-second active layer; 106-gate insulating layer; 107-dielectric layer; 108- Contact hole; 109-passivation layer; 110a-first metal layer; 110b-second metal layer; 104a, 104f-N+ doped region; 104b, 104d-N-doped region; 104c-channel; 105a, 105b- P+ doped region; 105c-channel.

Detailed ways

In order to enable your review committee to have a better understanding of the characteristics, purpose and functions of the present invention, the following will describe the relevant detailed structure and design concept of the device of the present invention, so that the review committee can understand this disclosure The characteristics are described in detail as follows:

之间。前述的缓冲层可由氧化硅、氮化硅或其组合所构成，而第一与第二主动层可由低温多晶硅所构成。另外，于第一基板101的另一侧可接着粘胶层(glue)，以用于接着玻璃载板。FIG. 1A shows a manufacturing method of a thin film transistor according to an embodiment of the present invention, and the manufacturing method is applicable to a display, and the display can be an organic light emitting display. As shown in Figure 1A, a first substrate 101 is provided, and a protective layer 102 is provided on one side of the first substrate 101, and then a buffer layer 103 is covered on the protective layer 102, and A first active layer 104 and a second active layer 105 are disposed on the buffer layer 103 . In addition, the aforementioned first substrate 101 can be a flexible substrate, and the material can be polyethylene terephthalate (PET, Polyethylene Terephthalate), ethylene naphthalate (PEN, Polyethylene Naphthalate), polyimide ( PI, Polyimide), polyethersulfone (PES, Polyether Sulfone), polycarbonate (PC, Polycarbonate) or a combination thereof. The protective layer 102 is made of materials with light absorption or light reflection properties, and the materials with light absorption or light reflection properties include metals, such as aluminum (Al), molybdenum (Mo), copper (Cu), titanium (Ti), tungsten (W), etc. or combinations thereof. In addition, the thickness of the protective layer is between

between. The aforementioned buffer layer can be made of silicon oxide, silicon nitride or a combination thereof, and the first and second active layers can be made of low temperature polysilicon. In addition, an adhesive layer (glue) can be attached to the other side of the first substrate 101 for attaching a glass carrier.

As shown in FIG. 1B, N+ doped regions 104a, 104f, N-doped regions 104b, 104d, a channel 104c and the first active layer 104 are formed by a dopant activation process. The P+ doped regions 105a, 105b and the channel 105c are formed on the second active layer. The aforementioned N+ doped region is adjacent to the N-doped region 104b, another N+ doped region 104d is adjacent to the N-doped region 104f, and the channel 104c is arranged between the N-doped regions 104b, 104d . The channel 105c of the second active layer is disposed between the P+ doped regions 105a, 105b. Then, a laser doping activation (laser activation) treatment with a temperature between 600° C. and 1200° C. is performed. Due to the protection of the protective layer 102 at this time, the laser light can be prevented from penetrating the first substrate 101 and damaging the physical properties of the first substrate 101 , and indirectly protecting the adhesive layer and the glass carrier attached to the first substrate 101 .

As shown in FIG. 1C, a gate insulating layer 106 is formed to cover the aforementioned active layers 104 and 105, and then a first metal layer 110a is formed, so that the first active layer 104, the second The active layer 105 forms a CMOS, PMOS or NMOS transistor with the gate insulating layer 106 and a first metal layer 110a.

As shown in FIG. 1D , performing interlayer dielectric (interlayer dielectric, ILD) deposition on the gate insulating layer 106 and the first metal layer 110a to deposit one or more dielectric layers 107, and Etching or patterning is performed on the dielectric layer 107 to expose partial regions of the first active layer 104 , the second active layer 105 and the first metal layer 110 a. The aforementioned etching process includes plasma etching or reactive ion etching, etc., and the aforementioned patterning process includes a lithography process. The aforementioned dielectric layer 107 can be made of silicon oxide, silicon nitride or a combination thereof.

As shown in FIG. 1E, a plurality of contact holes 108 are formed in the dielectric layer 107 after etching or patterning, and then, a second metal layer 110b is formed on the dielectric layer 107, the second The metal layer 110 b is in contact with the N+ doped regions 104 a , 104 f and the P+ doped regions 105 a , 105 b through the plurality of contact holes 108 . It should be noted that the second metal layer 110 can also be in contact with the first metal layer 110 a through the contact hole 108 .

As shown in FIG. 1F , a passivation layer 109 is formed on the dielectric layer 107 and the second metal layer 110 b. Afterwards, follow-up existing processes (such as forming a planarization layer, a pixel define layer, and pixel electrodes, etc.) are carried out, which will not be repeated here. The aforementioned passivation layer 109 includes a material selected from the group consisting of CoWP, CoP, NiWP, NiB, CoWB, NiReP, and CoReP. And after the aforementioned processes are completed, the glue layer (glue) and the glass carrier plate attached to the substrate 101 can be removed.

之间；一缓冲层103，形成于所述保护层102之上；一第一主动层104与一第二主动层105分别形成于所述缓冲层103之上；一栅极绝缘层106，覆盖于所述第一与第二主动层104、105；一介电层107，形成于所述栅极绝缘层106之上；一第一金属层110a与多个延伸部接触孔108，设置于所述介电层107；一第二金属层110b设置于介电层107之上，所述第二金属层110b经由所述多个接触孔108与所述主动层接触104、105；以及一钝化层109，覆盖于所述第二金属层110b与所述介电层107。于本发明更可应用温度介于600℃到1200℃间激光掺杂活化处理于所述第一主动层104上形成一N+掺杂区与一N-掺杂区以及于所述第二主动层105形成一P+掺杂区，例如，通过一掺杂活化(dopantactivaton)处理，以于所述第一主动层104上形成N+掺杂区104a、104f、N-掺杂区104b、104d与一通道104c以及所述第二主动层上形成P+掺杂区105a、105b与通道105c。前述的N+掺杂区邻接所述N-掺杂区104b，另一N+掺杂区104d邻接所述N-掺杂区104f，而所述通道104c设于N-掺杂区104b、104d之间。所述第二主动层的通道105c设置于P+掺杂区105a、105b之间。所述第二金属层110b经由所述多个接触孔108与所述N+掺杂区104a、104f及P+掺杂区105a、105b接触。值得注意的是，所述第二金属层110亦可经由接触孔108与所述第一金属层110a接触。另外，前述的缓冲层103与介电层107可由氧化硅、氮化硅或其组合所构成。FIG. 1F shows a thin film transistor substrate of the present invention, which is suitable for a display, and the display can be an organic light emitting display. The thin film transistor substrate includes: a first substrate 101, and the first substrate can be a flexible substrate; a protective layer 102 is formed on one side of the first substrate 101, and the protective layer 102 is formed on the entire surface Covering the first substrate, and the protective layer 102 is made of a material with light absorption or light reflection properties, and the material with light absorption or light reflection properties includes metals, for example, aluminum (Al), molybdenum (Mo ), copper (Cu), titanium (Ti), tungsten (W) or a combination thereof, and the thickness of the protective layer 102 is between

Between; a buffer layer 103, formed on the protective layer 102; a first active layer 104 and a second active layer 105 respectively formed on the buffer layer 103; a gate insulating layer 106, covering On the first and second active layers 104, 105; a dielectric layer 107 is formed on the gate insulating layer 106; a first metal layer 110a and a plurality of extension contact holes 108 are arranged on the The dielectric layer 107; a second metal layer 110b is disposed on the dielectric layer 107, the second metal layer 110b is in contact with the active layer 104, 105 through the plurality of contact holes 108; and a passivation layer 109 covering the second metal layer 110 b and the dielectric layer 107 . In the present invention, a laser doping activation treatment with a temperature between 600° C. and 1200° C. can be applied to form an N+ doped region and an N− doped region on the first active layer 104 and on the second active layer. 105 to form a P+ doped region, for example, through a dopant activation (dopantactivaton) treatment, so as to form N+ doped regions 104a, 104f, N-doped regions 104b, 104d and a channel on the first active layer 104 104c and the second active layer are formed with P+ doped regions 105a, 105b and a channel 105c. The aforementioned N+ doped region is adjacent to the N-doped region 104b, another N+ doped region 104d is adjacent to the N-doped region 104f, and the channel 104c is arranged between the N-doped regions 104b, 104d . The channel 105c of the second active layer is disposed between the P+ doped regions 105a, 105b. The second metal layer 110b is in contact with the N+ doped regions 104a, 104f and the P+ doped regions 105a, 105b through the plurality of contact holes 108 . It should be noted that the second metal layer 110 can also be in contact with the first metal layer 110 a through the contact hole 108 . In addition, the aforementioned buffer layer 103 and dielectric layer 107 may be formed of silicon oxide, silicon nitride or a combination thereof.

Furthermore, the present invention provides a display, comprising: a thin film transistor substrate and a second substrate disposed opposite to each other; and a display medium disposed between the thin film transistor substrate and the second substrate, wherein the display medium can be an organic light emitting layer.

In the present invention, a protective layer is arranged on one side of the flexible substrate to prevent the laser from penetrating the flexible substrate during laser technology, thereby damaging the glass substrate connected to the flexible substrate through the adhesive layer, or even at the same time Damage the physical properties of flexible substrates and bonding layers, thereby improving product yield and efficiency.

The above-mentioned ones are only exemplary embodiments of the present invention, and should not limit the implementation scope of the present invention. That is to say, all the equivalent changes and modifications made according to the scope of the patent application of the present invention should still fall within the scope covered by the patent of the present invention. I would like to ask your review committee to take note and pray for your approval.

Claims (21)

1. a thin film transistor base plate, is characterized in that, comprising:

One first substrate;

One protective layer, is formed at a side of described first substrate, and whole of described protective layer covers described first substrate, and wherein said protective layer is to have the material that absorbs light or reverberation characteristic; And

One resilient coating, is formed on described protective layer.

2. thin film transistor base plate according to claim 1, is characterized in that, described protective layer is metal.

3. according to the thin film transistor base plate described in claim 1, it is characterized in that, described protective layer is aluminium, molybdenum, copper, titanium, tungsten or its combination.

4. thin film transistor base plate according to claim 1, is characterized in that, the thickness of described protective layer between

between.

5. thin film transistor base plate according to claim 1, is characterized in that, described first substrate is flexible base plate.

6. thin film transistor base plate according to claim 1, is characterized in that, described first substrate is polyethylene terephthalate, naphthalenedicarboxylic acid second diester, polyimides, polyether sulfone, Merlon or its combination.

7. thin film transistor base plate according to claim 1, is characterized in that, more comprises:

One active layers, is formed on described resilient coating;

One gate insulator, is covered in described active layers;

One the first metal layer, is arranged on described gate insulator;

One dielectric layer, on described gate insulator;

A plurality of contact holes, are arranged at described dielectric layer; And

One second metal level, is arranged on described dielectric layer, via described a plurality of contact holes, contacts with described active layers.

8. thin film transistor base plate according to claim 7, is characterized in that, described active layers comprises a N+ doped region and a N-doped region.

9. thin film transistor base plate according to claim 7, is characterized in that, described active layers comprises a P+ doped region.

10. thin film transistor base plate according to claim 8, is characterized in that, described the second metal level contacts with described N+ doped region.

11. thin film transistor base plates according to claim 9, is characterized in that, described the second metal level contacts with described P+ doped region.

The manufacture method of 12. 1 kinds of thin film transistor base plates, is characterized in that, comprising:

One first substrate is provided;

A side in described first substrate forms a protective layer, and whole of described protective layer covers described first substrate, and wherein said protective layer is to have the material that absorbs light or reverberation characteristic; And

In upper formation one resilient coating of described protective layer.

The manufacture method of 13. thin film transistor base plates according to claim 12, is characterized in that, described protective layer is metal.

The manufacture method of 14. thin film transistor base plates according to claim 12, is characterized in that, described protective layer is aluminium, molybdenum, copper, titanium, tungsten or its combination.

The manufacture method of 15. thin film transistor base plates according to claim 12, is characterized in that, the thickness of described protective layer between

between.

The manufacture method of 16. thin film transistor base plates according to claim 12, is characterized in that, more comprises:

Form an active layers on described resilient coating;

Form a gate insulator, to cover described active layers;

One the first metal layer is set on described gate insulator;

Form a dielectric layer on described gate insulator;

A plurality of contact holes are set in described dielectric layer; And

One second metal level is set on described dielectric layer, via described a plurality of contact holes, contacts with described active layers.

The manufacture method of 17. thin film transistor base plates according to claim 16, is characterized in that, forms before described gate insulator, carries out the laser doping activation processing of a temperature between 600 ℃ to 1200 ℃ and in described active layers, forms a plurality of doped regions.

The manufacture method of 18. thin film transistor base plates according to claim 17, is characterized in that, described a plurality of doped regions are N+ doped region and N-doped region.

The manufacture method of 19. thin film transistor base plates according to claim 17, is characterized in that, described a plurality of doped regions are P+ doped region.

20. 1 kinds of displays, is characterized in that, comprising:

One thin film transistor base plate according to claim 1;

One second substrate, is oppositely arranged with described thin film transistor base plate; And

One display medium, is formed between described thin film transistor base plate and described second substrate.

21. displays according to claim 20, is characterized in that, described display medium is an organic luminous layer.

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