CN103545416B - Die bonding method of light emitting diode - Google Patents
Die bonding method of light emitting diode Download PDFInfo
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- CN103545416B CN103545416B CN201210258117.0A CN201210258117A CN103545416B CN 103545416 B CN103545416 B CN 103545416B CN 201210258117 A CN201210258117 A CN 201210258117A CN 103545416 B CN103545416 B CN 103545416B
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- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000000919 ceramic Substances 0.000 claims abstract description 32
- 230000005496 eutectics Effects 0.000 claims abstract description 32
- 239000000463 material Substances 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000005520 cutting process Methods 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 239000004952 Polyamide Substances 0.000 claims 1
- 150000002466 imines Chemical class 0.000 claims 1
- 229920002647 polyamide Polymers 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 description 11
- 239000002184 metal Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000004642 Polyimide Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 230000003139 buffering effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000010344 co-firing Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/85—Packages
- H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/01—Manufacture or treatment
- H10H20/036—Manufacture or treatment of packages
- H10H20/0364—Manufacture or treatment of packages of interconnections
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- Led Device Packages (AREA)
Abstract
本发明揭露一种发光二极管的固晶方法。发光二极管的基板包含第一陶瓷板、缓冲材料层、导电层以及第二陶瓷板。缓冲材料层位于第一陶瓷板上。导电层位于缓冲材料层上，且导电层具有一发光二极管的固晶区域。第二陶瓷板位于导电层上，且其具有一开口区域借以裸露出导电层的固晶区域。此发光二极管的基板可应用于使用共晶层的发光二极管的固晶方法中。
The present invention discloses a method for bonding a light emitting diode. The substrate of the light emitting diode comprises a first ceramic plate, a buffer material layer, a conductive layer and a second ceramic plate. The buffer material layer is located on the first ceramic plate. The conductive layer is located on the buffer material layer, and the conductive layer has a bonding region for the light emitting diode. The second ceramic plate is located on the conductive layer, and it has an opening region to expose the bonding region of the conductive layer. The substrate of the light emitting diode can be applied to a bonding method for a light emitting diode using a eutectic layer.
Description
技术领域technical field
本发明是有关于一种发光二极管的固晶方法，且特别是有关于一种使用共晶层的发光二极管的固晶方法及其使用的基板。The invention relates to a crystal-bonding method of a light-emitting diode, and in particular to a crystal-bonding method of a light-emitting diode using a eutectic layer and a substrate used therefor.
背景技术Background technique
目前将发光二极管芯片固晶于基板上的方法很多，较常见的方式是使用点胶方式将发光二极管芯片的底面上胶后，再粘着于基板上的固晶区域。此种方式即使应用了自动化的生产设备，发光二极管芯片粘着于基板上后，还需要等待胶固化后才能进行下一道步骤，因此固晶步骤的产能提升不易。其他一次固晶大量发光二极管芯片的方法，则有的尚未成熟，有的合格率过低，因此都尚未成为固晶大量发光二极管芯片的主流方式。有鉴于此，发光二极管生产技术急需如何固晶大量发光二极管芯片的优良方法，以提升发光二极管的整体产能。At present, there are many methods for bonding the LED chip on the substrate. The more common method is to glue the bottom surface of the LED chip by dispensing, and then stick it to the die-bonding area on the substrate. Even if automated production equipment is used in this method, after the LED chip is adhered to the substrate, it is necessary to wait for the glue to cure before proceeding to the next step. Therefore, it is not easy to increase the production capacity of the die-bonding step. Other methods for bonding a large number of LED chips at one time are not yet mature, and some have a low pass rate, so they have not yet become the mainstream method for bonding a large number of LED chips. In view of this, the LED production technology urgently needs an excellent method of how to bond a large number of LED chips, so as to increase the overall production capacity of LEDs.
发明内容Contents of the invention
因此，本发明的一目的是在提供一种改良发光二极管的基板及使用该基板的固晶方法。Therefore, an object of the present invention is to provide an improved LED substrate and a die bonding method using the substrate.
根据上述本发明的目的，提供一种发光二极管的基板，其包含第一陶瓷板、缓冲材料层、导电层以及第二陶瓷板。缓冲材料层位于第一陶瓷板上。导电层位于缓冲材料层上，且导电层具有一发光二极管的固晶区域。第二陶瓷板位于导电层上，且其具有一开口区域借以裸露出导电层的固晶区域。According to the above object of the present invention, a light emitting diode substrate is provided, which includes a first ceramic board, a buffer material layer, a conductive layer and a second ceramic board. A layer of cushioning material is on the first ceramic plate. The conductive layer is located on the buffer material layer, and the conductive layer has a crystal bonding area of a light emitting diode. The second ceramic plate is located on the conductive layer, and has an opening area to expose the crystal bonding area of the conductive layer.
依据本发明另一实施例，固晶区域实质上与第二陶瓷板未与导电层接触的表面齐平。According to another embodiment of the present invention, the die-bonding region is substantially flush with the surface of the second ceramic plate not in contact with the conductive layer.
依据本发明另一实施例，导电层的材质为金属材质。According to another embodiment of the present invention, the conductive layer is made of metal.
依据本发明另一实施例，缓冲材料层为一聚酰亚胺层。According to another embodiment of the present invention, the buffer material layer is a polyimide layer.
根据上述本发明的目的，提供一种发光二极管的固晶方法，其包含以下步骤。提供一基板，其由下而上依序包含一第一陶瓷板、一缓冲材料层、一导电层以及一第二陶瓷板，第二陶瓷板具有多个开口区域借以裸露出导电层的多个固晶区域。放置多个发光二极管芯片分别于导电层上的该些固晶区域，其中每一发光二极管芯片的底面具有一共晶层以与每一固晶区域接触。切割任两相邻发光二极管芯片之间的第二陶瓷板与导电层，以于缓冲材料层上留下多个切割道。使用一加热块同时下压于该些发光二极管芯片上，使该些发光二极管芯片的各共晶层分别固化于导电层的该些固晶区域上。According to the above object of the present invention, there is provided a crystal bonding method for light emitting diodes, which includes the following steps. A substrate is provided, which sequentially includes a first ceramic plate, a buffer material layer, a conductive layer, and a second ceramic plate from bottom to top, and the second ceramic plate has a plurality of opening regions to expose a plurality of conductive layers. Die bonding area. A plurality of light-emitting diode chips are respectively placed on the crystal-bonding regions on the conductive layer, wherein the bottom surface of each light-emitting diode chip has a eutectic layer to be in contact with each crystal-bonding region. The second ceramic board and the conductive layer between any two adjacent LED chips are cut to leave a plurality of cutting lines on the buffer material layer. A heating block is used to press down on the LED chips at the same time, so that the eutectic layers of the LED chips are respectively solidified on the solid crystal regions of the conductive layer.
依据本发明另一实施例，加热块的温度大于共晶层的共晶温度。According to another embodiment of the present invention, the temperature of the heating block is higher than the eutectic temperature of the eutectic layer.
依据本发明另一实施例，共晶层为一双金属混合层。According to another embodiment of the present invention, the eutectic layer is a bimetal mixed layer.
依据本发明另一实施例，共晶层为一金、锡混合层。According to another embodiment of the present invention, the eutectic layer is a mixed layer of gold and tin.
依据本发明另一实施例，导电层的材质为金属材质。According to another embodiment of the present invention, the conductive layer is made of metal.
依据本发明另一实施例，缓冲材料层为一聚酰亚胺层。According to another embodiment of the present invention, the buffer material layer is a polyimide layer.
由上述可知，应用本发明的具有缓冲能力基板，在使用加热块同时施压于多颗发光二极管芯片时，基板中的缓冲材料层提供受力过大时所需应力或位置的缓冲，而避免下压应力过大所造成的芯片破损或其他导致共晶制程低合格率的情形，使得大量发光二极管芯片的固晶制程的合格率能提升许多。As can be seen from the above, when using the substrate with cushioning capacity of the present invention, when using a heating block to apply pressure to multiple LED chips at the same time, the buffer material layer in the substrate provides buffering for the required stress or position when the force is too large, so as to avoid Chip breakage caused by excessive down-pressing stress or other conditions that lead to low yield of eutectic process can greatly improve the yield of die-bonding process for a large number of LED chips.
附图说明Description of drawings
为让本发明的上述和其他目的、特征、优点与实施例能更明显易懂，所附图式的说明如下：In order to make the above and other objects, features, advantages and embodiments of the present invention more obvious and understandable, the accompanying drawings are described as follows:
图1是绘示依照本发明一实施例的一种发光二极管固晶于基板上的剖面图；FIG. 1 is a cross-sectional view showing a light-emitting diode die-bonded on a substrate according to an embodiment of the present invention;
图2是绘示依照本发明另一实施例的一种发光二极管固晶于基板上的剖面图；FIG. 2 is a cross-sectional view showing a light-emitting diode die-bonded on a substrate according to another embodiment of the present invention;
图3是绘示依照本发明又一实施例的一种发光二极管固晶于基板上的剖面图；FIG. 3 is a cross-sectional view showing a light-emitting diode die-bonded on a substrate according to yet another embodiment of the present invention;
图4A～4D是绘示依照本发明一实施例的一种发光二极管固晶方法的各步骤剖面示意图。4A-4D are cross-sectional schematic diagrams illustrating various steps of a method for bonding LEDs according to an embodiment of the present invention.
【主要元件符号说明】[Description of main component symbols]
100 基板100 substrates
102 第一陶瓷板102 first ceramic plate
104 缓冲材料层104 cushioning material layer
106 导电层106 conductive layer
106a 固晶区域106a Die bonding area
106b 区域106b area
106c 区域106c area
108 第二陶瓷板108 second ceramic plate
108a 开口区域108a Opening area
108b 表面108b surface
110 发光二极管芯片110 LED chips
110a 共晶层110a eutectic layer
110’ 发光二极管芯片110’ LED chip
110” 发光二极管芯片110” LED chip
200 基板200 substrates
202 第二陶瓷板202 second ceramic plate
204 缓冲材料层204 buffer material layer
206 导电层206 conductive layer
206a 固晶区域206a Die bonding area
208 第二陶瓷板208 second ceramic plate
208a 开口区域208a Opening area
210 发光二极管芯片210 LED chips
210a 共晶层210a eutectic layer
212 切割道212 cutting lane
220 加热块220 heating block
具体实施方式detailed description
请参照图1，其绘示依照本发明一实施例的一种发光二极管芯片固晶于基板上的剖面图。基板100包含第一陶瓷板102、缓冲材料层104、导电层106以及第二陶瓷板108，并利用迭层共烧的方式将上述各层、板固定在一起形成基板。缓冲材料层104位于第一陶瓷板102上，用以提供发光二极管芯片110固晶时所需的应力或位置的缓冲。在本实施例中，缓冲材料层104可以是聚酰亚胺层或其他材质的缓冲材料。导电层106位于缓冲材料层104上，且具有一发光二极管芯片110的固晶区域106a。在本实施例中，导电层106较佳为一金属层，可供发光二极管芯片110底面的共晶层110a得以粘着于金属的导电层106上。若发光二极管芯片并非以共晶方式粘着于导电层106上，导电层106就可以是非金属的导电层。在本实施例中，固晶区域106a为一凸出导电层106的区域，且实质上与第二陶瓷板108未与导电层106接触的表面108b齐平。位于导电层106上的第二陶瓷板108需具有一开口区域108a，借以裸露出导电层106的固晶区域106a。在其他实施例中，固晶区域也可以平坦区域，而不与第二陶瓷板108的表面108b齐平。此外，固晶区域106a被区分为两彼此绝缘的区域(106b；106c)，供发光二极管芯片110的两电极分别电性连接。在本实施例中，发光二极管芯片110的其中一电极直接连接于固晶区域106a的区域106b，另一电极则以导线连接于固晶区域106a的另一区域106c。Please refer to FIG. 1 , which shows a cross-sectional view of a light-emitting diode chip die-bonded on a substrate according to an embodiment of the present invention. The substrate 100 includes a first ceramic plate 102 , a buffer material layer 104 , a conductive layer 106 and a second ceramic plate 108 , and the above-mentioned layers and plates are fixed together by lamination and co-firing to form a substrate. The buffer material layer 104 is located on the first ceramic board 102 and is used for providing stress or position buffering required for the LED chip 110 during die bonding. In this embodiment, the cushioning material layer 104 may be a polyimide layer or other cushioning materials. The conductive layer 106 is located on the buffer material layer 104 and has a die-bonding region 106 a of the LED chip 110 . In this embodiment, the conductive layer 106 is preferably a metal layer, so that the eutectic layer 110 a on the bottom surface of the LED chip 110 can be adhered to the metal conductive layer 106 . If the LED chip is not adhered on the conductive layer 106 in a eutectic manner, the conductive layer 106 can be a non-metallic conductive layer. In this embodiment, the die-bonding region 106 a is a region that protrudes from the conductive layer 106 and is substantially flush with the surface 108 b of the second ceramic board 108 that is not in contact with the conductive layer 106 . The second ceramic board 108 on the conductive layer 106 needs to have an opening area 108 a, so as to expose the die-bonding area 106 a of the conductive layer 106 . In other embodiments, the die-bonding area may also be a flat area, which is not flush with the surface 108 b of the second ceramic plate 108 . In addition, the die-bonding region 106a is divided into two mutually insulated regions ( 106b ; 106c ) for electrically connecting the two electrodes of the LED chip 110 respectively. In this embodiment, one electrode of the LED chip 110 is directly connected to the region 106b of the die-bonding region 106a, and the other electrode is connected to the other region 106c of the die-bonding region 106a by a wire.
请参照图2，其绘示依照本发明另一实施例的一种发光二极管芯片固晶于基板上的剖面图。图2的实施例不同于图1的实施例在于发光二极管芯片的种类。在图2的实施例中，发光二极管芯片110’是以覆晶的方式粘着于固晶区域106a上，换言之，发光二极管芯片110’的两电极直接连接于固晶区域106a的两彼此绝缘的区域(106b；106c)。Please refer to FIG. 2 , which shows a cross-sectional view of a LED chip bonded on a substrate according to another embodiment of the present invention. The embodiment of FIG. 2 is different from the embodiment of FIG. 1 in the type of LED chips. In the embodiment of FIG. 2, the LED chip 110' is adhered to the die-bonding region 106a in a flip-chip manner. In other words, the two electrodes of the LED chip 110' are directly connected to two mutually insulated regions of the die-bonding region 106a. (106b; 106c).
请参照图3，其绘示依照本发明又一实施例的一种发光二极管芯片固晶于基板上的剖面图。图3的实施例不同于图1、图2的实施例亦在于发光二极管芯片的种类。在图3的实施例中，发光二极管芯片110”的两电极是分别以导线连接至固晶区域106a的两彼此绝缘的区域(106b；106c)。Please refer to FIG. 3 , which shows a cross-sectional view of a LED chip bonded on a substrate according to another embodiment of the present invention. The embodiment in FIG. 3 is different from the embodiments in FIGS. 1 and 2 also in the type of LED chip. In the embodiment of FIG. 3 , the two electrodes of the LED chip 110 ″ are respectively connected to two mutually insulated regions ( 106 b ; 106 c ) of the die-bonding region 106 a by wires.
请参照图4A～4D，其绘示依照本发明一实施例的一种发光二极管固晶方法的各步骤剖面示意图。Please refer to FIGS. 4A-4D , which are schematic cross-sectional diagrams illustrating various steps of a LED die bonding method according to an embodiment of the present invention.
在图4A的步骤中，提供一基板200，其由下而上依序包含第一陶瓷板202、缓冲材料层204、导电层206以及第二陶瓷板208，且第二陶瓷板208具有多个开口区域208a借以裸露出导电层206的多个固晶区域206a。基板200在发光二极管芯片210固晶前尚未分割，借以供多颗发光二极管芯片210一起固晶于基板200上。在本实施例中，发光二极管芯片210底面的具有共晶层210a得以粘着于导电层206上。共晶层210a为一多金属混合层(通常为双金属混合层)，例如可为一金、锡混合层。当共晶层210a被加热高于其共晶温度时，共晶层210a会熔化并迅速固化，以达到将发光二极管芯片210迅速粘着于导电层206上的目的。在本实施例中，导电层206较佳为一金属层，可供发光二极管芯片210底部的共晶层210a得以粘着于金属的导电层206上。In the step of FIG. 4A, a substrate 200 is provided, which sequentially includes a first ceramic plate 202, a buffer material layer 204, a conductive layer 206, and a second ceramic plate 208 from bottom to top, and the second ceramic plate 208 has a plurality of The opening area 208 a exposes the plurality of die-bonding areas 206 a of the conductive layer 206 . The substrate 200 has not been divided before the LED chips 210 are die-bonded, so that a plurality of LED chips 210 can be die-bonded on the substrate 200 together. In this embodiment, the eutectic layer 210 a on the bottom surface of the LED chip 210 is adhered to the conductive layer 206 . The eutectic layer 210a is a multi-metal mixed layer (usually a double-metal mixed layer), such as a gold-tin mixed layer. When the eutectic layer 210a is heated above its eutectic temperature, the eutectic layer 210a will melt and solidify quickly, so as to achieve the purpose of quickly adhering the LED chip 210 to the conductive layer 206 . In this embodiment, the conductive layer 206 is preferably a metal layer, so that the eutectic layer 210 a at the bottom of the LED chip 210 can be adhered to the metal conductive layer 206 .
在图4B的步骤中，将多个发光二极管芯片210放置于对应的固晶区域206a上。每一发光二极管芯片210的共晶层210a接触固晶区域206a。In the step of FIG. 4B , a plurality of LED chips 210 are placed on corresponding die-bonding regions 206 a. The eutectic layer 210a of each LED chip 210 is in contact with the die-bonding region 206a.
在图4C的步骤中，切割任两相邻发光二极管芯片210之间的第二陶瓷板208与导电层206，以于缓冲材料层204上留下多个切割道212。换言之，基板的缓冲材料层204与第一陶瓷板202是保持连接而未被切割。In the step of FIG. 4C , the second ceramic board 208 and the conductive layer 206 between any two adjacent LED chips 210 are cut to leave a plurality of cutting lines 212 on the buffer material layer 204 . In other words, the buffer material layer 204 of the substrate and the first ceramic board 202 are kept connected without being cut.
在图4D的步骤中，使用一加热块220同时下压于发光二极管芯片210上，使该些发光二极管芯片210的共晶层210a熔化并固化于导电层206的对应的固晶区域206a上。在此步骤中，加热块220的温度应大于共晶层210a的共晶温度，才能使共晶层210a达到熔化的目的。在加热块220同时下压于发光二极管芯片210上时，因加热块220的下表面公差、发光二极管芯片210的厚度不一等因素，使得加热块220下压时可能造成某些发光二极管芯片210下压应力不均或加热块无接触等情形。此时，缓冲材料层204就能提供发光二极管芯片210受力过大时所需应力或位置的缓冲，而避免下压应力过大所造成的芯片破损或其他导致共晶制程低合格率的情形。在本实施例中，缓冲材料层204可以是聚酰亚胺层或其他材质的缓冲材料。In the step of FIG. 4D , a heating block 220 is used to press down on the LED chips 210 at the same time, so that the eutectic layers 210 a of the LED chips 210 are melted and solidified on the corresponding die-bonding regions 206 a of the conductive layer 206 . In this step, the temperature of the heating block 220 should be higher than the eutectic temperature of the eutectic layer 210a, so as to melt the eutectic layer 210a. When the heating block 220 is pressed down on the LED chip 210 at the same time, due to factors such as the tolerance of the lower surface of the heating block 220 and the thickness of the LED chip 210, some LED chips 210 may be damaged when the heating block 220 is pressed down. Uneven compressive stress or no contact with the heating block. At this time, the buffer material layer 204 can provide buffering of the required stress or position when the light-emitting diode chip 210 is subjected to excessive force, so as to avoid chip damage caused by excessive downward stress or other situations that lead to low eutectic process yield. . In this embodiment, the cushioning material layer 204 may be a polyimide layer or other cushioning materials.
本案因着眼于发光二极管芯片的固晶制程改良，固晶后的后续制程步骤(例如基板切割、打线或封装等步骤)是使用已知的制程，在此便不再赘述。This case focuses on the improvement of the die-bonding process of light-emitting diode chips, and the subsequent process steps after die-bonding (such as substrate cutting, wire bonding, or packaging) use known processes, and will not be repeated here.
由上述本发明实施方式可知，应用本发明的具有缓冲能力的基板，在使用加热块同时施压于多颗发光二极管芯片时，基板中的缓冲材料层提供受力过大时所需应力或位置的缓冲，而避免下压应力过大所造成的芯片破损或其他导致共晶制程低合格率的情形，使得大量发光二极管芯片的固晶制程的合格率能提升许多。From the above-mentioned embodiments of the present invention, it can be seen that when the substrate with cushioning capacity of the present invention is applied, when a heating block is used to apply pressure to multiple light-emitting diode chips at the same time, the buffer material layer in the substrate provides the required stress or position when the force is too large. buffer, and avoid chip damage caused by excessive down-press stress or other situations that lead to low eutectic process yield, so that the yield of die-bonding process of a large number of light-emitting diode chips can be greatly improved.
虽然本发明已以实施方式揭露如上，然其并非用以限定本发明，任何熟悉此技艺者，在不脱离本发明的精神和范围内，当可作各种的更动与润饰，因此本发明的保护范围当视所附的权利要求书所界定的范围为准。Although the present invention has been disclosed above in terms of implementation, it is not intended to limit the present invention. Any skilled person can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be based on the scope defined by the appended claims.
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| TW101124791A TW201403892A (en) | 2012-07-10 | 2012-07-10 | Substrate of light-emitting diode and method of solid crystal using the same |
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| CN101097978A (en) * | 2007-06-26 | 2008-01-02 | 上海大学 | Copper-interconnected flip-chip light-emitting diode and manufacturing method thereof |
| US20090017566A1 (en) * | 2007-07-09 | 2009-01-15 | Philips Lumileds Lighting Company Llc | Substrate Removal During LED Formation |
| CN101414652A (en) * | 2007-10-17 | 2009-04-22 | 叶秀慧 | Packaging structure of light emitting diode and manufacturing method thereof |
| US20110204408A1 (en) * | 2007-08-22 | 2011-08-25 | Photonstar Led Limited | High thermal performance packaging for optoelectronics devices |
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| CN101097978A (en) * | 2007-06-26 | 2008-01-02 | 上海大学 | Copper-interconnected flip-chip light-emitting diode and manufacturing method thereof |
| US20090017566A1 (en) * | 2007-07-09 | 2009-01-15 | Philips Lumileds Lighting Company Llc | Substrate Removal During LED Formation |
| US20110204408A1 (en) * | 2007-08-22 | 2011-08-25 | Photonstar Led Limited | High thermal performance packaging for optoelectronics devices |
| CN101414652A (en) * | 2007-10-17 | 2009-04-22 | 叶秀慧 | Packaging structure of light emitting diode and manufacturing method thereof |
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