TWI377629B - Package method for flip chip - Google Patents

Description

1377629

TW439IPA IX. Description of the Invention: [Technical Field of the Invention] In particular, the present invention relates to a flip chip packaging method, and a flip chip sealing method for improving substrate utilization. [Prior Art]

In the ever-changing generation of technology, the use of electronic products has become a trend of modern people's life === f electronic products are moving toward a thin and light design. Semiconductor packaging technology has developed many high-density semiconductor package forms, such as In the overlying packaging process, a primer is required to be formed between the wafer and the substrate. However, although the wafer is very thin or has a large area, the report is prone to overflow problems. The benefit of the glue can contaminate the solder bumps of adjacent wafers, resulting in the soldering of adjacent wafers, which are not easily fixed to the contaminated pads during subsequent wire bonding operations. Moreover, recently, customers have demanded a shrinking wafer size, which has shortened the distance between the wafer and the pads of adjacent wafers, thus causing the overflow primer to more easily contaminate the pads adjacent to the wafer. In view of the above, the present invention provides a flip chip packaging method for forming a trench between a pad where a primer is formed and a pad adjacent to a wafer, when a glue overflow occurs. The overflow glue fills the space in the trench first without flowing to the pad of the adjacent wafer, thus reducing the machine that contaminates the pad of the adjacent wafer 5 1377629

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The TW4391PA will, and increase the success rate of adjacent wafers in wire-bonding operations to increase product yield and reduce costs. Moreover, due to the formation of the grooves, the distance between the wafers can be made close without the problem that the pads are contaminated by the glue of the primer, so that the same substrate area can accommodate more wafers, so that the substrate utilization rate is improved. According to one aspect of the present invention, a flip chip packaging method is provided that includes providing a substrate having a dicing street, forming an insulating layer on the substrate, the insulating layer having a trench, the trench being on the dicing street, and a wafer • disposed on the substrate, the wafer is disposed on one side of the trench and adjacent to the trench, the wafer is electrically connected to the substrate by flip chip bonding; and is formed from one side of the wafer adjacent to the dicing street A primer is between the wafer and the substrate. In order to make the above description of the present invention more comprehensible, a preferred embodiment will be described in detail below with reference to the accompanying drawings, and the following description is given as follows: [Embodiment] The present invention provides a flip chip packaging method, including a substrate having a dicing street; an insulating layer formed on the substrate, the insulating layer having a groove, the groove being located on the scribe line; and a wafer disposed on the substrate, the wafer being disposed at one side of the groove And adjacent to the trench, the wafer is electrically connected to the substrate by flip-chip bonding; and a primer is formed between the wafer and the substrate from one side of the wafer adjacent to the dicing street. When the glue overflow occurs, the overflow will fill the space inside the trench without flowing to the pads of the adjacent wafer, thus reducing the chance of contaminating the pads of adjacent wafers. Following 6 1377629 1. »

TW4391PA is a detailed description of a preferred embodiment. However, this embodiment is only one of several embodiments of the present invention. The text and illustrations of the present invention are not intended to protect the scope of the present invention. Limited. Referring to FIG. 1, a flow chart of a flip chip packaging method in accordance with a preferred embodiment of the present invention is shown. The flip chip packaging method includes the following steps. First, please refer to FIG. 2 and FIG. 2 simultaneously. FIG. 2 is a plan view showing the substrate of the embodiment, and FIG. 2 is a front view of the substrate in the second drawing. In step 102, a substrate 202 is provided, the substrate 202 having a dicing street 204. • Referring to FIG. 3 and FIG. 3 simultaneously, FIG. 3 is a plan view showing the substrate on which the insulating layer and the pad are formed in the embodiment, and FIG. 3B is a view showing the substrate along the ia_ia in FIG. 3A. Cutaway view. In step 1 〇 4, an insulating layer 206 is formed on the substrate 202. The insulating layer 206 has a trench 208' trench 208 on the scribe line 204. The insulating layer 2〇6 includes a green lacquer, an isolation layer, an ABF dielectric layer (Ajinomoto Build-up film) or other dielectric material. The width of the trench 208 can be less than or equal to the width of the dicing street 204. The length of the trench 208 can be less than or equal to the length of the φ channel 204. In this embodiment, the width and length of the trench 208 are smaller than the scribe line 204, respectively. The width and length are exemplified. In addition, in the present invention, the flip chip packaging method further includes forming a plurality of pads 214 on the substrate 202 >, the trenches 208 are formed, for example, by an exposure and development technique, and the trenches 2 8 may be formed in the insulating layer 206. The process corresponding to the opening 213 of the pad 214 is completed in the process. Therefore, the formation of the trench is relatively simple and does not increase the process cost. In addition, the recessed space formed by the trench 208 absorbs the substrate 2〇2 at 7 1377629

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The amount of thermal expansion caused by the heating action in the subsequent process of the TW4391PA reduces the warpage of the substrate 202 as a whole, thereby improving the process yield of the flip chip package. Then, please refer to FIG. 4A and FIG. 4B simultaneously. FIG. 4A is a plan view of the substrate on which the wafer is disposed in the embodiment, and FIG. 4B is a cross-sectional view of the substrate taken along line 1B-1B in FIG. 4A. In step 106, a wafer 210 is disposed on the substrate 202. The wafer 210 is disposed on one side of the trench 208 and adjacent to the trench 208. The wafer 210 is electrically connected to the wafer. Substrate 202. In addition, the wafer 210 further has a plurality of solder balls 211'. The wafer 210 is electrically connected to the substrate 202 by the solder balls 211. Further, in this step, another wafer 212 may be formed on the substrate 202. The wafer 210 and the wafer 212 are respectively located on both sides of the dicing street 204. The wafer 212 may be disposed directly on the substrate 202 or stacked on the flip chip. This embodiment is described by way of example in the form of a flip chip 215. The solder pad 214 on the substrate 202 is electrically connected to the wafer 212. The electrical connection is performed by a wire bonding technique. In order to make the length of the gold wire moderate, the pad 214 is formed on the dicing street 204 and the wafer. Between 212. Then, referring to Fig. 5, a plan view of the substrate in the case of forming the primer in the embodiment is shown. In step 108, a primer 216 is formed between the wafer 210 and the substrate 202 from one side 219 of the wafer 210 adjacent the scribe line 204. When the primer 216 begins to be placed adjacent to one side 219 of the wafer 210, By the siphon principle, the primer 216 is slowly drawn between the wafer 210 and the substrate 202. Among them, the way to form the primer 216 can be used 8 1377629 • «

TW4391PA Jetting method or Dispensing method (Dispensing 〇rn〇f (4). In the process of forming the primer without forming the groove, if there is overflow glue, the glue may be contaminated. Referring to Fig. 6A, it is a schematic diagram showing the distribution of the overflow gel when no groove is formed. When the insulating layer 206 has no groove, one of the primers 221 can be accommodated because there is no groove, so it can only flow to Adjacent to the wafer, such as the solder pad 214 of the crystal moon 212, the solder pad 214 is contaminated. Therefore, in the subsequent wire bonding operation, the gold wire cannot be firmly adhered to the pad 214. In this case, Therefore, it is necessary to increase the spacing between the wafer 21 and the pad 214 to reduce the probability of the material 214 being contaminated. Thus, the usable space of the substrate 202 will be wasted. In the process of forming the primer, if there is overflow glue generated In this case, the present embodiment can effectively prevent the overflow glue from being contaminated to the pads of the adjacent wafers. Referring to FIG. 6B, a schematic diagram of the overflow distribution of the flip chip-molding method of the present embodiment is shown. One of the glue 216 overflows 2 18 will _ flow into the space of the trench 208 first, and prevent the overflow 218 from flowing to the pad 214 to contaminate the pad 214, so that the spacing between the die 21 〇 and the pad 214 does not need to be increased, thereby saving The space that can be used for the substrate 202. In addition, in order to electrically connect the wafer 212 and the pad 214, after the step 1 to 8, the flip chip packaging method may further include the step of forming a plurality of gold wires 217. Please refer to FIG. 7A and 7B, FIG. 7A is a plan view showing a substrate on which a plurality of gold wires are formed in the embodiment, and FIG. 7B is a cross-sectional view showing the substrate along the 1C-1C' in FIG. 7A. The gold wire 217 connects the wafer 212 and the pad 214' to make the wafer 212 via the gold wire 217 and the solder 9 1377629

♦ « I TW4391PA pad 214 electrical connection. In addition, after step 108, the flip chip packaging method may further include the step of cutting the substrate 202 along the dicing street 204 to form the flip chip package 220. Please refer to FIG. 8 , which is a schematic diagram of the flip chip package of the embodiment. After the substrate 202 is cut using a dicing blade 222, the flip chip packages 220 and 224 are formed, wherein the wafer 212 and the gold wire 217 are covered with the sealant 226 before the dicing to protect the gold wire 217 from moisture and foreign matter. In addition, during the cutting process, since the texture of the insulating layer 206 is soft, it is easy to form a burr at the edge after the cutting. However, due to the formation of the grooves, the scribe lines having the grooves have less insulating layer composition than the etched lines having no grooves, and when the insulating layer has less composition, the cutting is performed. The burrs remaining in the subsequent flip chip package also naturally become less. In this way, it contributes to the improvement of the quality of the finished package. In the wire bonding operation, in order to make the gold wire firmly fixed on the pad 214, the pad must be kept clean and no impurities can be on the pad, otherwise the gold wire ® cannot be stabilized on the pad. If the solder pad is too polluted, for example, the glue of the primer 216 flows onto the pad 214 (as shown in Fig. 6A), and even the problem of inability to wire may occur. Therefore, the trench 208 of the embodiment is formed such that when the glue 218 of the primer 216 occurs, the overflow 218 first fills the space in the trench 208 without flowing to the pad 214, thereby reducing the contamination welding. The opportunity of the pad 214 allows the gold wire 217 in the subsequent wire bonding operation to be stably fixed to the pad 214. In addition, due to the formation of the grooves, the area of the overflow can be controlled to be smaller, and the distance between the wafers can be narrowed to 1377629 • I «

The TW4391PA allows the substrate to accommodate more wafers and increases substrate utilization. Referring to Figure 9, a schematic view of another structure of the trench of the embodiment is shown. The insulating layer 302 has a plurality of trenches 304 that are located on the scribe lines 306. The trench formed by the flip chip packaging method of the present invention is not limited to the trench pattern of Fig. 1, and the distribution of the trench can be changed in accordance with the manner in which the flip chip package is distributed on the substrate. Therefore, the configuration of the various grooves increases the planning flexibility of the process. In addition, the size of the groove can be adjusted according to the amount of the glue. For example, when the amount of the glue is required to match the size of the product, the size of the groove can be matched to form a groove with a larger volume to accommodate more overflow. the amount. In this way, the area of the overflow can still be controlled to be small. The flip chip packaging method disclosed in the above embodiments of the present invention has a plurality of advantages. The following only some of the advantages are described as follows: 1) The formation of the trenches reduces the probability of contamination of the pads adjacent to the wafer by the primer, and improves the subsequent bonding. The success rate of the work and the quality of the wire. ® 2) The formation of the grooves allows the area of the overflow to be reduced, so the distance between the wafers is shortened, so that the same substrate area can accommodate more small-sized grains. Therefore, the use rate of the substrate is improved. 3) The formation of the trenches reduces the number of layers of the softer insulating layer. After the substrate is cut into the flip chip package, the remaining edges of the chip edge of the flip chip package are also reduced, thereby improving the flip chip package. Finished product quality. 4) The formation of the trenches reduces the amount of warpage of the substrate, thereby improving the process yield of the flip chip package. 1377629 • 4

TW4391PA In summary, although the invention has been described above in terms of a preferred embodiment, it is not intended to limit the invention. It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

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TW4391PA [Simple Description of the Drawings] FIG. 1 is a flow chart showing a flip chip packaging method in accordance with a preferred embodiment of the present invention. FIG. 2A is a plan view showing the substrate of the embodiment. FIG. 2B is a front view of the substrate in FIG. 2A. Fig. 3A is a plan view showing the substrate on which the insulating layer and the pad are formed in the embodiment. Fig. 3B is a cross-sectional view of the substrate taken along line 1A-1A' in Fig. 3A. • Fig. 4A is a plan view showing the substrate on which the wafer is provided in the embodiment. Fig. 4B is a cross-sectional view of the substrate taken along line 1B-1B' in Fig. 4A. Fig. 5 is a plan view showing the substrate in the form of a primer in the embodiment. FIG. 6A is a schematic view showing the distribution of the overflow gel when no groove is formed. Fig. 6B is a schematic view showing the distribution of the overflow gel of the flip chip forming method of the present embodiment. Fig. 7A is a plan view showing the substrate on which a plurality of gold wires are formed in the embodiment. Figure 7 is a cross-sectional view showing the substrate edge 1C-1C' in the seventh drawing. FIG. 8 is a schematic view showing the flip chip package of the embodiment. FIG. 9 is a schematic view showing another structure of the trench of the embodiment. 13 1377629

TW4391PA [Description of main component symbols] 202: Substrate 204, 306: dicing streets 206, 302: insulating layers 208, 304: trenches 210, 212: wafer 211: solder balls 213: openings 214: pads 215: flip chip 216: primer 217: gold wire 218, 221: overflow glue 219: - side 220, 224: flip chip 222: cutting blade 226: sealant

Claims (1)

1. Patent application scope: 咐月日修正 replacement page 2〇12M/3_1sl application & correction of the flip chip packaging method, including: (a) providing a substrate 'with dicing track; sample flying ^ 绝 = on the substrate The upper insulating layer has a trench, and the trench is located on the dicing street. The second surface is disposed on the substrate, and the wafer is disposed at a position==one side and adjacent to the trench, and the wafer is overlaid. a method of crystallizing a is electrically connected to the substrate; and (d) forming a bottom from the side of the wafer and the substrate from the side adjacent to the scriber y y y. A method of crystal sealing I, wherein the width of the trench is less than or equal to the width of the scribe line. 3::: Please refer to the flip chip package method of item 1, wherein the length of the trench is less than or equal to the long-term production of the scribe line. 4· such as ^ patent scope! The flip chip method of claim, wherein the insulating layer has a plurality of trenches, the trenches being located on the scribe line. 5. The flip chip packaging method of claim 1, wherein in the step (0), the wafer has a plurality of solder balls, and the wafer is electrically connected to the substrate by the solder balls. The flip chip packaging method according to the above aspect of the invention, wherein in the step (4), the trench is formed by an exposure development technique. 7. The coating according to claim 1 of the patent application scope. The crystal encapsulation method, wherein in the step (4), the primer is formed by Jetting. The flip chip packaging method according to claim 1, wherein the 097115987 1013125905-0 15 1377629 April, 101, 03, 曰, 翎, 5th, revised, replacement page, -____ " 2012/4/3_1a In the application and correction step (d), the primer is formed by dispensing (DispensingorNo-I^low). 9. The flip chip packaging method of claim 1, wherein after the step (d), the method further comprises: cutting the substrate along the scribe line to form a flip chip package. The flip chip packaging method as described in claim 1, further comprising: forming A wafer is mounted on the substrate, and the wafer and the other wafer are respectively located on both sides of the dicing line. 11. The flip chip packaging method according to claim 10, wherein the substrate has a plurality of a solder pad formed between the dicing street and the other wafer, the method further comprising: forming a plurality of gold wires to electrically charge the other wafer via the gold wires and the pads 12. The flip chip packaging method of claim 1, wherein the groove height of the trench is less than the thickness of the insulating layer. 0971.15987 1013125905-0 16