CN101276766A - Flip Chip Packaging Method - Google Patents

Abstract

The invention discloses a flip chip packaging method, which comprises the steps of providing a substrate, wherein the substrate is provided with a cutting channel; forming an insulating layer on the substrate, wherein the insulating layer is provided with a groove which is positioned on the cutting path; arranging a chip on the substrate, wherein the arrangement position of the chip is positioned at one side of the groove and is adjacent to the groove, and the chip is electrically connected with the substrate in a flip chip bonding mode; and forming a bottom glue between the chip and the substrate from one side of the chip adjacent to the cutting channel.

Description

Flip Chip Packaging Method

【Technical field】

The present invention relates to a method of flip-chip packaging, and in particular to a method of flip-chip packaging that improves substrate utilization.

【Background technique】

In the era of ever-changing technology, electronic products composed of integrated circuit components have become an indispensable tool in the daily life of modern people. With the trend of electronic products moving toward thinner and smaller designs, semiconductor packaging technology has relatively developed many high-density semiconductor packaging forms, such as flip-chip packages.

During the flip-chip packaging process, a primer needs to be formed between the chip and the substrate. However, when the chip is very thin or has a large area, it is easy to cause glue overflow. The overflowing glue will contaminate the bonding pads of adjacent chips, so that the gold wires are not easy to be fixed on the contaminated bonding pads during the subsequent wire bonding operation. Moreover, recently, customers have requested that the size of the chip be reduced day by day, so that the distance between the chip and the bonding pad of the adjacent chip is shortened accordingly, so that the overflowed primer is more likely to contaminate the bonding pad of the adjacent chip.

【Content of invention】

In view of this, the present invention is to provide a flip-chip packaging method. A groove is formed between the place where the primer is formed and the bonding pad of the adjacent chip. When the overflow of the primer occurs, the overflow will be filled first. The space in the groove does not flow to the bonding pads of adjacent chips, thereby reducing the chance of polluting the bonding pads of adjacent chips, and improving the success rate of bonding operations of adjacent chips, so as to improve product yield and reduce costs. Moreover, due to the formation of the grooves, the distance between the chips can be shortened without the problem of solder pads being polluted by overflowing glue from the primer. Therefore, the same substrate area can accommodate more chips, which improves the utilization rate of the substrate.

According to one aspect of the present invention, a flip-chip packaging method is proposed, including providing a substrate, the substrate has a dicing line; forming an insulating layer on the substrate, the insulating layer has a groove, and the groove is located on the dicing line; placing a chip Installed on the substrate, the chip is located on one side of the trench and adjacent to the trench, and the chip is electrically connected to the substrate in the form of flip-chip bonding; and, a primer is formed from the side of the chip adjacent to the dicing line between the chip and the substrate.

In order to make the above content of the present invention more obvious and understandable, a preferred embodiment is specifically cited below, together with the accompanying drawings, and described in detail as follows:

【Description of drawings】

FIG. 1 shows a flowchart of a flip-chip packaging method according to a preferred embodiment of the present invention.

FIG. 2A is a top view of the substrate of this embodiment.

FIG. 2B is a front view of the substrate in FIG. 2A.

FIG. 3A is a top view of the substrate formed with the insulating layer and the pads of the present embodiment.

FIG. 3B is a cross-sectional view of the substrate in FIG. 3A along 1A-1A'.

FIG. 4A is a top view of a substrate provided with chips in this embodiment.

FIG. 4B is a cross-sectional view of the substrate in FIG. 4A along 1B-1B'.

FIG. 5 is a top view of the substrate when the primer is formed in this embodiment.

FIG. 6A is a schematic diagram showing the distribution of glue overflow when no groove is formed.

FIG. 6B is a schematic diagram of the overflow distribution of the flip-chip packaging method with grooves formed in this embodiment.

FIG. 7A is a top view of a substrate formed with a plurality of gold wires in this embodiment.

FIG. 7B is a cross-sectional view of the substrate along line 1C-1C' in FIG. 7A.

FIG. 8 is a schematic diagram of the flip-chip package of this embodiment.

FIG. 9 is a schematic diagram of another structure of the groove of this embodiment.

【Detailed ways】

The present invention proposes a flip-chip packaging method, which includes providing a substrate with a dicing line; forming an insulating layer on the substrate, the insulating layer has a groove, and the groove is located on the dicing line; disposing a chip on the substrate, The chip is placed on one side of the trench and adjacent to the trench, and the chip is electrically connected to the substrate by flip-chip bonding; and, a primer is formed between the chip and the substrate from the side of the chip adjacent to the dicing line between. When the overflow of the primer occurs, the overflow will first fill the space in the trench and will not flow to the bonding pads of the adjacent chips, thus reducing the chance of contaminating the bonding pads of the adjacent chips. A preferred embodiment is given below as a detailed description, but this embodiment is only one of several implementations under the inventive spirit of the present invention, and the words and icons in its description will not limit the intended protection scope of the present invention .

Please refer to FIG. 1 , which shows a flowchart of a flip-chip packaging method according to a preferred embodiment of the present invention. The flip-chip packaging method includes the following steps. First, please refer to FIG. 2A and FIG. 2B at the same time. FIG. 2A shows a top view of the substrate of this embodiment, and FIG. 2B shows a front view of the substrate in FIG. 2A . In step 102 , a substrate 202 having a dicing line 204 is provided.

Next, please refer to FIG. 3A and FIG. 3B at the same time. FIG. 3A shows a top view of the substrate formed with insulating layers and pads in this embodiment, and FIG. 3B shows a cross-sectional view of the substrate in FIG. 3A along 1A-1A'. In step 104 , an insulating layer 206 is formed on the substrate 202 , the insulating layer 206 has a groove 208 located on the scribe line 204 . Wherein, the insulating layer 206 includes green paint, isolation layer, ABF dielectric layer (Ajinomoto Build-up film) or other dielectric materials. The width of the groove 208 can be less than or equal to the width of the cutting line 204, and the length of the groove 208 can be less than or equal to the length of the cutting line 204. In this embodiment, the width and length of the groove 208 are respectively smaller than the width and length of the cutting line 204 As an example for illustration. In addition, in this step, the flip-chip packaging method further includes forming a plurality of soldering pads 214 on the substrate 202. The grooves 208 are formed, for example, by an exposure and development technique. The grooves 208 can correspond to the soldering pads 214 in forming the insulating layer 206. The process of opening 213 is completed together. Therefore, the formation of the trench is quite simple without additional process cost.

In addition, the recessed space formed by the groove 208 absorbs the thermal expansion of the substrate 202 due to the heating action in the subsequent process, so that the overall warpage of the substrate 202 is reduced, thus improving the process qualification of the flip-chip package. Rate.

Then, please refer to FIG. 4A and FIG. 4B at the same time. FIG. 4A shows a top view of the substrate provided with chips in this embodiment, and FIG. 4B shows a cross-sectional view of the substrate in FIG. 4A along 1B-1B'. In step 106 , a chip 210 is disposed on the substrate 202 . The chip 210 is disposed on one side of the trench 208 and adjacent to the trench 208 . The chip 210 is electrically connected to the substrate 202 by flip-chip bonding. In addition, the chip 210 further has a plurality of solder balls 211 , and the chip 210 is electrically connected to the substrate 202 through the solder balls 211 . In addition, in this step, another chip 212 can also be formed on the substrate 202 , and the chip 210 and the chip 212 are respectively located on two sides of the dicing line 204 . The chip 212 can be directly disposed on the substrate 202 or stacked on the flip-chip chip. In this embodiment, the form of stacking on the flip-chip chip 215 is taken as an example for illustration. The welding pad 214 on the substrate 202 is used to electrically connect with the chip 212. The electrical connection can be completed by wire bonding. In order to make the length of the gold wire moderate, the welding pad 214 is formed between the dicing line 204 and the chip 212. .

Then, please also refer to FIG. 5 , which shows a top view of the substrate when the primer is formed in this embodiment. In step 108, the primer 216 is formed between the chip 210 and the substrate 202 from the side 219 of the chip 210 adjacent to the dicing line 204. When the primer 216 is initially placed on the side 219 adjacent to the chip 210, by According to the siphon principle, the primer 216 will be slowly sucked between the chip 210 and the substrate 202 . Wherein, the method of forming the primer 216 can be Jetting or Dispensing or No-Flow.

In the case of not forming a groove, if there is glue overflow during the process of forming the primer, the overflow glue may contaminate the pad. Please refer to FIG. 6A , which is a schematic diagram of the overflow glue distribution when no groove is formed. When the insulating layer 206 does not have a groove, an overflow glue 221 of the primer can only flow to the bonding pad 214 of the adjacent chip, such as the chip 212, because there is no groove to accommodate the bonding pad 214, and the bonding pad 214 is affected. pollute. Therefore, the gold wire cannot be firmly adhered to the bonding pad 214 during the subsequent wire bonding operation. In this case, it is necessary to increase the distance between the chip 210 and the bonding pad 214 to reduce the probability of the bonding pad 214 being contaminated. In this way, the available space of the substrate 202 will be wasted.

In the process of forming the primer, if there is glue overflow, this embodiment can effectively prevent the overflow glue from polluting the bonding pads of adjacent chips. Please refer to FIG. 6B , which is a schematic diagram of the overflow distribution of the flip-chip packaging method with grooves formed in this embodiment. An overflow glue 218 of the primer 216 will flow into the space of the groove 208 first, and avoid the overflow glue 218 from flowing to the welding pad 214 and polluting the welding pad 214, so that the distance between the crystal grain 210 and the welding pad 214 does not need to be increased. Therefore, the available space of the substrate 202 is saved.

In addition, in order to electrically connect the chip 212 and the bonding pad 214 , after the step 108 , the flip-chip packaging method may further include a step of forming a plurality of gold wires 217 . Please refer to FIG. 7A and FIG. 7B. FIG. 7A shows a top view of a substrate formed with a plurality of gold wires in this embodiment, and FIG. 7B shows a cross-sectional view of the substrate along line 1C-1C' in FIG. 7A. Through the wire bonding operation, a plurality of gold wires 217 are formed to connect the chip 212 and the bonding pad 214 , so that the chip 212 is electrically connected to the bonding pad 214 through the gold wire 217 .

In addition, after step 108 , the flip-chip packaging method may further include a step of cutting the substrate 202 along the dicing line 204 to form the flip-chip package 220 . Please refer to FIG. 8 , which shows a schematic diagram of the flip-chip package of this embodiment. After dicing the substrate 202 with a dicing knife 222 , flip-chip packages 220 and 224 are formed. In order to protect the gold wires 217 from moisture and foreign objects, the chip 212 and the gold wires 217 are covered with an encapsulant 226 before dicing.

In addition, during the cutting process, since the texture of the insulating layer 206 is relatively soft, it is easy to form burrs on the edges after cutting. However, due to the formation of the groove, the insulating layer composition of the scribe line with the groove is less than that of the scribe line without the groove. When the composition of the insulating layer is less, the dicing The remaining burrs of the final flip-chip package also naturally become less. In this way, it is helpful to improve the quality of the finished product of the flip-chip package.

During the wire bonding operation, in order to make the gold wires firmly fixed on the welding pads 214 , the welding pads must be kept clean without impurities on the welding pads, otherwise the gold wires cannot be firmly fixed on the welding pads. If the pads are too polluted, for example, the glue overflow of the primer 216 flows onto the pads 214 (as shown in FIG. 6A ), and even the problem of inability to bond wires may occur. Therefore, the groove 208 of this embodiment is formed so that when the overflow glue 218 of the primer 216 occurs, the overflow glue 218 will first fill the space in the groove 208 and will not flow to the solder pad 214, thus reducing the pollution of solder pads. The opportunity of the pad 214 enables the gold wire 217 in the subsequent wire bonding operation to be stably fixed on the pad 214 . In addition, due to the formation of the grooves, the area of glue overflow can also be controlled to be smaller, and the distance between chips can be shortened, so that the substrate can accommodate more chips and improve the utilization rate of the substrate.

Please refer to FIG. 9 , which shows a schematic diagram of another structure of the groove of this embodiment. The insulating layer 302 has a plurality of trenches 304 located on the dicing lines 306 . The trenches formed by the flip-chip packaging method of the present invention are not limited to the trench form shown in FIG. 1 , and the distribution of the trenches can be changed according to the distribution of the flip-chip package components on the substrate. Therefore, the arrangement of various grooves increases the planning flexibility of the manufacturing process.

In addition, the size of the groove can be adjusted according to the amount of primer. For example, when the amount of primer is required to match the size of the product, the size of the groove can be matched to form a groove with a larger volume to accommodate more excess glue. In this way, the area of glue overflow can still be controlled to be small.

The flip-chip packaging method disclosed in the above-mentioned embodiments of the present invention has many advantages, and only some of the advantages are listed below:

1) The formation of the groove reduces the probability of the bonding pad adjacent to the chip being polluted by the primer, improves the success rate of the subsequent wire bonding operation and ensures the quality of the wire bonding.

2) The formation of grooves can reduce the area of glue overflow, so the distance between chips can be shortened, so that the same substrate area can accommodate more crystal grains with smaller sizes. Therefore, the usage rate of the substrate is improved.

3) The formation of grooves reduces the number of soft insulating layers. After the substrate is cut into flip-chip packages, the remaining burrs on the cutting edges of flip-chip packages are also reduced, thus improving the performance of flip-chip packages. Finished quality.

4) The formation of the groove reduces the warpage of the substrate, thus improving the yield of the flip-chip package.

In summary, although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.

Claims (11)

1. crystal coated encapsulation method comprises:

(a) provide a substrate, have a Cutting Road;

(b) form an insulating barrier on this substrate, this insulating barrier has a groove, and this groove is positioned on this Cutting Road;

(c) chip is arranged on this substrate, the position that is provided with of this chip is positioned at a side of this groove and is adjacent to this groove, and this chip is electrically connected at this substrate in the mode of chip bonding; And

(d) side from this chip of contiguous this Cutting Road begins to form a primer between this chip and this substrate.

2. crystal coated encapsulation method according to claim 1 is characterized in that, the width of this groove is less than or equal to the width of this Cutting Road.

3. crystal coated encapsulation method according to claim 1 is characterized in that, the length of this groove is less than or equal to the length of this Cutting Road.

4. crystal coated encapsulation method according to claim 1 is characterized in that this insulating barrier has a plurality of grooves, and described groove is positioned on this Cutting Road.

5. crystal coated encapsulation method according to claim 1 is characterized in that, in this step (c), this chip has a plurality of tin balls, and this chip electrically connects by described tin ball and this substrate.

6. crystal coated encapsulation method according to claim 1 is characterized in that, in this step (a), this groove forms with an exposure imaging technology.

7. crystal coated encapsulation method according to claim 1 is characterized in that, in this step (d), (Jetting) forms this primer with spray regime.

8. crystal coated encapsulation method according to claim 1 is characterized in that, in this step (d), (Dispensing or No-Flow) forms this primer in a glue mode.

9. crystal coated encapsulation method according to claim 1 is characterized in that, in this step (d) afterwards, this method more comprises:

Cut this substrate along this Cutting Road, to form a flip chip.

10. crystal coated encapsulation method according to claim 1 is characterized in that, more comprises:

Form another chip on this substrate, this chip and this another chip lay respectively at the both sides of this Cutting Road.

11. crystal coated encapsulation method according to claim 10 is characterized in that, has more a plurality of weld pads on this substrate, described pad-shaped is formed between this Cutting Road and this another chip, and this method more comprises:

Form many gold threads, so that this another chip electrically connects via described gold thread and described weld pad respectively.

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