CN103515452B - Power rectifier device and its manufacturing method and its related semiconductor product - Google Patents
Power rectifier device and its manufacturing method and its related semiconductor product Download PDFInfo
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Abstract
本发明涉及功率整流器件和其制造方法及其相关半导体产品。该功率整流器件包括含有碳化硅的漂移层（110），设置在漂移层上的肖特基电极（120），肖特基电极和漂移层的表面提供肖特基接触（130），其中漂移层具有平面化的表面，使得漂移层表面的任何坑（140）的深度近似小于Dmax=Eb/Fa，其中Eb是金属‑半导体势垒高度，以及Fa是雪崩击穿场。本发明是有利的，因为其提供了具有改善平滑度的（漂移层的）表面的功率整流器件，以及制造具有降低泄漏电流的功率整流器件的方法。
The present invention relates to a power rectifying device, its manufacturing method and related semiconductor products. The power rectifier device includes a drift layer (110) containing silicon carbide, a Schottky electrode (120) arranged on the drift layer, and a Schottky contact (130) is provided on the surface of the Schottky electrode and the drift layer, wherein the drift layer With a planarized surface, the depth of any pit (140) in the drift layer surface is approximately less than D max =E b /F a , where E b is the metal-semiconductor barrier height and F a is the avalanche breakdown field. The present invention is advantageous because it provides a power rectifying device with improved smoothness of the surface (of the drift layer), and a method of manufacturing a power rectifying device with reduced leakage current.
Description
技术领域technical field
本发明涉及高功率半导体器件的技术领域，尤其涉及基于高功率碳化硅(SiC)的器件，如SiC肖特基势垒功率整流器件(电源整流器件，power rectifier device)以及制造这类功率整流器件的方法。The present invention relates to the technical field of high-power semiconductor devices, in particular to devices based on high-power silicon carbide (SiC), such as SiC Schottky barrier power rectifier devices (power rectifier devices, power rectifier devices) and the manufacture of such power rectifier devices Methods.
背景技术Background technique
碳化硅肖特基势垒器件是具有比常规的硅器件更低功率损耗的高性能功率器件，并且可以以更高的开关频率(switching frequency)操作。SiC显示出具有高击穿电场、高热传导性和高饱和电子漂移速度的优点。SiC是一种宽带隙半导体，并且可有利地用于制造低功率损耗转换应用的器件，例如整流器。Silicon carbide Schottky barrier devices are high performance power devices with lower power losses than conventional silicon devices and can operate at higher switching frequencies. SiC exhibits the advantages of high breakdown electric field, high thermal conductivity, and high saturation electron drift velocity. SiC is a wide bandgap semiconductor and can be advantageously used to fabricate devices for low power loss conversion applications, such as rectifiers.
通常，功率整流器件可以由外延生长的SiC层制造。由于位错缺陷，如生长坑(pit，凹坑)、小丘(异常析出，hillock)和生长台阶，外延的SiC层通常表现出若干不规则。这样的形态缺陷会导致电场集中区域，增加了电子从肖特基金属隧穿到SiC漂移层的可能性，从而增加了在高阻塞电压(闭锁电压，blocking voltage)时的泄漏电流。由于硅和碳沿晶片表面的扩散，功率整流器件的制造过程的高温阶段，像是例如注入退火(implant anneal)，还会导致表面粗糙化。Typically, power rectifying devices can be fabricated from epitaxially grown SiC layers. Epitaxial SiC layers usually exhibit several irregularities due to dislocation defects, such as growth pits, hillocks and growth steps. Such morphological defects lead to areas of concentrated electric field, increasing the possibility of electron tunneling from the Schottky metal to the SiC drift layer, thereby increasing the leakage current at high blocking voltage (blocking voltage). High temperature stages of the fabrication process of power rectifying devices, such as eg implant anneal, also result in surface roughening due to the diffusion of silicon and carbon along the wafer surface.
电场集中的图案取决于表面不规则的形态。与沿外延生长方向的深度相比具有相对较窄宽度的针形坑可以导致例如电场的高度局部集中。另一方面，具有相对较大的横向延伸的浅坑可以导致较小程度的电场集中。坑的曲率半径和深度、所施加的电压以及掺杂SiC层的厚度是可以影响功率整流器件泄漏电流的参数的例子。The pattern of electric field concentration depends on the morphology of surface irregularities. Needle-shaped pits having a relatively narrow width compared to the depth along the epitaxial growth direction can lead, for example, to a high local concentration of the electric field. On the other hand, shallow pits with a relatively large lateral extension may result in a smaller degree of electric field concentration. The radius of curvature and depth of the pit, the applied voltage, and the thickness of the doped SiC layer are examples of parameters that can affect the leakage current of a power rectifying device.
因此，提供漂移层的表面具有改善的平滑度的功率整流器件以及相应的制造方法将是所期望的。Accordingly, it would be desirable to provide a power rectifying device with improved smoothness of the surface of the drift layer and a corresponding method of manufacture.
发明内容Contents of the invention
本发明的至少一些实施方式的目的是至少缓解上述现有技术的上述缺陷中的至少一些，并且提供现有技术的改善替代。It is an object of at least some embodiments of the present invention to at least alleviate at least some of the above-mentioned disadvantages of the prior art described above and to provide an improved alternative to the prior art.
一般来说，本发明的目的是提供高电压功率转换半导体器件，具体是具有改善平滑度的(漂移层)表面的SiC肖特基势垒功率整流器件。进一步，本发明的目的是提供制造具有降低泄漏电流的功率整流器件的方法是。In general, it is an object of the present invention to provide high voltage power conversion semiconductor devices, in particular SiC Schottky barrier power rectification devices with improved smoothness (drift layer) surfaces. Further, it is an object of the present invention to provide a method of manufacturing a power rectifying device with reduced leakage current.
本发明的这些和其他目的通过具有在本发明中定义的特征的功率整流器件和方法实现。通过本发明的示例性实施方式实现本发明的其它目的。These and other objects of the present invention are achieved by a power rectifying device and method having the features defined in the present invention. Other objects of the present invention are achieved by the exemplary embodiments of the present invention.
因此，根据本发明的第一方面，提供了功率整流器件。功率整流器件包括漂移层，该漂移层包括碳化硅和设置在漂移层上的肖特基电极。漂移层和肖特基电极提供肖特基接触，其中漂移层具有平面化的表面，使得漂移层表面的任何坑的深度近似小于Dmax＝Eb/Fa，其中Eb是金属-半导体能量势垒高度，以及Fa是雪崩击穿场。Therefore, according to a first aspect of the present invention, a power rectifying device is provided. A power rectifying device includes a drift layer including silicon carbide and a Schottky electrode disposed on the drift layer. The drift layer and the Schottky electrode provide a Schottky contact, where the drift layer has a planarized surface such that the depth of any pit on the surface of the drift layer is approximately less than Dmax = Eb / Fa , where Eb is the metal-semiconductor energy is the barrier height, and F a is the avalanche breakdown field.
根据本发明的第二方面，提供了制造功率整流器件的方法。该方法包括以下步骤：形成包括SiC的漂移层，在漂移层表面上形成牺牲层，将在牺牲层中获得的形态(或结构)转移至漂移层的表面，以及在漂移层上形成肖特基电极，其中肖特基电极和漂移层的表面提供肖特基接触。According to a second aspect of the present invention, a method of manufacturing a power rectifying device is provided. The method comprises the steps of forming a drift layer comprising SiC, forming a sacrificial layer on the surface of the drift layer, transferring the morphology (or structure) obtained in the sacrificial layer to the surface of the drift layer, and forming a Schottky layer on the drift layer electrode, wherein the Schottky electrode and the surface of the drift layer provide a Schottky contact.
本发明确信，通过消除具有特定深度的坑，可以获得凹坑(pitting)对功率整流器件击穿性能可忽略的(或至少降低的)影响。合适的坑的最大深度可以被限定为金属-半导体势垒能量高度与雪崩击穿场之间的比率。The present inventors believe that by eliminating pits with a certain depth, a negligible (or at least reduced) effect of pitting on the breakdown performance of a power rectifying device can be obtained. A suitable maximum depth of a pit can be defined as the ratio between the metal-semiconductor barrier energy height and the avalanche breakdown field.
根据将牺牲层的表面形态转移到漂移层的(有坑的)表面的制造方法，可以获得这样的表面。有利地，牺牲层具有比漂移层的初始(有坑的)表面更加平滑的表面。Such a surface can be obtained according to a fabrication method that transfers the surface morphology of the sacrificial layer to the (pitted) surface of the drift layer. Advantageously, the sacrificial layer has a smoother surface than the original (cratered) surface of the drift layer.
功率整流器件可以是SiC肖特基势垒功率整流器件，如二极管，或包括至少一个肖特基势垒结的半导体器件。The power rectifying device may be a SiC Schottky barrier power rectifying device, such as a diode, or a semiconductor device including at least one Schottky barrier junction.
术语“坑”应当被理解为在SiC表面中的任何空洞、孔或凹痕。坑可以与形态缺陷相关，例如结晶位错，如在基板的外延生长期间发生的螺旋位错和边缘位错；或由处理(外延生长之后)引起的后生长缺陷，如退火期间碳和硅原子的扩散；或离子轰击诱导的损伤。The term "pit" should be understood as any void, hole or indentation in the SiC surface. Pits can be associated with morphological defects, such as crystallographic dislocations, such as screw and edge dislocations that occur during epitaxial growth of the substrate; or post-growth defects caused by processing (after epitaxial growth), such as carbon and silicon atoms during annealing diffusion; or ion bombardment-induced damage.
坑可以包括位于漂移层表面，并经由侧壁延伸到相对底部的缝隙。坑可以在漂移层中以外延生长的方向延伸，延伸长度可以被称为坑的深度。缝隙的横向延伸可以被称为缝隙的宽度，并且可以是圆形的或任何其他形状。坑的底部可以是，例如平坦的，或形成由侧壁的锥度(tapering)限定的锐角。坑的底部还可以由宽度或曲率半径限定。坑的深度、缝隙和底部的宽度以及侧壁的锥度限定坑的形状。The pit may include a slit located on the surface of the drift layer and extending to the opposite bottom via the sidewall. The pit may extend in the direction of epitaxial growth in the drift layer, and the extended length may be referred to as the depth of the pit. The lateral extension of the slot may be referred to as the width of the slot and may be circular or any other shape. The bottom of the well may, for example, be flat, or form an acute angle defined by the tapering of the side walls. The bottom of the well may also be defined by a width or a radius of curvature. The depth of the pit, the width of the slot and bottom, and the taper of the side walls define the shape of the pit.
由于肖特基电极设置在漂移层上，金属可以部分或全部填充坑，从而在半导体材料中产生金属凸出。从金属层突出部分的形状可以与坑的形状相对应，并且限定电场集中。Since the Schottky electrode is disposed on the drift layer, the metal can partially or completely fill the pit, thereby creating a metal protrusion in the semiconductor material. The shape of the protruding portion from the metal layer may correspond to the shape of the pit and define the electric field concentration.
功率整流器件的反向电流受隧穿支配，该隧穿受金属-半导体界面的势垒高度和表面形态影响。在表面延伸到漂移层中的坑会引起在漂移层中的电场集中，这增加了电子隧穿的可能性。The reverse current of power rectifier devices is dominated by tunneling, which is affected by the barrier height and surface morphology of the metal-semiconductor interface. A pit extending into the drift layer at the surface causes an electric field concentration in the drift layer, which increases the probability of electron tunneling.
根据本发明，如果比Eb/Fa纳米更深的坑被消除，功率整流器件中电子隧穿的可能性会显著降低。半导体中最大肖特基金属凹痕可以被限制，从而降低电子隧穿的可能性以及其对功率整流器件击穿性能的影响。According to the present invention, if pits deeper than Eb /Fa nanometers are eliminated, the possibility of electron tunneling in power rectifying devices is significantly reduced. The maximum Schottky metal notch in semiconductors can be limited, thereby reducing the possibility of electron tunneling and its impact on the breakdown performance of power rectifier devices.
肖特基金属可以是，例如溅射的或蒸发的钛、钨或钼。The Schottky metal can be, for example, sputtered or evaporated titanium, tungsten or molybdenum.
根据一个实施方式，直径或尺寸小于约2微米的漂移层表面的任何坑的深度可以小于约5纳米。这样形状的坑可以是不足够窄和深从而产生足够高以排除势垒高度的电场集中。因此，该实施方式在降低凹坑对功率整流器件的电击穿性能的影响方面是有利的。According to one embodiment, any pits on the surface of the drift layer having a diameter or size of less than about 2 microns may have a depth of less than about 5 nanometers. Such shaped pits may not be narrow and deep enough to create an electric field concentration high enough to exclude barrier heights. Therefore, this embodiment is advantageous in reducing the influence of the pits on the electrical breakdown performance of the power rectifying device.
根据一个实施方式，功率整流器件在其外围可以包括结终端区(junctiontermination region)，这对在器件边缘降低电场聚集是有利的，从而降低早期电击穿的风险。终端区可以包括，例如在器件外围附近设置的连续的带。According to one embodiment, the power rectifying device may include a junction termination region at its periphery, which is advantageous for reducing electric field concentration at the edge of the device, thereby reducing the risk of early electrical breakdown. The termination region may comprise, for example, a continuous strip disposed about the periphery of the device.
根据一个实施方式，功率整流器件的漂移层包括-p型区域阵列(耗尽阻塞物(depletion stopper)，或场阻塞物(field stopper))，这可以有利地屏蔽肖特基势垒金属暴露于高电场。P-型区域可以有利地以阵列布置。P-型掺杂物的例子包括，例如铝和硼。According to one embodiment, the drift layer of the power rectifier device includes an array of p-type regions (depletion stoppers, or field stoppers), which can advantageously shield the Schottky barrier metal from exposure to high electric field. The P-type regions may advantageously be arranged in an array. Examples of P-type dopants include, for example, aluminum and boron.
根据一个实施方式，功率整流器的漂移层可以包括近表面部分，其设置有比漂移层其余部分的掺杂高1.5到8倍的掺杂比(或是漂移层其余部分的掺杂1.5到8倍高的掺杂比)。漂移层的近表面部分的深度可以近似等于p-型耗尽阻塞物的深度。According to one embodiment, the drift layer of the power rectifier may comprise a near-surface portion provided with a doping ratio 1.5 to 8 times higher than the doping of the rest of the drift layer (or 1.5 to 8 times the doping of the rest of the drift layer). high doping ratio). The depth of the near-surface portion of the drift layer may be approximately equal to the depth of the p-type depletion stopper.
根据一个实施方式，功率整流器件可以有利地具有设置有耗尽阻塞区的外围。可以布置该耗尽阻塞区，如p-掺杂区，以便在电压阻塞期间，防止功率整流器件的耗尽区到达器件的边缘。According to one embodiment, the power rectifying device may advantageously have a periphery provided with a depletion blocking region. The depletion blocking region, such as a p-doped region, may be arranged to prevent the depletion region of the power rectifying device from reaching the edge of the device during voltage blocking.
根据一个实施方式，功率整流器件可以包括分配在由结终端区所限定区域内的浪涌pn二极管(surge pn diode)阵列，并且其中任何浪涌pn二极管设置有欧姆接触，并且具有漂移层厚度两倍的最小横向延伸。According to one embodiment, the power rectifying device may comprise an array of surge pn diodes (surge pn diodes) distributed within the region defined by the junction termination region, and wherein any surge pn diode is provided with an ohmic contact and has a drift layer thickness of two times the minimum lateral extension.
根据一个实施方式，漂移层可以有利地是n-型导电性的。According to one embodiment, the drift layer may advantageously be of n-type conductivity.
根据一个实施方式，将在牺牲层上获得的形态转移到漂移层表面的步骤可以包括利用蚀刻工艺去除牺牲层。蚀刻优于其他材料去除工艺，像是例如研磨或抛光，因为它没有暴露用于机械加工的晶片(或至少将其暴露较少)，并且可以允许材料去除的彻底控制。According to one embodiment, the step of transferring the morphology obtained on the sacrificial layer to the surface of the drift layer may comprise removing the sacrificial layer using an etching process. Etching is superior to other material removal processes like eg grinding or polishing because it does not expose the wafer for machining (or at least exposes it less) and can allow thorough control of material removal.
蚀刻工艺也是有利的，因为它们允许晶片的选择性平面化。晶片可以设置有例如相对较厚的氧化层掩膜，其保护特定区域，如离子注入区域，并且留下所期望被暴露的肖特基区域。通过这样的方式，在平面化期间可以保护注入区域，使得在没有影响注入区域深度的情况下获得局部平面化。这对于SiC器件是特别有利的，因为其可以具有相对较浅的注入深度，从而对过度的材料去除可以是敏感的。Etching processes are also advantageous because they allow selective planarization of the wafer. The wafer may be provided with, for example, a relatively thick oxide mask, which protects certain regions, such as ion implanted regions, and leaves the desired Schottky regions exposed. In this way, the implanted region can be protected during planarization so that a local planarization is obtained without affecting the depth of the implanted region. This is particularly advantageous for SiC devices since they can have relatively shallow implant depths and thus can be sensitive to excessive material removal.
根据一个实施方式，蚀刻工艺可以是等离子蚀刻，如感应耦合等离子体(ICP)蚀刻。According to one embodiment, the etching process may be plasma etching, such as inductively coupled plasma (ICP) etching.
根据进一步的实施方式，蚀刻工艺可以在牺牲层与SiC之间具有0.9到1.1的选择性。选择性表示两种材料之间蚀刻速度的比率。According to further embodiments, the etching process may have a selectivity between the sacrificial layer and SiC of 0.9 to 1.1. Selectivity expresses the ratio of etch rates between two materials.
以几乎相同，像是例如在0.9到1.1范围内的蚀刻速度使用蚀刻工艺来蚀刻SiC和牺牲层是有利的，应为这能够使得牺牲层的表面形态转移至漂移层的表面。在通过蚀刻使牺牲层变薄期间，漂移层的突出表面区域会逐渐暴露于蚀刻工艺，并与所述牺牲层基本相同的速度被蚀刻。从而突出的表面不规则性可以被牺牲层的相应表面形态替代，并且通过持续进一步的蚀刻，空洞不规则性，如坑和孔洞也被替代。假如牺牲层具有比外延生长漂移层的初始表面更加平滑的形态，则这样的工艺改善了漂移层的形态。It is advantageous to use an etching process to etch the SiC and the sacrificial layer with almost the same etch rate, say for example in the range of 0.9 to 1.1, since this enables transfer of the surface morphology of the sacrificial layer to the surface of the drift layer. During thinning of the sacrificial layer by etching, the protruding surface regions of the drift layer are gradually exposed to the etching process and are etched at substantially the same rate as the sacrificial layer. Prominent surface irregularities can thus be replaced by corresponding surface topography of the sacrificial layer, and by continuing further etching hollow irregularities such as pits and holes are also replaced. Such a process improves the morphology of the drift layer provided that the sacrificial layer has a smoother morphology than the initial surface of the epitaxially grown drift layer.
根据一个实施方式，牺牲层可以是二氧化硅层，其适于半导体器件制造工艺中的整合。所述氧化物可以通过沉积旋涂玻璃被施加，这是有利的，因为通过使用类似于用于施加光致抗蚀剂的工艺，可以以各种涂层厚度施加氧化物。According to one embodiment, the sacrificial layer may be a silicon dioxide layer, which is suitable for integration in a semiconductor device manufacturing process. The oxide can be applied by deposition spin-on-glass, which is advantageous because by using a process similar to that used to apply photoresist, the oxide can be applied at various coating thicknesses.
进一步地，旋涂玻璃的液体性质能够使其完全填满具有相对小曲率半径的穴洞和坑。由于电场集中，较小的曲率半径增加了击穿(贯穿，breakthrough)的风险。另一方面，具有小曲率半径的坑更加容易被旋涂玻璃完全填满，这是有利的，因为其增强了平面化期间(经由蚀刻)去除坑的可能性。由于旋涂玻璃的表面张力，使用旋涂玻璃还可以提供相对较平滑的表面。Further, the liquid nature of spin-on-glass enables it to completely fill cavities and pits with relatively small radii of curvature. A smaller radius of curvature increases the risk of breakdown due to electric field concentration. On the other hand, pits with small radii of curvature are more likely to be completely filled by spin-on-glass, which is advantageous because it enhances the probability of pit removal (via etching) during planarization. Using spin-on-glass also provides a relatively smooth surface due to the surface tension of spin-on-glass.
其他的沉积技术包括，例如化学气相沉积(CVD)。Other deposition techniques include, for example, chemical vapor deposition (CVD).
使用氧化物也是有利的，因为它可以由可用于处理半导体器件其他阶段的不同蚀刻工艺蚀刻，并且该工艺具有在氧化物与碳化硅之间的低选择性。Using oxide is also advantageous because it can be etched by a different etch process that can be used to process other stages of a semiconductor device, and the process has a low selectivity between oxide and silicon carbide.
使用电介质牺牲层如氧化物的进一步优势是完成的蚀刻工艺后的残留部分相对较容易被检测。牺牲层的完全去除可以通过，例如扫描电子显微镜(SEM)的检测来验证。A further advantage of using a dielectric sacrificial layer, such as an oxide, is that the remainder of the completed etch process is relatively easy to detect. Complete removal of the sacrificial layer can be verified, for example, by inspection with a scanning electron microscope (SEM).
在牺牲层与碳化硅之间具有低选择性的蚀刻工艺的实例包括，在六氟化硫(SF6)和氩(Ar)气体混合物中的感应耦合等离子体(ICP)蚀刻，电子回旋共振(ECR)等离子体蚀刻，平行板反应离子蚀刻(RIE)以及离子铣削。Examples of etching processes with low selectivity between the sacrificial layer and silicon carbide include, inductively coupled plasma (ICP) etching in a gas mixture of sulfur hexafluoride (SF 6 ) and argon (Ar), electron cyclotron resonance ( ECR) plasma etching, parallel plate reactive ion etching (RIE) and ion milling.
根据一个实施方式，制造功率整流器件的方法可以进一步包括，在将牺牲层的表面形态转移到漂移层的表面之前，牺牲层表面的化学机械抛光(CMP)。本实施方式是有利的，因为在形态转移之前，可以获得具有更少不规则性，像是例如坑和小丘的更加平滑表面的牺牲层。According to one embodiment, the method of manufacturing a power rectifying device may further include, before transferring the surface morphology of the sacrificial layer to the surface of the drift layer, chemical mechanical polishing (CMP) of the surface of the sacrificial layer. This embodiment is advantageous because before the morphology transfer a smoother surface of the sacrificial layer with less irregularities like eg pits and hillocks can be obtained.
根据一个实施方式，制造功率整流器件的方法可以进一步包括，在漂移层上形成肖特基电极之前，对漂移层的表面退火的步骤。本实施方式是有利的，因为晶片的退火(即，加热)可以去除源于等离子体蚀刻牺牲层的离子损坏，由此提供了具有降低形态缺陷数量的改善的漂移层表面，否则，会损害器件的性能。According to one embodiment, the method for manufacturing a power rectifier device may further include, before forming the Schottky electrode on the drift layer, the step of annealing the surface of the drift layer. This embodiment is advantageous because annealing (i.e., heating) of the wafer can remove ionic damage originating from plasma etching of the sacrificial layer, thereby providing an improved drift layer surface with a reduced number of morphological defects that would otherwise damage the device performance.
热处理可以是例如快速热处理(RTP)。The thermal treatment may be, for example, rapid thermal processing (RTP).
根据一个实施方式，制造功率整流器件的方法可以进一步包括在将牺牲层的形态转移到漂移层的表面的步骤后，并且在形成肖特基电极的步骤前，抛光漂移层表面的步骤。本实施方式是有利的，因为抛光可以进一步降低外延层表面的微观粗糙度，以便形成单层阶(monolayer step)的有序结构，其可以改善被沉积的肖特基势垒并减少泄漏电流量。According to one embodiment, the method of manufacturing a power rectifier device may further include a step of polishing the surface of the drift layer after the step of transferring the morphology of the sacrificial layer to the surface of the drift layer and before the step of forming the Schottky electrode. This embodiment is advantageous because polishing can further reduce the micro-roughness of the epitaxial layer surface to form a monolayer step ordered structure, which can improve the deposited Schottky barrier and reduce the amount of leakage current .
抛光可以通过例如CMP实施。Polishing can be performed by, for example, CMP.
根据一个实施方式，制造功率整流器件的方法可以进一步包括，在漂移层上形成肖特基电极之前，对漂移层的表面氧化和氢氟酸(HF)蚀刻(的后续步骤)。氧化可以在例如含有氧的环境中RTP退火期间实施，其中氧可以与某些表面材料(Si原子)反应以形成二氧化硅。然后，可以例如立即在肖特基金属的沉积之前通过HF蚀刻去除氧化物，这是有利的，因为它提供了具有改善平滑度的肖特基势垒结。According to one embodiment, the method of manufacturing a power rectifying device may further include, before forming the Schottky electrode on the drift layer, surface oxidation and hydrofluoric acid (HF) etching (subsequent steps) of the drift layer. Oxidation can be performed, for example, during an RTP anneal in an environment containing oxygen, where the oxygen can react with certain surface materials (Si atoms) to form silicon dioxide. The oxide can then be removed eg by HF etching immediately before the deposition of the Schottky metal, which is advantageous because it provides a Schottky barrier junction with improved smoothness.
根据一个实施方式，制造功率整流器件的方法可以进一步包括，在形成漂移层后，在漂移层中注入掺杂原子的步骤。注入区域可以形成例如JTE区，耗尽阻塞网，以及pn二极管阵列。According to one embodiment, the method for manufacturing a power rectifying device may further include, after forming the drift layer, implanting dopant atoms into the drift layer. Implanted regions can form, for example, JTE regions, depletion blocking nets, and pn diode arrays.
在将牺牲层的形态转移到漂移层的表面之前实施注入是有利的，因为还可以降低注入引起的表面损伤和/或漂移层的退火过程引起的不规则性。Performing the implantation before transferring the morphology of the sacrificial layer to the surface of the drift layer is advantageous, since surface damage caused by the implantation and/or irregularities caused by the annealing process of the drift layer can also be reduced.
根据一个实施方式，制造功率整流器件的方法可以进一步包括，先于(或在其之前)漂移层表面上形成肖特基电极的步骤，在漂移层中注入掺杂原子的步骤。According to one embodiment, the method for manufacturing a power rectifying device may further include, before (or before) the step of forming a Schottky electrode on the surface of the drift layer, the step of implanting dopant atoms into the drift layer.
应当明白，上述对于根据本发明第一方面的功率整流器件的实施方式中的任何特征可以与根据本发明第二方面的方法组合。It should be understood that any of the features in the above embodiments of the power rectifying device according to the first aspect of the present invention may be combined with the method according to the second aspect of the present invention.
当研读下列详细公开、绘图和所附权利要求时，本发明的进一步目标、特征和优势将变得显而易见。本领域的技术人员将意识到，本发明的不同特征可以组合以产生不同于如下所述的实施方式。Further objects, features and advantages of the present invention will become apparent when studying the following detailed disclosure, drawings and appended claims. Those skilled in the art will appreciate that different features of the invention can be combined to create embodiments other than those described below.
附图说明Description of drawings
参考附图，根据本发明优选实施方式的下列说明性和非限制性的详细描述，本发明的上述以及另外的目的、特征和优势将变得更加易于理解，其中：The above and other objects, features and advantages of the present invention will become more readily understood from the following illustrative and non-limiting detailed description of preferred embodiments of the present invention, with reference to the accompanying drawings, wherein:
图1示意性地示出根据本发明实施方式的功率整流器件的横截面；Fig. 1 schematically shows a cross-section of a power rectifying device according to an embodiment of the present invention;
图2示意性地示出根据本发明实施方式的功率整流器件的俯视图；Fig. 2 schematically shows a top view of a power rectifying device according to an embodiment of the present invention;
图3示意性地示出根据本发明另一个实施方式的功率整流器件的俯视图；Fig. 3 schematically shows a top view of a power rectifying device according to another embodiment of the present invention;
图4是根据本发明实施方式的功率整流器件的示意性横截面；4 is a schematic cross-section of a power rectifying device according to an embodiment of the present invention;
图5a-图5d示意性地示出根据本发明实施方式的功率整流器件的平面化过程；5a-5d schematically illustrate the planarization process of a power rectifier device according to an embodiment of the present invention;
图6a-图6b示意性地示出在平面化蚀刻前后漂移层表面的坑的视图；以及Figures 6a-6b schematically illustrate views of pits on the surface of the drift layer before and after planarization etching; and
图7是根据本发明实施方式功率整流器件制造方法的框图。FIG. 7 is a block diagram of a method for manufacturing a power rectifying device according to an embodiment of the present invention.
所有的图都是示意性的，不是必然地按比例方式绘制，通常仅仅示出必要的部件以阐明本发明，而其他部件可以省略或仅是暗示。All figures are schematic and not necessarily drawn to scale, generally only showing components necessary to clarify the invention, while other components may be omitted or merely implied.
具体实施方式Detailed ways
参考图1，其示出根据本发明另一个实施方式的功率整流器件的示意图。Referring to FIG. 1 , it shows a schematic diagram of a power rectifying device according to another embodiment of the present invention.
功率整流器件100包括碳化硅漂移层110，其在例如具有离轴方向为例如2到8度的4H多型基板150上外延生长。包括例如钛的肖特基电极120设置在漂移层110上。将欧姆接触160连接到低电阻基板150的背面。漂移层110具有平面化的表面(即，表面是平面的或平坦的)，使得漂移层110表面的任何坑140的深度近似小于Dmax＝Eb/Fa，其中Eb是金属-半导体势垒高度，以及Fa是雪崩击穿场。The power rectifying device 100 includes a silicon carbide drift layer 110 epitaxially grown on, for example, a 4H polytype substrate 150 with an off-axis direction of, for example, 2 to 8 degrees. A Schottky electrode 120 including, for example, titanium is disposed on the drift layer 110 . Ohmic contacts 160 are connected to the backside of the low resistance substrate 150 . The drift layer 110 has a planarized surface (i.e., the surface is planar or flat) such that the depth of any pit 140 on the surface of the drift layer 110 is approximately less than Dmax = Eb / Fa , where Eb is the metal-semiconductor potential bastion height, and F a is the avalanche breakdown field.
漂移层110表面的坑140在金属沉积时可以引起扩散于半导体中的金属针的形成。小半径的金属尖端会导致电场的高局部集中，其通常随着金属凹痕曲率半径的减少而增加。电子从肖特基金属120隧穿到半导体中的高可能性会限制电流从金属流到半导体的热势垒，从而降低有效的势垒能量。然而，只要由于金属凹痕的势垒高度的最大减少不超过金属-半导体势垒高度Eb，就可以保持金属与半导体之间的能量势垒。半导体中的最大平均电场由雪崩击穿场Fa限制。因此，任何不比Dmax＝Eb/Fa深的金属凹痕不会将势垒高度减少到零。The pits 140 on the surface of the drift layer 110 may cause the formation of metal needles diffused in the semiconductor during metal deposition. A small radius metal tip results in a high local concentration of the electric field, which generally increases with decreasing radius of curvature of the metal dent. The high probability of tunneling of electrons from the Schottky metal 120 into the semiconductor limits the thermal barrier for current flow from the metal to the semiconductor, thereby reducing the effective barrier energy. However, the energy barrier between metal and semiconductor can be maintained as long as the maximum reduction in barrier height due to metal indentation does not exceed the metal-semiconductor barrier height Eb . The maximum average electric field in a semiconductor is limited by the avalanche breakdown field F a . Therefore, any metal dimple not deeper than D max =E b /F a will not reduce the barrier height to zero.
金属-半导体势垒高度Eb和雪崩击穿场Fa的值可以分别是，例如1eV和2MV/cm。因此，根据一个实施方式，不深于约5nm的任何坑可以确保坑对功率整流器件100的击穿性能的可以忽略的(或至少显著降低)的影响。The values of the metal-semiconductor barrier height E b and the avalanche breakdown field F a may be, for example, 1 eV and 2 MV/cm, respectively. Therefore, according to one embodiment, any pit not deeper than about 5 nm may ensure a negligible (or at least significantly reduced) effect of the pit on the breakdown performance of the power rectifying device 100 .
根据本实施方式，具有小于5nm深度以及大于约2μm的横向尺寸(或宽度)的浅凹痕，由于它们相对较大的曲率半径，会保持在表面上。至于图1，应当指出，漂移层表面上剩下的坑140的深度不是按照数量级按比例绘制的。可以提供给漂移层约0.7到1.1μm的厚度每100V所期望的电压。有利地，漂移层110的掺杂可以足够低，以便以额定的阻塞电压提供低于4H SiC雪崩击穿临界场的最大电场。According to the present embodiment, shallow indentations having a depth of less than 5 nm and a lateral dimension (or width) greater than about 2 μm will remain on the surface due to their relatively large radius of curvature. With regard to Figure 1, it should be noted that the depths of the remaining pits 140 on the surface of the drift layer are not drawn to scale in terms of magnitude. A desired voltage of about 0.7 to 1.1 μm per 100 V of thickness can be supplied to the drift layer. Advantageously, the doping of the drift layer 110 can be low enough to provide a maximum electric field below the critical field of 4H SiC avalanche breakdown at a rated blocking voltage.
有利地，可以保护高功率整流器的器件的外围避免电场聚集作用。如图2所示，功率整流器件200的外围可以配置有离子注入p-型耗尽阻塞区212，以及可以抑制在功率整流器件200外围的电场尖峰的结终端(JT)区211。区211、212两者可以形成为围绕功率整流器件200的连续带。Advantageously, the periphery of the device of the high power rectifier can be protected from electric field concentration effects. As shown in FIG. 2 , the periphery of the power rectifier 200 can be configured with an ion-implanted p-type depletion blocking region 212 and a junction termination (JT) region 211 that can suppress electric field spikes at the periphery of the power rectifier 200 . Both regions 211 , 212 may be formed as a continuous strip surrounding the power rectifying device 200 .
p-型欧姆接触区213可以提供给耗尽阻塞区212，其有利地使肖特基金属120的电位和JT区211的内围的电位几乎相等。连续肖特基金属的外围221(在图2中仅仅示出轮廓221)可以完全重叠于漂移层210的表面，并且可以进一步位于欧姆接触区213内。The p-type ohmic contact region 213 may be provided to the depletion blocking region 212 , which advantageously makes the potential of the Schottky metal 120 and the inner periphery of the JT region 211 nearly equal. The periphery 221 of the continuous Schottky metal (only the outline 221 is shown in FIG. 2 ) may completely overlap the surface of the drift layer 210 and may be further within the ohmic contact region 213 .
通过例如将约1013cm-2的量注入受体，可以形成JT区211，以便形成结终端扩展(junction termination extension)(JTE)。应当明白，可以应用不同于使用JTE的技术的其他结终端技术。作为实例，浮动保护环(floating guard rings)阵列可以被用作结终端的手段。The JT region 211 can be formed by, for example, injecting an amount of about 10 13 cm −2 into the acceptor so as to form a junction termination extension (JTE). It should be appreciated that other junction termination techniques than those using JTE may be applied. As an example, an array of floating guard rings may be used as a means of junction termination.
参考图3，功率整流器件可以配置有在肖特基金属120下面的离子注入p-型耗尽阻塞314的紧密间隔的阵列。该紧密间隔的阵列可以给肖特基势垒提供静电屏蔽。在根据该实施方式的器件的金属-半导体界面处的电场可以有利地低于在非屏蔽功率整流器件中的电场。SiC肖特基二极管中的反向电流受隧穿控制，因此，减少在肖特基界面的电场会是有利的。邻近的耗尽阻塞314之间的紧密间距可以使静电屏蔽可行。Referring to FIG. 3 , a power rectifying device can be configured with a closely spaced array of ion-implanted p-type depletion stoppers 314 beneath the Schottky metal 120 . This closely spaced array can provide electrostatic shielding to the Schottky barriers. The electric field at the metal-semiconductor interface of a device according to this embodiment may advantageously be lower than in an unshielded power rectifying device. The reverse current in SiC Schottky diodes is controlled by tunneling, therefore, it would be beneficial to reduce the electric field at the Schottky interface. The close spacing between adjacent depletion stoppers 314 can make electrostatic shielding feasible.
有利地，所述紧密间隔的邻近的耗尽阻塞之间的最大间距不会超过p-掺杂穿透深度的约6倍，这可以提供非常高的屏蔽。取决于在SiC中的穿透深度，这种关系可以例如与约1到5微米的邻近p-型耗尽阻塞314之间间距的范围相应。Advantageously, the maximum spacing between closely spaced adjacent depletion stoppers does not exceed about 6 times the p-doping penetration depth, which can provide very high shielding. Depending on the penetration depth in SiC, this relationship may correspond, for example, to a range of spacing between adjacent p-type depletion stoppers 314 of about 1 to 5 microns.
在被屏蔽功率整流器件设计300中的漂移层110的顶部可以具有类似于在垂直场效应晶体管中通道(channel)的功能。通道的总体区域可以显著小于肖特基金属的总体区域，因为总体区域的一部分会被耗尽阻塞314占用。有用的功率整流器件横截面积的另外部分可以被邻近于耗尽阻塞314的区域占用，这是由于所述邻近的区域被pn结的固有电位耗尽。有利地，与漂移层110的主体的掺杂水平相比，漂移层110的近表面部分可以具有增加的系数为1.5到8的掺杂水平。所述近表面通道部分的厚度可以近似等于(接近)p-型耗尽阻塞314的注入深度。The top of the drift layer 110 in the shielded power rectifier device design 300 may function similarly to a channel in a vertical field effect transistor. The overall area of the channel can be significantly smaller than that of the Schottky metal since a portion of the overall area will be taken up by the depletion block 314 . Another portion of the useful power rectifying device cross-sectional area may be taken up by the region adjacent to the depletion stopper 314 due to the fact that the adjacent region is depleted by the intrinsic potential of the pn junction. Advantageously, the near-surface portion of the drift layer 110 may have an increased doping level by a factor of 1.5 to 8 compared to the doping level of the main body of the drift layer 110 . The thickness of the near-surface channel portion may be approximately equal to (close to) the implantation depth of the p-type depletion stopper 314 .
有利地，离子注入p-型耗尽阻塞314的宽度不会超过它们之间的间距，这是因为被耗尽阻塞314占用的器件区域不可用于电子从阳极到阴极的垂直转移。Advantageously, the width of the ion-implanted p-type depletion stoppers 314 does not exceed the spacing between them, since the device area occupied by the depletion stoppers 314 is not available for vertical transfer of electrons from the anode to the cathode.
功率整流器件300可以进一步配置有在基板150背面的欧姆接触160。外延层叠层可以进一步包括缓冲层170，其可以抑制基板晶体缺陷对漂移层110晶体质量的影响。The power rectifying device 300 may be further configured with an ohmic contact 160 on the backside of the substrate 150 . The epitaxial layer stack may further include a buffer layer 170 , which can suppress the influence of substrate crystal defects on the crystal quality of the drift layer 110 .
根据一个实施方式，功率整流器件可以进一步配置有分布在漂移层110区域上的许多相对较大的浪涌电流pn二极管(浪涌二极管)315。浪涌二极管315可以采用与外部p-型区域312相同的p-注入类型和欧姆接触区313。所有浪涌二极管315可以被肖特基势垒金属完全覆盖。According to one embodiment, the power rectifying device may be further configured with a number of relatively large surge current pn diodes (surge diodes) 315 distributed on the drift layer 110 region. Surge diode 315 may employ the same p-implantation type and ohmic contact region 313 as outer p-type region 312 . All surge diodes 315 may be completely covered by Schottky barrier metal.
器件300可以进一步配置有用于电流浪涌状态的安全特征。沿器件200和300边缘的pn二极管部分可以提供这样的安全特征，这是因为，由于少数载流子注入，在高电流密度下，pn结会保留相对较低的正向电压降。然而，边缘的总体区域可以相对较小，这可以能够使得器件200保持相对较低的电流浪涌。浪涌二极管315阵列可以将浪涌电流分布在更大的范围上，因此，可以提供具有更高浪涌电流稳定性的器件300。有利地，浪涌二极管315的最小横向尺寸可以超过漂移层110厚度的两(2)倍。较小区域的浪涌二极管可以被邻近的肖特基势垒区域缩短，这在碳化硅中可以具有比pn二极管更小的接通电压。Device 300 may be further configured with safety features for current surge conditions. The pn diode portions along the edges of devices 200 and 300 can provide such a safety feature because, at high current densities, the pn junction retains a relatively low forward voltage drop due to minority carrier injection. However, the overall area of the edge may be relatively small, which may enable device 200 to maintain a relatively low current surge. The array of surge diodes 315 can distribute the surge current over a larger area, thus, can provide the device 300 with higher surge current stability. Advantageously, the minimum lateral dimension of surge diode 315 may exceed two (2) times the thickness of drift layer 110 . Smaller area surge diodes can be shortened by the adjacent Schottky barrier area, which in silicon carbide can have a smaller turn-on voltage than pn diodes.
根据特定应用要求，可以选择被浪涌二极管315利用的肖特基势垒二极管区域的小部分。过于密集的浪涌二极管阵列会占用高比例的漂移层区域，而过于宽松的阵列会具有较低的可接受浪涌电流值。Depending on specific application requirements, the fraction of the Schottky barrier diode area utilized by surge diode 315 can be selected. An array of surge diodes that is too dense will occupy a high percentage of the drift layer area, while an array that is too loose will have a lower acceptable surge current value.
浪涌二极管阵列不限于圆形二极管阵列。可以应用不同的浪涌二极管结构，像是例如具有超出漂移层厚度两(2)倍的带(条纹，stripe)宽度的pn二极管带线性阵列。Surge diode arrays are not limited to circular diode arrays. Different surge diode structures can be applied, like for example a linear array of pn diode strips with a stripe width exceeding two (2) times the thickness of the drift layer.
如在图3中示出的，功率整流器件可以包括紧密间隔的耗尽阻塞314或分布在肖特基二极管区域上的浪涌二极管315阵列，或两者的组合。该器件还可以配置有沿整个外围的JTE区。As shown in FIG. 3, the power rectification device may comprise an array of closely spaced depletion stoppers 314 or surge diodes 315 distributed over the Schottky diode area, or a combination of both. The device can also be configured with a JTE region along the entire periphery.
图4示出功率整流器件的横截面，该功率整流器件具有在基板450上提供的背面欧姆接触460，以及在基板450与漂移层410之间提供的缓冲层470。最小尺寸超出漂移层410厚度约两(2)倍的专用浪涌二极管415阵列可以提供在漂移层410的近表面部分416中，以便提供对浪涌电流状态的改善保护。每个浪涌二极管415可以设置有欧姆接触。FIG. 4 shows a cross-section of a power rectifying device having a backside ohmic contact 460 provided on a substrate 450 and a buffer layer 470 provided between the substrate 450 and the drift layer 410 . An array of dedicated surge diodes 415 with minimum dimensions exceeding the drift layer 410 thickness by approximately two (2) times may be provided in the near-surface portion 416 of the drift layer 410 to provide improved protection against surge current conditions. Each surge diode 415 may be provided with an ohmic contact.
图5a至图5d示意性地示出根据本发明制造功率整流器件的方法的示例性实施方式。Figures 5a to 5d schematically illustrate an exemplary embodiment of a method of manufacturing a power rectifying device according to the present invention.
在图5a中，提供包括SiC的漂移层510。漂移层可以在SiC基板150上外延生长。在其上提供有肖特基电极120的漂移层510的顶部表面包括不规则性，像是例如在漂移层510的外延生长期间以及在基板150的后续处理期间形成的坑540和台阶542。由于电场的局部集中，不规则性会增加由电子隧穿引起的泄漏电流的风险。In Fig. 5a, a drift layer 510 comprising SiC is provided. The drift layer may be epitaxially grown on the SiC substrate 150 . The top surface of the drift layer 510 on which the Schottky electrode 120 is provided includes irregularities such as pits 540 and steps 542 formed, for example, during epitaxial growth of the drift layer 510 and during subsequent processing of the substrate 150 . Irregularities increase the risk of leakage currents caused by electron tunneling due to local concentrations of the electric field.
如图5b所示，牺牲层522，像是例如SiO2可以通过在漂移层510表面上沉积旋涂玻璃而提供。旋涂玻璃是一种玻璃类型，可以作为液体施加并且固化以在表面上形成氧化物层。由于液体特性，所述旋涂玻璃可以填充漂移层510的洞穴，并提供平滑化的表面。可以获得具有约50nm厚涂层的旋涂玻璃层。然而，可以使用更薄和更厚的两种涂层来形成牺牲层522。As shown in FIG. 5 b , a sacrificial layer 522 such as eg SiO 2 may be provided by depositing spin-on-glass on the surface of the drift layer 510 . Spin-on-glass is a type of glass that can be applied as a liquid and cured to form an oxide layer on the surface. Due to the liquid nature, the spin-on-glass can fill the cavities of the drift layer 510 and provide a smoothed surface. Spin-on-glass layers with approximately 50 nm thick coatings can be obtained. However, both thinner and thicker coatings may be used to form the sacrificial layer 522 .
利用类似于常规光致抗蚀剂的应用的技术，即在固化步骤后的旋转和烘烤，旋涂玻璃可以被应用。Spin-on-glass can be applied using techniques similar to the application of conventional photoresists, ie spin and bake after the curing step.
牺牲层522的形成可以在低选择性等离子体蚀刻之后，像是例如在SF6和氩气体混合物中的感应耦合等离子体(ICP)蚀刻后。因此，可以以几乎相同的蚀刻速度蚀刻SiC和SiO2，这使得在牺牲层522上获得的形态能够转移到漂移层510的表面。The formation of the sacrificial layer 522 may follow a low-selectivity plasma etch, such as, for example, an inductively coupled plasma (ICP) etch in a SF 6 and argon gas mixture. Therefore, SiC and SiO 2 can be etched at almost the same etching rate, which enables the morphology obtained on the sacrificial layer 522 to be transferred to the surface of the drift layer 510 .
如图5c所示，在蚀刻工艺进程过程中，漂移层表面的任何突出部分最终会暴露于等离子体并被其蚀刻。As shown in Figure 5c, during the course of the etching process, any protruding portions of the surface of the drift layer will eventually be exposed to and etched by the plasma.
图5d示出平面化表面，其中蚀刻工艺持续直到牺牲层522已经从最深的凹痕中被去除。除坑540较低部分之外的所有不规则被去除。因此，表面比启动平面化之前更平滑，尤其是比生长时更平滑。该制造方法是有利的，因为其可以仅保留不深于约5nm坑540(在图5d中由d1指示)，这对所得的功率整流器件100的击穿性能具有降低作用。牺牲层522的表面形态已经被转移到漂移层510的表面。Figure 5d shows a planarized surface where the etch process continues until the sacrificial layer 522 has been removed from the deepest recesses. All irregularities except the lower portion of pit 540 are removed. As a result, the surface is smoother than before planarization was initiated, and especially smoother than growth. This method of fabrication is advantageous because it can only leave a pit 540 no deeper than about 5 nm (indicated by d 1 in FIG. 5d ), which has a degrading effect on the breakdown performance of the resulting power rectifying device 100 . The surface morphology of the sacrificial layer 522 has been transferred to the surface of the drift layer 510 .
还可以重复上述平面化，以便进一步增强表面的平滑度，如果使用的蚀刻工艺具有在牺牲层522与SiC之间的更高选择性，像是例如0.7，那么这是特别有利的。The planarization described above can also be repeated in order to further enhance the smoothness of the surface, which is particularly advantageous if the etching process used has a higher selectivity between the sacrificial layer 522 and SiC, like eg 0.7.
图6a和图6b示出具有40nm深坑640的漂移层610的表面。使用具有氧化物-SiC选择性为0.9的等离子体蚀刻的单个平面化循环会将坑640的深度d0减少到约4nm(图6b)，这足以消除不期望的电场集中效应。通过重复步骤，即，在漂移层610顶部添加并蚀刻第二牺牲层622，可以进一步降低坑深度d1。可选地，如果需要，平面化循环的数量可以进一步增加。例如，如果平面化蚀刻的选择性(显著)偏离1，这会是有利的。6a and 6b show the surface of the drift layer 610 with deep pits 640 of 40 nm. A single planarization cycle using a plasma etch with an oxide-SiC selectivity of 0.9 reduces the depth do of the pit 640 to about 4 nm (Fig. 6b), which is sufficient to eliminate the unwanted electric field concentration effect. By repeating the steps of adding and etching a second sacrificial layer 622 on top of the drift layer 610 , the pit depth d 1 can be further reduced. Optionally, the number of planarization cycles can be further increased if desired. For example, it can be advantageous if the selectivity of the planarization etch deviates (significantly) from unity.
在将牺牲层622的形态转移到漂移层610表面的平面化蚀刻后，可以利用扫描电子显微镜(SEM)来验证已经去除所有氧化物622。After the planarizing etch that transfers the morphology of the sacrificial layer 622 to the surface of the drift layer 610, scanning electron microscopy (SEM) can be used to verify that all of the oxide 622 has been removed.
可以利用像是例如原子力显微镜(AFM)或隧道显微镜的表征技术，来监测剩下的坑640的实际深度。The actual depth of the remaining pits 640 can be monitored using characterization techniques like, for example, atomic force microscopy (AFM) or tunneling microscopy.
图7示意性地示出根据本发明实施方式制造功率整流器件的方法的框图。Fig. 7 schematically shows a block diagram of a method of manufacturing a power rectifying device according to an embodiment of the present invention.
如上所述，在包括基板的晶片上形成7001漂移层。该形成7001之后可以跟随注入步骤7010，其中，可以将例如铝离子注入以在漂移层中形成p型区。As described above, a drift layer is formed 7001 on a wafer including a substrate. This formation 7001 may be followed by an implantation step 7010 in which eg aluminum ions may be implanted to form a p-type region in the drift layer.
接着，在漂移层上形成7002牺牲层，并且该牺牲层可以在抛光步骤7020过程中被CMP抛光，以便进一步改善表面形态，使得能够形成具有降低不规则的更加平滑的表面。Next, a sacrificial layer is formed 7002 on the drift layer, and the sacrificial layer may be CMP polished during a polishing step 7020 to further improve the surface morphology, enabling a smoother surface with reduced irregularities.
蚀刻步骤7003，或牺牲层的形态转移到漂移层之后，可以跟随利用SEM的检查步骤7030。可以添加该检查步骤7030，以便验证牺牲层的去除。After the etching step 7003, or the transfer of the morphology of the sacrificial layer to the drift layer, an inspection step 7030 using a SEM may follow. This check step 7030 can be added to verify removal of the sacrificial layer.
为了进一步降低可以由蚀刻工艺引起的表面不规则和损伤，退化步骤7004可以跟随在蚀刻工艺后。在包含氧的环境中，可以将晶片加热到900℃至1300℃之间的温度，使得表面被氧化。如果表面是SiC的硅晶面，氧化物可以是例如1-2nm，而对于SiC的碳化面，其可以是几十纳米或更厚。然后，可以通过HF蚀刻7005去除氧化物。To further reduce surface irregularities and damage that may be caused by the etching process, a degradation step 7004 may follow the etching process. The wafer may be heated to a temperature between 900°C and 1300°C in an oxygen containing environment such that the surface is oxidized. If the surface is the silicon facet of SiC, the oxide can be eg 1-2 nm, while for the carbide facet of SiC it can be tens of nanometers or thicker. The oxide can then be removed by HF etching 7005 .
金属沉积7006之前，可以进行铝的离子注入7040，其中，在漂移层中形成p型耗尽阻塞网和/或pn二极管阵列。表面还可以被抛光7050，以降低任何残余缺陷，其中，例如去除10-20nm的表面。Prior to metal deposition 7006, aluminum ion implantation 7040 may be performed, wherein p-type depletion blocking nets and/or pn diode arrays are formed in the drift layer. The surface may also be polished 7050 to reduce any residual defects, wherein, for example, 10-20nm of the surface is removed.
在一个实施例中，pn二极管的制造包括以下步骤：在具有被蚀刻沟槽的p-基板上生长n-型SiC层，牺牲氧化物的沉积，氧化物的CMP以及平面化蚀刻。可以将通过CMP过程中在沟槽中心的氧化物的碟形蚀化(dishing)而获得的更加平滑的图案转移到SiC中。In one embodiment, the fabrication of a pn diode includes the steps of growing an n-type SiC layer on a p-substrate with etched trenches, deposition of a sacrificial oxide, CMP of the oxide, and planarization etch. The smoother pattern obtained by dishing of the oxide in the center of the trench during CMP can be transferred into SiC.
在一个实施例中，可以沉积具有100-200nm厚度的CVD氧化物并形成图案，以便掩蔽(mask)注入的p-型层。然后，可以沉积具有60nm厚度的旋涂玻璃并在250℃下烘烤，之后通过平面化蚀刻去除在器件中心部分的旋涂玻璃。然后，可以对离子损伤退火，并通过清洗晶片背面的氧化物，沉积镍以及在960℃将其烧结而提供背面欧姆接触。In one embodiment, a CVD oxide having a thickness of 100-200 nm may be deposited and patterned to mask the implanted p-type layer. Then, spin-on-glass with a thickness of 60 nm may be deposited and baked at 250° C., after which the spin-on-glass at the center portion of the device is removed by planarizing etching. The ion damage can then be annealed and the backside ohmic contact provided by cleaning the oxide on the backside of the wafer, depositing nickel and sintering it at 960°C.
然后可以在HF中剥离(strip)残余氧化物，随后进行注入的退火。可选地，根据如上描述的实施方式通过CMP进一步改善表面，其中，制造功率整流器件的方法进一步包括，在将牺牲层的形态转移到漂移层的表面的步骤7003后，对漂移层的表面抛光。The residual oxide can then be stripped in HF, followed by an anneal of the implant. Optionally, according to the embodiment described above, the surface is further improved by CMP, wherein the method for manufacturing a power rectifying device further includes, after the step 7003 of transferring the morphology of the sacrificial layer to the surface of the drift layer, polishing the surface of the drift layer .
然后可以沉积钛肖特基金属，随后将铝接合垫(bonding pad)金属施加到正面(器件面)，并将金焊料金属施加到背面。Titanium Schottky metal can then be deposited, followed by aluminum bonding pad metal applied to the front side (device side) and gold solder metal applied to the back side.
根据本发明实施方式注入SiC表面的平面化是有利的，这是因为其能够去除SiC的较少厚度。因此，可以实现材料去除的彻底控制，以便不过多地影响注入的p-阱(p-well)深度。Planarization of implanted SiC surfaces according to embodiments of the present invention is advantageous because it enables removal of less thickness of SiC. Thus, thorough control of material removal can be achieved so as not to affect the implanted p-well depth too much.
平面化可以在两个阶段实施，其中第一阶段去除在外延晶片生长时的生长坑，第二平面化阶段可以在受体注入的退火后施加，以便去除由于活化退火可能会出现的表面缺陷。根据该实施方式的器件的屏蔽设计可以偏好对SiC具有较低势垒的金属，如钨(W)或钼(Mo)的使用。与由钛在400-450℃退火而提供的1200mV势垒高度相比，这样的金属会产生约800mV的势垒高度。W或Mo较低的势垒高度会致使较低的正向电压降。通过静电屏蔽与局部平面化表面的结合，可以实现较低的电流泄漏。Planarization can be performed in two stages, where the first stage removes growth pits during epitaxial wafer growth, and the second planarization stage can be applied after the anneal of the acceptor implant in order to remove surface defects that may arise due to the activation anneal. Shielding designs for devices according to this embodiment may favor the use of metals that have a lower barrier to SiC, such as tungsten (W) or molybdenum (Mo). Such a metal would yield a barrier height of about 800 mV compared to the 1200 mV barrier height provided by titanium annealed at 400-450°C. A lower barrier height for W or Mo results in a lower forward voltage drop. Lower current leakage can be achieved through the combination of electrostatic shielding and locally planarized surfaces.
在一个实施例中，方向平行于功率整流器件1的pn二极管阵列可以覆盖约10％至30％的肖特基势垒区域。In one embodiment, the pn diode array whose direction is parallel to the power rectifying device 1 can cover about 10% to 30% of the Schottky barrier area.
可以实施用大于1×1014cm-2剂量的高剂量注入7010，以限定pn二极管和沿肖特基势垒区域外围的pn二极管边缘。可以实施另一个注入，以限定在整流器外围的JTE区311。JTE 311的宽度可以是约20-60μm，或在最大阻塞电压时是耗尽区的宽度的至少两倍。金属接触可以覆盖至少几微米的JTE 311。JTE 311可以包括约1.1×1013cm-2电活性受体的掺杂剂量的p型层。该掺杂剂可以是例如铝，利用300keV的注入能量和1.65×1013cm-2的注入剂量，将掺杂剂离子注入。在碳覆盖层下，可以在1650℃下实施注入退火30分钟，其中碳覆盖层可以通过硬烘烤的光致抗蚀剂在例如800℃的热处理形成。在注入后，可以在氧等离子体中去除碳覆盖层(carbon cap)。在剥离碳层后，结合例如图5和图7，可以实施如上所述的局部平面化。可以添加可选的CMP平面化步骤7040，以进一步改善表面形态。A high dose implant 7010 with a dose greater than 1×10 14 cm −2 may be performed to define a pn diode and a pn diode edge along the periphery of the Schottky barrier region. Another implant may be performed to define a JTE region 311 at the periphery of the rectifier. The width of JTE 311 may be about 20-60 μm, or at least twice the width of the depletion region at maximum blocking voltage. Metal contacts may cover JTE 311 by at least a few microns. JTE 311 may include a p-type layer at a doping dose of about 1.1×10 13 cm −2 electroactive acceptors. The dopant may be, for example, aluminum, and the dopant ions are implanted with an implantation energy of 300keV and an implantation dose of 1.65×10 13 cm −2 . Implantation annealing may be performed at 1650°C for 30 minutes under the carbon capping layer, where the carbon capping layer may be formed by heat treatment of the hard baked photoresist at eg 800°C. After implantation, the carbon cap can be removed in an oxygen plasma. After peeling off the carbon layer, local planarization as described above may be performed with reference to FIGS. 5 and 7, for example. An optional CMP planarization step 7040 can be added to further improve the surface morphology.
pn二极管区可以用约200nm厚的氧化物掩蔽，以便避免不期望的p型材料的去除。这种更厚的氧化物掩膜可以朝向每个p-型区的中心部分偏移约2-3μm，以避免不期望的n-型区的掩蔽。The pn diode region can be masked with an oxide about 200nm thick in order to avoid undesired removal of p-type material. This thicker oxide mask can be offset by about 2-3 μm towards the central portion of each p-type region to avoid undesired masking of the n-type region.
通过之前所述的烧结镍可以形成背面欧姆接触160。可以在提供欧姆接触的区域中在晶片顶面(器件面)的氧化物中打开阱。然后，可以沉积铝/钛金属叠层并形成图案，以便限定欧姆接触。可以在约950℃烧结铝/钛叠层以形成欧姆接触。由于与SiC是晶格匹配的金属间化合物Ti3SiC2的形成，提供铝/钛接触的欧姆行为(Ohmic behavior)的化合物是已知的。在这个阶段，牺牲的氧化物522在缓冲的HF中可以从顶部表面被全部去除，此后，将基板被转移到沉积室中，在其中可以沉积钛肖特基金属120。然后，通过在顶部沉积铝垫金属并将其图案化，完成器件制造。可以将银焊料金属施加到晶片背面。器件还可以由聚酰亚胺保护。The back ohmic contact 160 may be formed by sintering nickel as described earlier. Wells can be opened in the oxide on the top surface of the wafer (device side) in the areas that provide ohmic contacts. An aluminum/titanium metal stack can then be deposited and patterned to define ohmic contacts. The aluminum/titanium stack can be sintered at about 950°C to form ohmic contacts. Compounds that provide Ohmic behavior of aluminum/titanium contacts are known due to the formation of the intermetallic compound Ti3SiC2 which is lattice matched to SiC. At this stage, the sacrificial oxide 522 can be completely removed from the top surface in buffered HF, after which the substrate is transferred to a deposition chamber where a titanium Schottky metal 120 can be deposited. Device fabrication is then completed by depositing and patterning an aluminum pad metal on top. Silver solder metal can be applied to the backside of the wafer. Devices can also be protected by polyimide.
在另一个实施例中，在外延生长后不久，用于肖特基-势垒功率整流器制造的半导体模板可以配置有局部平面化的表面。如上述实施方式所述，局部平面化可以去除深度大于约5nm的坑。这样的过程是有利的，因为可以获得具有降低形态缺陷数量的起始原料，以用于肖特基-势垒功率整流器的制造。根据该实施方式的外延晶片是有利的，因为它们可以简化肖特基-势垒功率整流器的制造。碳化硅晶片在其晶片边缘周围常常是有缺陷的，因此，可以应用适当的边缘切除。在许多情况下，基板区，典型地离晶片边缘几毫米，不会满足晶体或表面质量的要求。由于碳化硅晶片可以包含适当数量的粗糙缺陷，这会引起包含粗糙缺陷的任何功率器件不可避免的失效，所以本发明的实施方式是有利的。完全平面化(或平坦化)所述粗糙缺陷不是获得本实施方式的好处的要求。In another embodiment, a semiconductor template for Schottky-barrier power rectifier fabrication may be configured with a locally planarized surface shortly after epitaxial growth. As described in the above embodiments, local planarization can remove pits with a depth greater than about 5 nm. Such a process is advantageous because a starting material with a reduced number of morphological defects can be obtained for the fabrication of Schottky-barrier power rectifiers. Epitaxial wafers according to this embodiment are advantageous because they simplify the manufacture of Schottky-barrier power rectifiers. Silicon carbide wafers are often defective around their wafer edges, therefore, appropriate edge cuts can be applied. In many cases, the substrate area, typically a few millimeters from the edge of the wafer, will not meet crystallographic or surface quality requirements. Embodiments of the present invention are advantageous because silicon carbide wafers may contain a reasonable number of roughness defects, which would cause inevitable failure of any power device containing roughness defects. Complete planarization (or flattening) of the roughness defect is not a requirement to obtain the benefits of this embodiment.
一般来说，本发明的实施方式会产生配置有低掺杂(即3×1014到6×1016cm-3)外延层的半导体晶片，该外延层具有约4至100微米之间的厚度，并且施主掺杂水平与在约300V与15kV之间的理论击穿电压相应。由于这些层受坑和其他缺陷的影响更小，产生的击穿电压与应用已知的在4H SiC中碰撞电离率利用结构-特定掺杂曲线(structure-specificdoping profile)计算的击穿电压相对应。In general, embodiments of the present invention result in semiconductor wafers configured with low doping (ie, 3×10 14 to 6×10 16 cm −3 ) epitaxial layers having a thickness between about 4 and 100 microns , and the donor doping level corresponds to a theoretical breakdown voltage between about 300V and 15kV. Since these layers are less affected by pits and other defects, the resulting breakdown voltages correspond to those calculated using the structure-specific doping profile applying known impact ionization rates in 4H SiC .
虽然已经描述了具体的实施方式，本领域的技术人员应当理解，在所附权利要求限定的范围内，可以设想各种修改和变化。Although particular embodiments have been described, it will be appreciated by those skilled in the art that various modifications and changes are conceivable within the scope defined in the appended claims.
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