CN112071898B - Rapid ionization device and preparation method thereof - Google Patents

Abstract

The invention belongs to the field of pulsed power semiconductor devices, and more particularly, relates to a fast ionization device and a preparation method thereof. The fast ionization device includes a metallized cathode, a highly doped n+ region, a highly doped p+ short-circuit point on the cathode side, a p base region, an n-base region, an n-type ionization promoting layer, and a highly doped anode side, which are arranged adjacently in sequence. Miscellaneous n+ short-circuit point, highly doped p+ region, metallized anode. By introducing an n-type ionization promoting layer with a higher doping concentration than the n-base region in the FID device structure, the invention limits the expansion of the space charge region of the n-base region, thereby limiting the region that the collision ionization front needs to pass through. The width of the collision ionization front is reduced, and the propagation time of the collision ionization front is reduced, thereby improving the turn-on speed of the device.

Description

A kind of fast ionization device and preparation method thereof

technical field

The invention belongs to the field of pulsed power semiconductor devices, and more particularly, relates to a fast ionization device (FastIonization Dynistor, FID) and a preparation method thereof.

Background technique

The delayed avalanche breakdown phenomenon is a new physical phenomenon in semiconductor devices discovered by the Russian Ioffe Research Institute, which reveals that when a reverse voltage increased by 10 ¹² V/s is applied across the silicon device, a Ultrafast impact ionization front, when the impact ionization front passes through the space charge region of the device, the device turns on rapidly. Devices designed based on the delayed avalanche breakdown phenomenon can turn on time beyond the limit of the saturation drift velocity of free carriers, thereby shortening the on-time of the device to the sub-nanosecond range.

The fast ionization device FID is a new type of device based on the delayed avalanche breakdown phenomenon. It can be quickly turned on in hundreds of picoseconds and can be used to generate pulses with high voltage levels and short rise times, which are very suitable for pulsed power systems. middle. The structure of the existing FID device is shown in Figure 1. The device mainly includes a four-layer structure, which are n+ layer, p layer, n layer and p+ layer in order from top to bottom. In addition, both the n+ layer and the p+ layer include short-circuit point structures.

A FID device is a two-terminal device, that is, the device has only a cathode and an anode. As shown in the working circuit of the FID device as shown in Figure 2, when the FID device is working, the DC power supply DC first charges the capacitor C. At this time, the FID device is in a forward blocking state, and the connection between the anode (node 2) and the cathode (node 1) is It is subjected to a forward voltage intermittently, and then, when it needs to be triggered and turned on, the trigger source pulse generates a trigger pulse, and a trigger pulse with a voltage rise rate greater than 1kV/ns is applied to the anode of the FID device. When the voltage across the device rises to greater than the blocking voltage When the electric field strength on the J ₂ junction exceeds the critical breakdown field strength, violent collision ionization occurs on the J ₂ junction, and then the ionized region propagates to the two electrodes of the device, so that the device can rapidly operate within hundreds of picoseconds. On, the capacitor C discharges through the FID device, thereby pulsing a high voltage across the load _RL .

Generally, in order to achieve higher blocking voltage of FID devices, single crystal materials with higher resistivity are used in device design and fabrication, and the device has a wider n-base region (ie, n-layer) at the same time. Before turn-on, however, almost the entire n-base region becomes depleted. Therefore, during the turn-on process, the impact ionization front inside the device needs to pass through the entire n-base region, and a certain concentration of plasma is generated in the n-base region, and then the device enters the conduction state. Due to the limited concentration of electron-hole plasma generated in the region traversed by the impact ionization front, the n-base region still has a high resistivity after being turned on, resulting in a high residual voltage across the device. The device design with high resistivity and long base width leads to high residual voltage at both ends of the device after the FID device is turned on, and the on-state loss of the device is large, which is not conducive to the long-term stable operation of the device.

SUMMARY OF THE INVENTION

Aiming at the defects or improvement requirements of the prior art, the present invention provides a fast ionization device and a preparation method thereof. By adding an n-type booster between the n-base region and the highly doped p+ region on the anode side in the structure of the FID device The ionization layer shortens the propagation range of the impact ionization front and accelerates the turn-on speed of the device; at the same time, it also reduces the residual voltage after the device is turned on, reduces the on-state loss of the device, thereby increasing its switching speed and improving the device's operating characteristics .

In order to achieve the above purpose, the present invention provides a fast ionization device, which includes a metallized cathode, a highly doped n+ region, a highly doped p+ short-circuit point on the cathode side, a p base region, an n- base region, n-type ionization promoting layer, highly doped n+ short-circuit point on anode side, highly doped p+ region, metallized anode;

Wherein, the highly doped n+ region and the highly doped p+ short-circuit point on the cathode side are located between the p base region and the metallized cathode, and the highly doped n+ region and the cathode side are high The doped p+ short-circuit points have the same thickness and are alternately arranged;

The highly doped p+ region and the highly doped n+ short circuit point on the anode side are both located between the n-type ionization promoting layer and the metallized anode, and the highly doped n+ short circuit point on the anode side is connected to the high doped n+ short circuit point on the anode side. The highly doped p+ regions have the same thickness and are alternately arranged.

Preferably, the thickness of the n-base region is 400-800 μm.

Preferably, the doping concentration in the n-type ion-promoting layer is 10 ¹⁶ -10 ¹⁸ cm ^-3 ; the thickness of the n-type ion-promoting layer is 10-60 μm.

Preferably, the doping concentration in the n-type ion-promoting layer is (1-5)*10 ¹⁷ cm ^-3 ; the thickness of the n-type ion-promoting layer is 25-35 μm.

According to another aspect of the present invention, there is provided a preparation method of the fast ionization device, comprising the following steps:

(1) Impurity diffusion is carried out on the cleaned n-type Si sheet to form a PNP structure; then the p-shaped region on one side is removed by a thinning machine; a PN structure comprising a p-base region and an n-base region is obtained;

(2) Oxidize the PN structure obtained in step (1) to form a SiO ₂ mask layer, remove the SiO ₂ mask layer on the N side by photolithography, and form an n-type ionization booster on the n-base side by a diffusion process chemical layer;

(3) Simultaneously oxidize the upper surface and the lower surface of the above-mentioned silicon wafer to form a SiO ₂ layer mask layer; Through double-sided photolithography, the pattern of the photolithography plate is transferred to the two poles of the Si wafer; The etching removes the place without photoresist protection Then remove the photoresist at the _two poles of the Si wafer; then carry out impurity diffusion to form a highly doped n+ type short circuit point on the anode side and a highly doped n+ region on the cathode side;

(4) Impurity diffusion is carried out at the two poles of the above-mentioned silicon wafer to form a highly doped p+ region on the anode side and a highly doped p+ short circuit point on the cathode side;

(5) the silicon wafer obtained in step (4) is cut into a circle, and the Al sheet is punched into the same size as the Si sheet after the cut circle, and then the oxide film, organic dirt and contamination impurities on the surface of the Si sheet and the Al sheet are removed;

(6) loading the multi-layer material into the mold, each layer of material is arranged in the order of graphite-Mo sheet-Al sheet-Si sheet, and the Si sheet anode is opposite to the Al sheet, and then the loaded mold is vacuum sintered;

(7) Evaporating an Al film on the cathode surface of the Si sheet as an electrode; then annealing to form a Si-Al alloy between the cathode surface of the Si sheet and the Al film to obtain a rapid ionization device.

Preferably, in step (2), an n-type ion-promoting layer is formed on the side of the n-base region by a low-concentration phosphorus diffusion process.

Preferably, step (4) is specifically as follows: coating the two electrodes of the silicon wafer with an alcohol source made of boron oxide and aluminum nitrate, and diffusing concentrated boron to form a highly doped p+ region on the anode side and a highly doped p+ region on the cathode side short circuit point.

Preferably, in step (6), the installed mold is placed in a vacuum sintering furnace, the vacuum degree in the vacuum sintering furnace is above 10 ^-4 Pa, the sintering temperature is controlled to be 690-700°C, and the constant temperature time is 5-30min, Then, the sintering furnace is cooled at a rate of 10-20°C/min, and the temperature is naturally cooled in the air after the temperature is lowered to below 400°C.

Through the above technical scheme conceived by the present invention, compared with the prior art, the following beneficial effects can be achieved:

(1) A fast ionization FID device provided by the present invention includes a metallized cathode, a highly doped n+ region, a highly doped p+ short-circuit point on the cathode side, a p base region, an n- base region, Introduction of n-type ion-promoting layer, highly doped n+ short-circuit point on anode side, highly doped p+ region, metallized anode, and n-type ion-promoting layer with higher doping concentration than n- base region in FID device , by limiting the expansion of the space charge region of the n-base region, thereby limiting the width of the region that the collision ionization front needs to pass through, reducing the range of collision ionization front crossing, and reducing the propagation time of the collision ionization front, thereby improving the turn-on of the device. speed.

(2) The fast ionization FID device proposed by the present invention can greatly reduce the thickness of the n-base region under the condition that the blocking voltage of the FID device remains unchanged, and can significantly increase the turn-on speed. The thickness is reduced by 10%.

(3) After the FID device provided with the n-type ionization promoting layer provided by the present invention is turned on, the length of the propagation region of the collision ionization front is reduced, so the on-resistance of the device is reduced, and the residual voltage at both ends of the device is reduced, thereby reducing the The on-state loss of the device is more favorable for the device to work under the repeated frequency state.

(4) In the present invention, the n-type ionization promoting layer is introduced into the traditional FID device. By optimizing the setting of the doping concentration of the n-type ionization promoting layer and the thickness of the layer, in conjunction with the overall FID device structure, the device conducts The pass speed is significantly improved, and the residual voltage of the device is also greatly reduced.

(5) The core of the technical solution of the present invention is to provide an FID device structure including an ionization-promoting layer. Compared with the traditional FID device, the FID device using this structure has the advantages of improving the turn-on speed, reducing the on-state voltage drop and reducing the on-state voltage. loss, etc. In addition, in the preparation method of the FID device including the ionization-promoting layer structure provided by the present invention, the n-type ionization-promoting layer is formed by diffusion in the preparation process, which reduces the process cost, and then the cathode and anode patterns are transferred by double-sided lithography. process steps.

Description of drawings

1 is a schematic structural diagram of an existing rapid ionization device;

Figure 2 is a schematic diagram of the working circuit of the FID device;

3 is a schematic structural diagram of a fast ionization device comprising an ionization-promoting layer provided by the present invention;

Figure 4 shows the effect of different ionization layer concentrations on the device turn-on process;

Figure 5 shows the effect of different ionization-promoting layer thicknesses on the device turn-on process;

Fig. 6 is the simulation result of the fast ionization device with and without the ionization-promoting layer;

Throughout the drawings, the same reference numerals are used to designate the same elements or structures, wherein 1 is a metallized cathode, 2 is a highly doped n+ region, 3 is a cathode side highly doped p+ short circuit, and 4 is a p Base region, 5 is an n-base region, 6 is an n-type ion-promoting layer, 7 is a highly doped n+ short circuit point on the anode side, 8 is a highly doped p+ region, and 9 is a metallized anode.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.

A fast ionization device provided by the present invention, as shown in FIG. 3 , includes a metallized cathode 1, a highly doped n+ region 2, a highly doped p+ short-circuit point 3 on the cathode side, and a p base region 4, which are arranged adjacently in sequence. , n-base region 5, n-type ionization promoting layer 6, anode side highly doped n+ short circuit point 7, highly doped p+ region 8, metallized anode 9;

Wherein, the highly doped n+ region 2 and the highly doped p+ short circuit point 3 on the cathode side are located between the p base region 4 and the metallized cathode 1, and the highly doped n+ region 2 and The highly doped p+ short-circuit points 3 on the cathode side have the same thickness and are alternately arranged;

The highly doped p+ region 8 and the anode side highly doped n+ short circuit point 7 are both located between the n-type ionization promoting layer 6 and the metallized anode 9, and the anode side highly doped n+ The short-circuit point 7 and the highly doped p+ region 8 have the same thickness and are alternately arranged.

The metallized cathode 1 and the metallized anode 9 of the present invention can use aluminum metal.

The present invention selects and sets the thickness and doping concentration of each layer according to the withstand voltage level of the device. For example, in some embodiments, the doping concentration of the highly doped n+ region 2 is 10 ¹⁸ -10 ²⁰ cm ^-3 , and the thickness is 20-30 μm; the thickness of the p-base region 4 is 60-80 μm; The impurity concentration is 10 ¹³ -10 ¹⁴ cm ^-3 , and the thickness is 500 μm; the doping concentration of the highly doped p+ region 8 is 10 ¹⁷ -10 ¹⁹ cm ^-3 , and the thickness is 20-30 μm.

The doping concentration of the n-type ionization promoting layer of the present invention has a great influence on the turn-on speed of the device and the drop range of the residual voltage, but it is not the case that the higher the doping concentration or the thicker the ionization promoting layer, the better. Taking into account the device turn-on speed, residual voltage and ease of process realization, a feasible n-type ionization promoting layer has a doping concentration of 10 ¹⁶ -10 ¹⁸ cm ^-3 and a thickness of 10-60 μm. In addition, according to the effect of the concentration of the ion-promoting layer on the turn-on process of the device shown in Fig. 4, it can be seen that when the concentration of the ion-promoting layer reaches 1*10 ¹⁷ cm ^-3 , the turn-on speed and the residual voltage of the device no longer decrease, so In order to ensure the high implantation efficiency of the emitter, the preferred doping concentration of the n-type ionization layer is (1～5)*10 ¹⁷ cm ^-3 . The thickness of the ionization layer shown in FIG. 5 affects the device turn-on process. It can be seen that when the thickness of the ion-promoting layer is increased to 30 μm, the residual voltage of the device drops very little. Under the setting of impurity concentration and thickness, the forward blocking ability of the device will not decrease, and the emitter can be guaranteed to have a high injection efficiency, the conduction speed of the device is accelerated, and the residual voltage across the device after conduction is reduced.

The present invention also provides the preparation method of the fast ionization device, comprising the following steps:

(1) Impurity diffusion is performed on the cleaned n-type Si sheet to form a PNP structure; then the p region on one side is removed by a thinning machine to obtain a PN structure comprising p base region 4 and n-base region 5;

(2) Oxidize the PN structure obtained in step (1) to form a SiO ₂ mask layer, remove the SiO ₂ mask layer on the N side by photolithography, and form an n-type ionization booster on the n-base side by a diffusion process chemical layer 6;

(3) Simultaneously oxidize the upper surface and the lower surface of the above-mentioned silicon wafer to form a SiO ₂ layer mask layer; Through double-sided photolithography, the pattern of the photolithography plate is transferred to the two poles of the Si wafer; The etching removes the place without photoresist protection Then remove the photoresist at the _two poles of the Si wafer; then carry out impurity diffusion to form a highly doped n+ type short circuit point 7 on the anode side and a highly doped n+ region 2 on the cathode side;

(4) Impurity diffusion is performed at the two poles of the above-mentioned silicon wafer to form a highly doped p+ region 8 on the anode side and a highly doped p+ short circuit point 3 on the cathode side;

(5) Cut the circle, and punch the Al sheet into the same size as the Si sheet after the cut circle, and then remove the oxide film, organic dirt and contamination impurities on the surface of the Si sheet and the Al sheet;

(6) load the multi-layer material into the mold, each layer of material is arranged in the order of "graphite-Mo sheet-Al sheet-Si sheet", and the Si sheet anode is opposite to the Al sheet, and then the loaded mold is vacuum sintered;

(7) Evaporating an Al film on the cathode surface of the Si sheet as an electrode; then annealing to form a Si-Al alloy between the cathode surface of the Si sheet and the Al film to obtain a rapid ionization device.

In some embodiments, step (1) performs Ga and Al diffusion on the cleaned n-type Si wafer to form a PNP structure.

In some embodiments, in step (2), an n-type ionization promoting layer 6 is formed on the side of the n-base region of the silicon wafer in step (1) by a low-concentration phosphorus diffusion process.

In some embodiments, in step (3), phosphorus diffusion is performed to form a highly doped n+ type short-circuit point 7 on the anode side and a highly doped n+ region 2 on the cathode side.

In some embodiments, step (4) is specifically as follows: coating an alcohol source made of boron oxide (B ₂ O ₃ ) and aluminum nitrate (Al(NO ₃ ) ₃ ) on both the anode side and the cathode side of the silicon wafer, and performing the process. Concentrated boron diffuses to form a highly doped p+ region 8 on the anode side and a highly doped p+ short-circuit point 3 on the cathode side.

In some embodiments, in step (6), the installed mold is placed in a vacuum sintering furnace, the vacuum degree in the vacuum sintering furnace is above 10 ^-4 Pa, the sintering temperature is controlled at 690-700 ° C, and the constant temperature time is 5-30 minutes; then cool down the sintering furnace at a rate of 10-20°C/min, and it can be cooled naturally in the air when it is below 400°C.

In some embodiments, it also includes the steps of:

(8) Grinding to form positive and negative double bevel terminals; then performing mesa corrosion and mesa protection, and finally performing die packaging.

The following are examples:

Example 1

As shown in FIG. 3, a fast ionization device structure includes: metallized cathode 1, highly doped n+ region 2, highly doped p+ short circuit point 3 on the cathode side, p base region 4, n- base region 5, n-type Ionization promoting layer 6 , highly doped n+ short circuit point 7 on anode side, highly doped p+ region 8 , metallized anode 9 . The highly doped p+ region 8 is located on the side of the metallized anode 9, and the highly doped n+ short circuit point 7 on the anode side is located between the highly doped p+ regions 8 on the side of the metallized anode 9; the n-type ionization promoting layer 6 is located on the highly doped p+ Layer 8, between the highly doped n+ short-circuit point 7 on the anode side and the n- base region 5, the p base region 4 is located above the n- base region 5, and the highly doped n+ region 2 is located between the p base region 4 and the metallized cathode 1. During this time, the highly doped p+ short-circuit point 3 on the cathode side is located between the highly doped n+ regions 2 on the metallized cathode 1 side, and three PN junctions J ₁ , J ₂ and J ₃ are formed in the structure.

The preparation process of the fast ionization device is as follows:

(1) Select n-type Si single crystal;

(2) Cleaning the Si wafer. Wash with ammonium hydroxide (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ) and water (H ₂ O) in a 1:2:5 ratio, and with hydrochloric acid (HCl), hydrogen peroxide (H ₂ O ₂ ) and The cleaning solution prepared with water (H ₂ O) in a ratio of 1:2:8 was used to clean the silicon wafers at 65°C for 10 minutes each;

(3) PNP structure is formed through Ga and Al diffusion, the surface concentration is 1*10 ¹⁶ cm ^-3 , and the diffusion junction depth is set to 100 μm;

(4) Use a wafer thinning machine to remove the p-type region on one side, and set the thinning thickness to 100 μm;

(5) An n-type ion-promoting layer is formed by a low-concentration phosphorus diffusion process, with a surface concentration of 1*10 ¹⁷ cm ^-3 and a thickness of 30 μm; that is, the distance from the n-type ion-promoting layer to the metal anode is 60 μm;

(6) Oxidation to form a SiO ₂ mask layer. Oxidize silicon wafers at 1180°C, pass dry oxygen (O ₂ ) for 1 hour → wet oxygen (steam) for 4 hours → dry oxygen (O ₂ ) for 1 hour;

(7) Double-sided lithography, transferring the pattern of the lithography plate to the two poles of the Si wafer;

(8) Etch to remove the SiO ₂ layer where there is no photoresist protection. The silicon wafer after photolithography was etched with a reagent prepared by hydrofluoric acid (HF), ammonium fluoride (NH ₄ F), and water (H ₂ O) in a ratio of 3:6:10. The water bath temperature was 65°C for 3 minutes. ;

(9) Remove glue. The residual photoresist on the Si wafer was removed with concentrated sulfuric acid (H ₂ SO ₄ ).

(10) Phosphorus diffuses to form a highly doped n+ region on the cathode side and a highly doped n+ short-circuit point on the anode side. Nitrogen (N ₂ ) carried the phosphorus source through phosphorus oxychloride (POCl ₃ ), and pre-deposited on the silicon wafer for 50 minutes, the temperature was raised from 1000°C to 1250°C, and the temperature was kept at 1250°C for 1.5 hours;

(11) Circumcision. Cut the Si wafer to the required size;

(12) Punching the Al sheet into a wafer with the same diameter as the Si sheet, and the thickness of the Al sheet is 30 μm;

(13) Rinse the Al sheet and the Si sheet with a 1:9 etching solution of hydrofluoric acid (HF): nitric acid (HNO ₃ ) for 4 seconds to remove the surface oxide film, residual organic dirt and contamination impurities, improve Al Wetting between the sheet and the Si sheet to form a flat, uniform large-area alloy pn junction;

(14) Coat the anode side and cathode side of the silicon wafer with an alcohol source composed of boron oxide (B ₂ O ₃ ) and aluminum nitrate (Al(NO ₃ ) ₃ ), respectively, to carry out concentrated boron diffusion, at 1200° C. Diffusion for 30 minutes;

(15) After stacking in the order of "graphite-Mo sheet-Al sheet-Si sheet-graphite-Mo sheet-Al sheet-Si sheet-...", put the mold into the vacuum sintering furnace, Among them, the Si sheet anode is opposite to the Al sheet;

(16) Evacuate the sintering furnace to make the vacuum degree above 10 ^-4 Pa, control the sintering temperature at 690°C, and keep the constant temperature for 5 to 30 minutes;

(17) Cool down the sintering furnace at a rate of 15°C/min, and let it cool down naturally in the air below 400°C;

(18) Coating. Evaporate a layer of Al film on the cathode surface of the Si wafer in a vacuum coating machine;

(19) Annealing. Vacuum anneal the Si wafer at 500℃;

(20) Grinding corners. Form positive and negative double bevel terminals to reduce surface electric field and improve withstand voltage;

(21) Corrosion. Prepare a corrosion solution with nitric acid (HNO ₃ ), hydrofluoric acid (HF), phosphoric acid (H ₃ PO ₄ ), and acetic acid (CH ₃ COOH) in a ratio of 3:2:2:2, and etch for 1 minute at room temperature;

(22) Countertop protection. The countertop is coated with silicone rubber for protection and cured at room temperature for 3 days;

(23) Die package.

Comparative Example 1

The structure of the ionization device of this comparative example is shown in Figure 1. Compared with the fast ionization device of Example 1, only the n-type ionization promoting layer is missing, and the length of the n-base region of the ionization device of this comparative example is 560 μm, while the length of the n-base region of the ionization device of Example 1 is 500 μm, the surface concentration of the n-type ionization promoting layer is 1*10 ¹⁷ cm ⁻³ , and the thickness is 30 μm. Other structural layers are the same.

As shown in FIG. 6 , when the FID device is triggered and turned on in the simulation, the waveforms of the voltages at both ends of the FID device with the ionization layer structure in Example 1 and the FID device without the ionization layer structure in Comparative Example 1 are obtained from the simulation results. It can be seen that the voltage across the FID device with the ion-promoting layer structure decreases faster after triggering, and the residual voltage is lower, which is in line with the design goal of the ion-promoting layer.

After the n-type ionization promoting layer is added to the FID device in the embodiment of the present invention, the thickness of the n-base region can be greatly reduced under the condition that the blocking voltage of the FID device remains unchanged. In addition, when the FID device is working, the metallized anode is connected to the forward voltage, the voltage difference between the metallized anode and the metallized cathode is less than the blocking voltage of the device design, and the device is in a forward blocking state. At this time, the n-base region It forms a space charge region with some regions in the p base region; when triggering, the metallized anode applies a trigger pulse with a voltage rise rate greater than 1kV/ns, the anode voltage rises rapidly, and the space charge region of the n-base region expands rapidly, but due to n The concentration of the ion-promoting layer is significantly higher than that of the n-base region, so the space charge region of the n-base region cannot be further expanded after it extends to the n-type ion-promoting layer. The width of the n-base region is smaller than the width of the n-base region without the ionization layer, so the length of the space charge region before the device is turned on is greatly reduced, and the electric field intensity distribution in the n-base region is flatter, which is more beneficial to the device. Propagation of the impact ionization front during conduction; when the voltage across the device reaches _two to three times the maximum blocking voltage of the device, the electric field strength at the J junction exceeds the critical breakdown field strength, and the propagation of the impact ionization front begins inside the device; Since the n-type ionization-promoting layer prevents the further expansion of the space charge region after the space charge region extends to the entire n-base region, the width of the region that the collision ionization front needs to pass through is limited, and the range of the collision ionization front is reduced.

In this embodiment, the n-type ionization promoting layer can further reduce the propagation time of the collision ionization front by limiting the width of the region traversed by the collision ionization front, thereby increasing the turn-on speed. After the device is turned on, the length of the propagation area of the impact ionization front is reduced, so the on-resistance of the device is reduced, and the residual voltage across the device is reduced, thereby reducing the on-state loss of the device, which is more conducive to the device operating in the repeated frequency state. .

Those skilled in the art can easily understand that the above are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention, etc., All should be included within the protection scope of the present invention.

Claims (5)

1. A rapid ionization device is characterized by comprising a metalized cathode (1), a highly-doped n + region (2), a cathode side highly-doped p + short-circuit point (3), a p base region (4), an n-base region (5), an n-type ionization promoting layer (6), an anode side highly-doped n + short-circuit point (7), a highly-doped p + region (8) and a metalized anode (9) which are arranged adjacently in sequence;

wherein the highly doped n + region (2) and the cathode side highly doped p + short point (3) are both located between the p base region (4) and the metallization cathode (1), and the highly doped n + region (2) and the cathode side highly doped p + short point (3) have the same thickness and are alternately arranged;

the highly doped p + region (8) and the anode-side highly doped n + short-circuit point (7) are both located between the n-type ionization promoting layer (6) and the metallization anode (9), and the anode-side highly doped n + short-circuit point (7) and the highly doped p + region (8) have the same thickness and are arranged alternately;

the doping concentration in the n-type ionization promoting layer (6) is (1-5) × 10 ¹⁷ cm ^-3 (ii) a The thickness of the n-type ionization promoting layer (6) is 25-35 μm; the doping concentration of the highly doped p + region is 10 ¹⁷ ～10 ¹⁹ cm ^-3 The thickness is 20-30 μm; the thickness of the n-base region (5) is 400-800 μm.

2. The method for preparing a rapid ionization device according to claim 1, comprising the steps of:

(1) carrying out impurity diffusion on the cleaned n-type Si wafer to form a PNP structure; then removing the p-shaped region on one side of the substrate by a thinning machine; obtaining a PN structure comprising a p base region (4) and an n-base region (5);

(2) oxidizing the PN structure obtained in the step (1) to form SiO ₂ A mask layer formed by removing SiO on the N side by photolithography ₂ A layer mask layer, wherein an n-type separation promoting layer (6) is formed on the n-base region side through a diffusion process;

(3) oxidizing the upper surface and the lower surface of the silicon wafer simultaneously to form SiO ₂ A layer mask layer; transferring the pattern of the photoetching plate to two electrodes of the Si wafer by double-sided photoetching; etching to remove SiO at the position without photoresist protection ₂ A layer; then removing the photoresist on the two electrodes of the Si wafer; then, impurity diffusion is performed to form a highly doped n + -type short-circuit point (7) on the anode side and a highly doped n + -type short-circuit point on the cathode sideDoping an n + region (2);

(4) impurity diffusion is carried out on the two poles of the silicon wafer to form a highly doped p + region (8) on the anode side and a highly doped p + short-circuit point (3) on the cathode side;

(5) rounding the silicon wafer obtained in the step (4), punching an Al sheet into the same size as the rounded Si sheet, and removing an oxide film, organic dirt and contamination impurities on the surfaces of the Si sheet and the Al sheet;

(6) loading the multilayer materials into a mold, arranging each layer of material according to the sequence of graphite-Mo sheets-Al sheets-Si sheets, enabling Si sheet anodes to be opposite to the Al sheets, and then carrying out vacuum sintering on the loaded mold;

(7) evaporating an Al film on the cathode surface of the Si sheet to be used as an electrode; and then annealing to form Si-Al alloy between the cathode surface of the Si sheet and the Al film, thereby obtaining the rapid ionization device.

3. A manufacturing method according to claim 2, wherein the step (2) forms the n-type ionization promoting layer (6) on the n-base region side by a low concentration phosphorus diffusion process.

4. The preparation method according to claim 2, wherein the step (4) is specifically: coating an alcohol source prepared from boron oxide and aluminum nitrate on two electrodes of the silicon wafer, and performing concentrated boron diffusion to form a highly doped p + region (8) on the anode side and a highly doped p + short-circuit point (3) on the cathode side.

5. The production method according to claim 2, wherein the step (6) places the assembled mold in a vacuum sintering furnace having a degree of vacuum of 10 ^-4 And Pa above, controlling the sintering temperature to be 690-700 ℃, keeping the temperature for 5-30min, cooling the sintering furnace at the speed of 10-20 ℃/min, and naturally cooling in the air after the temperature is reduced to below 400 ℃.

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