CN103258741B - Nano-wire field effect transistor and forming method thereof - Google Patents
Nano-wire field effect transistor and forming method thereof Download PDFInfo
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- CN103258741B CN103258741B CN201210039335.5A CN201210039335A CN103258741B CN 103258741 B CN103258741 B CN 103258741B CN 201210039335 A CN201210039335 A CN 201210039335A CN 103258741 B CN103258741 B CN 103258741B
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Abstract
A kind of nano-wire field effect transistor and forming method thereof, form the method for nano-wire field effect transistor to comprise: SOI substrate is provided, SOI substrate comprises the first Semiconductor substrate, the buried regions be positioned in the first Semiconductor substrate, the second Semiconductor substrate be positioned on buried regions; Graphical second Semiconductor substrate forms source region, drain region and nano wire; Remove the buried regions of nano wire inferior portion thickness, to form groove, make nano wire be suspended in groove; The side in the region that the second Semiconductor substrate after graphical surrounds with residue buried regions forms side wall; Form the grid structure comprising grid and gate dielectric layer between the side wall of the side wall in side, source region and side, drain region, the width sum of grid and side wall equals the length of nano wire; Ion doping is carried out to source region and drain region, forms source electrode and drain electrode.The technical program shortens the length of nano wire, can reduce the series resistance between source electrode and drain electrode.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to nano-wire field effect transistor and forming method thereof.
Background technology
Integrated circuit develops into integrated millions of device from integrated tens of devices single chip.The performance of traditional integrated circuit and complexity are considerably beyond the initial imagination.In order to realize the raising in complexity and current densities (quantity of the device that can hold on certain chip area), the characteristic size of device, also referred to as " physical dimension (geometry) ", along with the integrated circuit of every generation becomes less and less.Improve complexity and performance that integrated circuit density not only can improve integrated circuit, and also can reduce consumption for consumers.Based on the demand to integrated circuit (IC) chip high density, high speed, low-power consumption, integrated circuit is more and more to high density, high speed, low-power consumption future development.
When the characteristic size of the field-effect transistor in integrated circuit is reduced to below 32nm, the formation method of traditional field-effect transistor is inadaptable, proposes nano-wire field effect transistor (NanowireFET).Wherein nano-wire field effect transistor refers to that channel length is the field-effect transistor of nanometer (nm) order of magnitude, and in fact, namely the length of raceway groove is short to field-effect transistor when intending with the thickness comparability of raceway groove.Nano-wire field effect transistor has high current on/off ratio, causes potential barrier reduction effects less by short-channel effect and leakage simultaneously.
Fig. 1 ~ Fig. 5 is the cross-sectional view of the method for the manufacture nano-wire field effect transistor of prior art, and the method for the manufacture nano-wire field effect transistor of prior art is:
With reference to figure 1, provide SOI substrate, wherein SOI substrate comprises: the first Semiconductor substrate 11, the buried regions 12 be positioned in the first Semiconductor substrate 11, the second Semiconductor substrate 13 be positioned on buried regions 12.
With reference to figure 2, utilize photoetching, graphical second Semiconductor substrate 13 of etching technics forms nano wire 131, is positioned at source region 132, the drain region 133 at nano wire 131 two ends.
With reference to figure 3, carry out wet etching, form groove 121 in buried regions 12 to buried regions 12, nano wire 131 is suspended in above groove 121, anneals to nano wire 131, makes nano wire 131 cylindrical or oval.
With reference to figure 4, depositing conducting layer and hard mask layer, to the hard mask layer 15 that conductive layer and hard mask layer carry out photoetching, etching technics formation grid 14 and be positioned on grid 14, this grid 14 surrounds nano wire 131 in its surrounding, and the length of nano wire 131 is greater than the thickness of grid 14.
With reference to figure 5, metallization medium layer, carries out back carving (etchback) to dielectric layer and forms side wall 16 in the surrounding of grid 14.Be less than the length d of nano wire 131 in the thickness d 1 of the side wall 16 of nano wire 131 bearing of trend and the thickness d 2 sum d1+d1+d2 of grid 14, therefore nano wire 131 stretches out side wall, has and is exposed to extraneous part.
Afterwards, ion implantation can be carried out and form source electrode and drain electrode source region 132, drain region 133.
The method of the formation nano-wire field effect transistor of the above prior art, the length forming nano wire is comparatively large, is greater than the thickness of side wall 16 and the thickness sum of grid 14, and the resistance between such source electrode and drain electrode is comparatively large, can affect the performance of device.
In prior art, there are many patents about nanometer field wire effect transistor and patent application, such as publication number is " NanowireFETwithTrapezoidgatestructure (having the nano-wire field effect transistor of terraced gate structure) " disclosed in the U.S. Patent application of US2011315950A1, but, all do not solve above technical problem.
Summary of the invention
The problem that the present invention solves is the method that prior art forms nano-wire field effect transistor, and the length of the nano wire of formation is comparatively large, is greater than the thickness of side wall on nano wire bearing of trend and the thickness sum of grid, causes the resistance between source electrode and drain electrode larger.
For solving the problem, the invention provides a kind of method forming nano-wire field effect transistor, comprising:
SOI substrate is provided, described SOI substrate comprises the first Semiconductor substrate, the buried regions be positioned in described first Semiconductor substrate, the second Semiconductor substrate be positioned on described buried regions;
Graphically described second Semiconductor substrate forms source region, drain region and nano wire;
Remove the buried regions of described nano wire inferior portion thickness, to form groove, make nano wire be suspended in groove;
The side in the region that the second Semiconductor substrate after graphical surrounds with residue buried regions forms side wall;
Grid structure is formed between the side wall and the side wall of side, drain region of side, described source region, described grid structure comprises grid and the gate dielectric layer between described grid and nano wire, and on nano wire bearing of trend, the width sum of grid and side wall equals the length of described nano wire;
Ion doping is carried out to described source region and drain region, forms source electrode and drain electrode.
Alternatively, graphically described second Semiconductor substrate forms source region, drain region and nano wire, and the buried regions removing described nano wire inferior portion thickness comprises:
Described second Semiconductor substrate forms patterned mask layer, defines the position of source region, drain region and nano wire;
With described patterned mask layer for mask, etch described second Semiconductor substrate and form source region, drain region and nano wire and the buried regions of the described nano wire inferior portion thickness of etching removal;
Remove the patterned mask layer be positioned on described nano wire;
Described side wall is also positioned at the side of described patterned mask layer.
Alternatively, described second Semiconductor substrate forms patterned mask layer, defines source region, the position of drain region and nano wire comprises:
Described second Semiconductor substrate forms hard mask layer;
Graphical described hard mask layer, defines the position of nano wire;
Form dielectric layer, cover described patterned hard mask layer and described second Semiconductor substrate;
Graphical described dielectric layer, defines the position of source region and drain region.
Alternatively, described hard mask layer is silicon nitride layer.
Alternatively, described dielectric layer is silicon oxide layer.
Alternatively, after removing the patterned mask layer be positioned on described nano wire, also comprise before forming side wall: in hydrogen atmosphere, annealing process is carried out to described nano wire.
Alternatively, the formation method of described side wall comprises:
Form dielectric layer, cover described patterned mask layer, remaining buried regions;
Dielectric layer described in dry etching forms side wall;
Remove the dielectric layer under described nano wire.
Alternatively, the dielectric layer under utilizing isotropism dry method or wet etching to remove described nano wire
Alternatively, described dielectric layer is single layer structure or laminated construction.
Alternatively, the dielectric layer of described single layer structure is silicon oxide layer or silicon nitride layer.
Alternatively, after formation grid structure, before ion doping is carried out to described source region and drain region, also comprise:
Remove patterned mask layer on described source region, on drain region.
Alternatively, wet etching is utilized to remove patterned mask layer on described source region, on drain region.
Alternatively, the method forming grid structure comprises:
Form gate dielectric layer and conductive layer successively, cover patterned mask layer on described side wall, source region and drain region, remaining buried regions and nano wire;
Carry out planarization to described conductive layer and gate dielectric layer and form grid structure, the end face of described grid structure is equal with the end face of described side wall.
Alternatively, described flattening method is chemical mechanical milling tech.
Alternatively, the material of described conductive layer is metal or polysilicon.
Alternatively, described first Semiconductor substrate is silicon substrate.
Alternatively, described second Semiconductor substrate is silicon substrate.
Alternatively, described buried regions is silicon oxide layer.
The present invention also provides a kind of nano-wire field effect transistor, comprising:
First Semiconductor substrate;
Be positioned at the buried regions in described first Semiconductor substrate, described buried regions has groove;
Be positioned at source electrode on the buried regions of described groove both sides and drain electrode, be suspended in described groove and with source electrode and the nano wire be connected that drains;
Grid structure and be positioned at the side wall of described grid structure surrounding, described grid structure and side wall are between described source electrode, drain electrode and surround described nano wire, described grid structure comprises grid and the gate dielectric layer between described grid and nano wire, and the width sum of described grid and side wall equals the length of described nano wire.
Alternatively, the material of described grid is metal or polysilicon.
Alternatively, described first Semiconductor substrate is silicon substrate.
Alternatively, the material of described source electrode, drain electrode and nano wire is silicon, and has Doped ions in described source electrode and drain electrode.
Alternatively, described buried regions is silicon oxide layer.
Compared with prior art, the present invention has the following advantages:
The technical program forms the method for nano-wire field effect transistor, provide comprise the first Semiconductor substrate, the SOI substrate of the buried regions be positioned in described first Semiconductor substrate, the second Semiconductor substrate be positioned on buried regions; Afterwards, first graphical second Semiconductor substrate forms source region, drain region and nano wire, removes the buried regions of described nano wire inferior portion thickness, below nano wire, forms groove, make nano wire be suspended in groove; Then, in the side of described source region, the side of drain region, the side of residue buried regions form side wall; Between the side wall and the side wall of side, drain region of side, described source region, form the grid structure comprising grid and gate dielectric layer, on nano wire bearing of trend, the width sum of grid and side wall equals the length of described nano wire; Ion doping is carried out to described source region and drain region, forms source electrode and drain electrode.That is, the technical program first forms side wall, then between side wall, grid structure is formed, self-registered technology is utilized when forming grid structure, depositing operation can be utilized to form gate dielectric layer and conductive layer, afterwards flatening process is carried out to conductive layer and gate dielectric layer and form grid structure, do not need to utilize photoetching, etching technics formation grid structure, therefore the width sum of grid and side wall equals the length of nano wire, the length of nano wire is shortened relative to prior art, the series resistance between source electrode and drain electrode can be reduced, improve the performance of device.
Accompanying drawing explanation
Fig. 1 ~ Fig. 5 is the cross-sectional view of the method for the manufacture nano-wire field effect transistor of prior art;
Fig. 6 is the schematic flow sheet of the method for the formation nano-wire field effect transistor of the specific embodiment of the invention;
Fig. 7 ~ Figure 17 is the cross-sectional view of the method for the formation nano-wire field effect transistor of the specific embodiment of the invention.
Embodiment
In prior art, first utilize photoetching, etching technics forms grid, then around grid, side wall is formed, due to photoetching, the resolution of etching technics and lithographic accuracy all have certain limit, in photoetching, in etching process, there will be map migration phenomenon, in order to avoid grid is to source electrode or drain directions skew, cause grid across on source electrode or drain electrode, therefore the length of nano wire is increased, nano wire is had and is exposed to extraneous part, even if grid is to source electrode or drain directions skew, grid is also only offset on nano wire, and can not across on source electrode or drain electrode, but, the length that this kind of method result in nano wire is longer, thus the series resistance increased between source electrode and drain electrode, and then the performance of device reduces.In order to reduce the length of nano wire, to reduce the resistance between source electrode and drain electrode, the technical program first forms side wall, then between side wall, form the grid structure comprising grid and gate dielectric layer, utilize self-registered technology when forming grid structure, do not need to utilize photoetching, etching technics, therefore the width sum of grid and side wall equals the length of nano wire, shorten the length of nano wire relative to prior art, the series resistance between source electrode and drain electrode can be reduced, improve the performance of device.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here to implement with multiple, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention.Therefore the present invention is not by the restriction of following public embodiment.
Fig. 6 is the schematic flow sheet of the method for the formation nano-wire field effect transistor of the specific embodiment of the invention, and with reference to figure 6, the method for the formation nano-wire field effect transistor of the specific embodiment of the invention, comprising:
Step S61, provides SOI substrate, and described SOI substrate comprises the first Semiconductor substrate, the buried regions be positioned in described first Semiconductor substrate, the second Semiconductor substrate be positioned on described buried regions;
Step S62, graphically described second Semiconductor substrate forms source region, drain region and nano wire;
Step S63, removes the buried regions of described nano wire inferior portion thickness, to form groove, makes nano wire be suspended in groove;
Step S64, the side in the region that the second Semiconductor substrate after graphical surrounds with residue buried regions forms side wall;
Step S65, grid structure is formed between the side wall and the side wall of side, drain region of side, described source region, described grid structure comprises grid and the gate dielectric layer between described grid and nano wire, and on nano wire bearing of trend, the width sum of grid and side wall equals the length of described nano wire;
Step S66, carries out ion doping to described source region and drain region, forms source electrode and drain electrode.
Fig. 7 ~ Figure 17 is the cross-sectional view of the method for the formation nano-wire field effect transistor of the specific embodiment of the invention, below in conjunction with the method for formation nano-wire field effect transistor describing the specific embodiment of the invention with reference to figure 6 and Fig. 7 ~ Figure 17 in detail.
In conjunction with reference to figure 6 and Fig. 7, perform step S61, SOI substrate is provided, described SOI substrate comprises the first Semiconductor substrate 71, the buried regions 72 be positioned in described first Semiconductor substrate 71, the second Semiconductor substrate 73 be positioned on described buried regions 72.The material of the first Semiconductor substrate 71 is monocrystalline silicon, monocrystalline germanium or monocrystalline germanium silicon, iii-v element compound, monocrystalline silicon carbide; The material of the second Semiconductor substrate 73 is monocrystalline silicon, monocrystalline germanium or monocrystalline germanium silicon, iii-v element compound, monocrystalline silicon carbide; Buried regions 72 is silicon oxide layer, but is not limited to silicon oxide layer, other dielectric layers that also can be known to the skilled person.
In conjunction with reference to figure 6 and Figure 11, perform step S62, graphically described second Semiconductor substrate 73 forms source region 731, drain region 732 and nano wire 733; Perform step S63, remove the buried regions 72 of described nano wire 733 inferior portion thickness, to form groove 74, nano wire 733 is suspended in groove 74.Graphically described second Semiconductor substrate 73 forms source region 731, drain region 732 and nano wire 733, the buried regions 72 removing described nano wire 733 inferior portion thickness comprises: with reference to Figure 10, described second Semiconductor substrate 73 forms patterned mask layer 83, defines the position of source region, drain region and nano wire; With reference to Figure 11, with described patterned mask layer 83 for mask, etch described second Semiconductor substrate 73 and form source region 731, drain region 732 and nano wire 733 and the buried regions 72 of the described nano wire 733 inferior portion thickness of etching removal; With reference to Figure 12, remove the patterned mask layer be positioned on described nano wire 733.Wherein, described second Semiconductor substrate 73 forms patterned mask layer, define source region, the position of drain region and nano wire comprises: with reference to figure 7, described second Semiconductor substrate forms hard mask layer 81; With reference to figure 8, graphical described hard mask layer, forms patterned hard mask layer 811, defines the position of nano wire; With reference to figure 9, form dielectric layer 82, cover described patterned hard mask layer 811 and described second Semiconductor substrate 73; With reference to Figure 10, graphical described dielectric layer forms patterned dielectric layer 821, defines the position of source region and drain region.Wherein, patterned dielectric layer 821 and patterned hard mask layer 811 together constitute patterned mask layer 83.
The concrete method of step S62 and step S63 is:
With reference to figure 7, second Semiconductor substrate 73 forms hard mask layer 81, in the specific embodiment of the invention, the material of hard mask layer 81 is silicon nitride, but the material of hard mask layer is not limited to silicon nitride, other dielectric materials that can use as hard mask that also can be known to the skilled person.The thickness of hard mask layer 81 needs to determine according to the actual requirements.
With reference to figure 8, in the specific embodiment of the invention, utilize photoetching, the graphical hard mask layer 81 of etching technics, form patterned hard mask layer 811, concrete patterned hard mask layer 811 is the hard mask layer of many strips arranged in parallel, the hard mask layer of this strip defines the position of nano wire, and outside the position of also extending nano wire, the hard mask layer of same strip defines the position of multiple nano wires point-blank.In other embodiments, also can be and utilize photoetching, the graphical hard mask layer of etching technics, form the hard mask layer of the strip in arrayed, the hard mask layer of each strip defines the position of nano wire, the hard mask layer of corresponding strip does not extend outside the position of nano wire, and the position of multiple nano wires is point-blank defined by the hard mask layer of the multiple strips be located along the same line respectively.
Only illustrate the hard mask layer of two strips in Fig. 8, play and object of the present invention is described.The quantity of the hard mask layer of the strip of concrete formation is determined according to actual needs.
With reference to figure 9, form dielectric layer 82, the hard mask layer 811 after cover graphics and the second Semiconductor substrate 73, in the embodiment of the present invention, dielectric layer 82 is silicon oxide layer, but is not limited to silicon oxide layer, other dielectric layers that also can be known to the skilled person.Afterwards, with reference to Figure 10, utilize photoetching, etching technics patterned media layer forms patterned dielectric layer 821, patterned dielectric layer 821 defines source region, drain region.Wherein, patterned hard mask layer 811 and patterned dielectric layer 821 form the patterned mask layer 83 in the embodiment of the present invention jointly.
It should be noted that, in the present invention, patterned mask layer 83 is not limited to be made up of patterned hard mask layer 811 and patterned dielectric layer 821.The method forming patterned mask layer 83, for first to form patterned hard mask layer 811, defines the position of nano wire, then forms patterned dielectric layer, defines the position of source region and drain region.In the present invention, the formation method of patterned mask layer 83 is not limited to specific embodiment described above, also can be, forms mask layer, then Patterned masking layer, defines the position of nano wire, source region, drain region.Also can be known to the skilled person, other can define the method for position of nano wire, source region, drain region.
With reference to Figure 11, with patterned mask layer 83 for mask, etch the second Semiconductor substrate 73 and form source region 731, drain region 732 and nano wire 733; Afterwards, etching buried regions 72, remove the buried regions of nano wire inferior portion thickness, in buried regions 72, form groove 74, make nano wire 733 be suspended in groove 74, that is, the second Semiconductor substrate 73 and buried regions 72 is etched successively for mask with patterned mask layer 83, but when etching buried regions 72, the only buried regions of etched portions thickness, concrete etch thicknesses needs to determine according to actual process.The method etching the second Semiconductor substrate 73 and buried regions 72 is dry etching.
Afterwards, with reference to Figure 12, remove the patterned hard mask layer 811 be positioned on described nano wire, the method removing hard mask layer 811 is wet etching.After removing patterned hard mask layer 811, carry out annealing process to described nano wire 733 in hydrogen atmosphere, the shape of nano wire 733 is become the shape of edge-smoothing clearly from original corner angle, such as, become cylindrical from square column type.Annealing process makes the surface roughness of nano wire improve, and carrier scattering phenomenon can be made like this to reduce, and mobility improves, thus can improve the performance of device.
In conjunction with reference to figure 6 and Figure 14, perform step S64, the side in the region that the second Semiconductor substrate after graphical surrounds with residue buried regions forms side wall 75, namely side wall 75 is formed in the side of groove, the side of the second Semiconductor substrate namely after graphically and the side of residue buried regions form side wall 75, Semiconductor substrate after wherein graphical comprises source region and drain region, therefore in the side of source region 731, the side of drain region 732 defines side wall 75.Because on, source region and drain region, patterned mask layer is not also removed, therefore side wall 75 is also positioned at the side of patterned mask layer and patterned dielectric layer 821 on described source region, on drain region.The method of concrete formation side wall comprises: with reference to Figure 13, form dielectric layer, cover remaining patterned mask layer and patterned dielectric layer 821, remaining buried regions 72, specific embodiment of the invention dielectric layer is silicon oxide layer, but be not limited to silicon oxide layer, other dielectric layers that also can be known to the skilled person; Then, dielectric layer described in dry etching forms side wall 75; The method forming dielectric layer is CVD (Chemical Vapor Deposition) method, below nano wire 733, be also formed with dielectric layer, but when etch media layer forms side wall 75, due to the effect of the mask of nano wire 733, the dielectric layer below nano wire can not etch removal; Therefore, afterwards, with reference to Figure 14, remove the dielectric layer under described nano wire 733, be specially the dielectric layer under utilizing isotropism dry method or wet etching to remove described nano wire 733.
In conjunction with reference to figure 6 and Figure 15, perform step S65, grid structure is formed between the side wall and the side wall of side, source region 732 of side, described source region 731, described grid structure comprises grid 76 and the gate dielectric layer (not shown) between described grid 76 and nano wire 733, and on nano wire 733 bearing of trend, the width d1 of grid 73 and the width 2d2 sum of side wall equal the length d of described nano wire.Concrete, the method forming grid structure comprises: form gate dielectric layer and conductive layer successively, cover patterned mask layer, remaining buried regions 72 and nano wire 733 on described side wall 75, source region 731 and drain region 732, on source region 731 and drain region 732, patterned mask layer is patterned dielectric layer 821 in this embodiment; Afterwards, carry out planarization to described conductive layer and gate dielectric layer and form the grid structure comprising grid 76 and gate dielectric layer, the end face of described grid structure is equal with the end face of described side wall 75, and namely the end face of described grid 76 is equal with the end face of described side wall 75.Flattening method is chemical mechanical milling tech.The material of conductive layer is metal or polysilicon.It should be noted that, the end face of grid is equal with the end face of side wall and do not mean that both are strictly equal, allows under certain process conditions, to there is certain error between the two.
In conjunction with reference to figure 6 and Figure 16, perform step S66, ion doping is carried out to described source region 731 and drain region 732, form source electrode 734 and drain electrode 735.Concrete formation method is: after formation grid 76, before ion doping is carried out to described source region 731 and drain region 732, remove patterned mask layer on described source region 731, on drain region 732, namely remove patterned dielectric layer 821, be specially and utilize wet etching to remove patterned mask layer on described source region, on drain region.Then, ion doping is carried out to described source region 731 and drain region 732, form source electrode 734 and drain electrode 735.Wherein, need to determine according to the actual requirements to ionic type, dosage, energy etc. that ion doping is carried out in described source region 731 and drain region 732.
Afterwards, with reference to Figure 17, source electrode 734, drain electrode 735, grid 76 form metal silicide layer 77.Then, form interlayer dielectric layer, then in interlayer dielectric layer, form contact hole, with source electrode 734, drain 735, grid 76 is electrically connected.The method of concrete formation metal silicide layer 77, formation contact hole is art technology known technology, does not repeat at this.
The technical program first forms side wall, then between side wall, grid structure is formed, self-registered technology is utilized when forming grid structure, depositing operation can be utilized to form gate dielectric layer and conductive layer, afterwards flatening process is carried out to conductive layer and gate dielectric layer and form the grid structure comprising grid and gate dielectric layer, do not need to utilize photoetching, etching technics formation grid, therefore the width sum of grid and side wall equals the length of nano wire, the length of nano wire is shortened relative to prior art, the series resistance between source electrode and drain electrode can be reduced, improve the performance of device.
Based on the method for formation nano-wire field effect transistor described above, with reference to Figure 16, the specific embodiment of the invention also provides a kind of nano-wire field effect transistor, comprising: the first Semiconductor substrate 71; Be positioned at the buried regions 72 in described first Semiconductor substrate 71, described buried regions 72 has groove; Be positioned at source electrode 734 on described groove both sides buried regions 72 and drain electrode 735, be suspended in described groove and with source electrode 734 and 735 nano wires be connected 733 that drain; Grid structure and be positioned at the side wall 75 of described grid structure surrounding, described grid structure and side wall 75 are between described source electrode 734, drain electrode 735 and surround described nano wire 733, described grid structure comprises grid 76 and the gate dielectric layer (not shown) between described grid 76 and nano wire 733, and the width sum of described grid 76 and side wall 75 equals the length of described nano wire 733.The material of described grid is metal or polysilicon.Described first Semiconductor substrate is silicon substrate.The material silicon of source electrode, drain electrode and nano wire, and in described source electrode and drain electrode, there is Doped ions.Buried regions is silicon oxide layer.
The related content forming related structure and material in the method for nano-wire field effect transistor can be incorporated herein, and does not repeat at this.
The nano-wire field effect transistor of the technical program, shortens the length of nano wire relative to prior art, can reduce the series resistance between source electrode and drain electrode, improves the performance of device.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (15)
1. form a method for nano-wire field effect transistor, it is characterized in that, comprising:
SOI substrate is provided, described SOI substrate comprises the first Semiconductor substrate, the buried regions be positioned in described first Semiconductor substrate, the second Semiconductor substrate be positioned on described buried regions;
Graphically described second Semiconductor substrate forms source region, drain region and nano wire;
Remove the buried regions of described nano wire inferior portion thickness, to form groove, make nano wire be suspended in groove;
The side in the region that the second Semiconductor substrate after graphical surrounds with residue buried regions forms side wall;
Grid structure is formed between the side wall and the side wall of side, drain region of side, described source region, described grid structure comprises grid and the gate dielectric layer between described grid and nano wire, and on nano wire bearing of trend, the width sum of grid and side wall equals the length of described nano wire;
Ion doping is carried out to described source region and drain region, forms source electrode and drain electrode;
Wherein, described graphically described second Semiconductor substrate forms source region, the method for drain region and nano wire comprises:
Described second Semiconductor substrate forms hard mask layer;
Graphical described hard mask layer, defines the position of nano wire;
Form first medium layer, cover described patterned hard mask layer and described second Semiconductor substrate;
Graphical described first medium layer, defines the position of source region and drain region;
With described patterned hard mask layer, patterned first medium layer for mask, etch described second Semiconductor substrate and form source region, drain region and nano wire and the buried regions of the described nano wire inferior portion thickness of etching removal;
Remove the patterned hard mask layer be positioned on described nano wire;
Described side wall is also positioned at the side of described patterned first medium layer;
The formation method of described side wall comprises:
Form second dielectric layer, cover described patterned first medium layer, remaining buried regions;
Second dielectric layer described in dry etching forms side wall;
Remove the second dielectric layer under described nano wire.
2. the method forming nano-wire field effect transistor as claimed in claim 1, it is characterized in that, described hard mask layer is silicon nitride layer.
3. the method forming nano-wire field effect transistor as claimed in claim 1, it is characterized in that, described first medium layer is silicon oxide layer.
4. the method forming nano-wire field effect transistor as claimed in claim 1, is characterized in that, after removing the patterned mask layer be positioned on described nano wire, also comprises: in hydrogen atmosphere, carry out annealing process to described nano wire before forming side wall.
5. the method forming nano-wire field effect transistor as claimed in claim 1, is characterized in that, the second dielectric layer under utilizing isotropic dry etch or wet etching to remove described nano wire.
6. the method forming nano-wire field effect transistor as claimed in claim 1, it is characterized in that, described second dielectric layer is single layer structure or laminated construction.
7. the method forming nano-wire field effect transistor as claimed in claim 6, it is characterized in that, the second dielectric layer of described single layer structure is silicon oxide layer or silicon nitride layer.
8. the method forming nano-wire field effect transistor as claimed in claim 1, is characterized in that, after formation grid structure, before carrying out ion doping, also comprises described source region and drain region:
Remove patterned mask layer on described source region, on drain region.
9. the as claimed in claim 8 method forming nano-wire field effect transistor, is characterized in that, utilizes wet etching to remove patterned mask layer on described source region, on drain region.
10. the method forming nano-wire field effect transistor as claimed in claim 1, is characterized in that, the method forming grid structure comprises:
Form gate dielectric layer and conductive layer successively, cover patterned mask layer on described side wall, source region and drain region, remaining buried regions and nano wire;
Carry out planarization to described conductive layer and gate dielectric layer and form grid structure, the end face of described grid structure is equal with the end face of described side wall.
11. methods forming nano-wire field effect transistor as claimed in claim 10, it is characterized in that, described flattening method is chemical mechanical milling tech.
12. methods forming nano-wire field effect transistor as claimed in claim 10, it is characterized in that, the material of described conductive layer is metal or polysilicon.
13. methods forming nano-wire field effect transistor as claimed in claim 1, it is characterized in that, described first Semiconductor substrate is silicon substrate.
14. methods forming nano-wire field effect transistor as claimed in claim 1, it is characterized in that, described second Semiconductor substrate is silicon substrate.
15. methods forming nano-wire field effect transistor as claimed in claim 1, it is characterized in that, described buried regions is silicon oxide layer.
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| CN104658897B (en) * | 2013-11-19 | 2017-06-13 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
| CN104752200A (en) * | 2013-12-27 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Transistor and manufacturing method thereof |
| CN116825818A (en) * | 2015-11-12 | 2023-09-29 | 蓝枪半导体有限责任公司 | Grid full-cladding nanowire field effect transistor device |
| US12040395B2 (en) | 2019-12-13 | 2024-07-16 | Intel Corporation | High voltage extended-drain MOS (EDMOS) nanowire transistors |
| CN111415902B (en) * | 2020-03-05 | 2023-07-14 | 中国科学院微电子研究所 | Metal nanostructure, manufacturing method thereof, electronic device, electronic equipment |
| CN114914292A (en) * | 2020-05-11 | 2022-08-16 | 北京华碳元芯电子科技有限责任公司 | Transistor |
| CN113594006B (en) * | 2021-07-29 | 2022-08-30 | 中国科学院上海微系统与信息技术研究所 | Vacuum channel transistor and manufacturing method thereof |
| CN114023648B (en) * | 2021-10-18 | 2023-08-22 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing trench gate semiconductor device |
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