CN205749689U - A kind of test structure of fin formula field effect transistor parasitic capacitance - Google Patents
A kind of test structure of fin formula field effect transistor parasitic capacitance Download PDFInfo
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- CN205749689U CN205749689U CN201620502335.8U CN201620502335U CN205749689U CN 205749689 U CN205749689 U CN 205749689U CN 201620502335 U CN201620502335 U CN 201620502335U CN 205749689 U CN205749689 U CN 205749689U
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- 238000012360 testing method Methods 0.000 title claims abstract description 50
- 230000005669 field effect Effects 0.000 title claims abstract description 29
- 230000003071 parasitic effect Effects 0.000 title claims abstract description 27
- 238000002955 isolation Methods 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 230000004888 barrier function Effects 0.000 claims abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052681 coesite Inorganic materials 0.000 claims description 9
- 229910052906 cristobalite Inorganic materials 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 9
- 229910052682 stishovite Inorganic materials 0.000 claims description 9
- 229910052905 tridymite Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 238000005530 etching Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 230000008859 change Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000000994 depressogenic effect Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
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- 230000008021 deposition Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Abstract
This utility model provides the test structure of a kind of fin formula field effect transistor parasitic capacitance, described test structure includes: semi-conductive substrate, at least one fin structure being formed in described Semiconductor substrate, it is positioned at the shallow channel isolation area of described semiconductor substrate surface, grid region across described fin structure, it is formed at above described fin structure and is positioned at source region and the drain region of both sides, described grid region, described grid region, source region and drain region are drawn by grid, source, drain electrode respectively, are also formed with insulating barrier between described grid, source, drain electrode；Wherein, described fin structure be mid portion be the fin structure of dead slot, be filled with the insulant of shallow channel isolation area in described dead slot.By test structure described in the utility model, solve conventional test architectures of the prior art and cannot separate direct overlap capacitance (direct overlap capacitance:Cdo) and the problem of outward flange electric capacity (outer fringing capacitance:Cof).
Description
Technical field
This utility model relates to fin formula field effect transistor, particularly relates to a kind of fin formula field effect transistor parasitic capacitance
Test structure.
Background technology
Along with developing rapidly of semiconductor fabrication, semiconductor device is towards higher component density and higher
The direction of integrated level is developed.Transistor is currently widely used as most basic semiconductor device, therefore along with quasiconductor
The component density of device and the raising of integrated level, the grid size of transistor is the most shorter and shorter.But, the grid size of transistor
Shorten and transistor can be made to produce short-channel effect (short channel effect), and then produce leakage current, final impact half
The electric property of conductor device.
In order to overcome the short-channel effect of transistor, suppressing leakage current, prior art proposes fin formula field effect transistor
(Fin FET).Fin formula field effect transistor presents good grid controlling in terms of raceway groove control, and due to superior
Static control ability makes transistor develop towards the smaller szie less than 20nm, and plough groove type contact (Trench contact) is also
It is used on smaller size of fin formula field effect transistor.
When plough groove type contact (Trench contact) is applied on the fin formula field effect transistor device of 16nm, its edge
Parasitic capacitance substantially exceeds compared to planar structure a lot.Owing to parasitic capacitance has negative in the performance of fin formula field effect transistor
Face rings, and the even parasitic capacitance in fin formula field effect transistor is excessive, then the response speed that can cause semiconductor device is relatively low,
The problems such as power consumption increase, therefore, carry out parasitic capacitance for fin formula field effect transistor and assess the performance to device and have very
Important meaning.The parasitic capacitance of fin formula field effect transistor mainly includes direct overlap capacitance (direct overlap
Capacitance:Cdo), outward flange electric capacity (outer fringing capacitance:Cof) and inward flange electric capacity
(inner fringingcapacitance:Cif), but owing to the low passage of fin formula field effect transistor adulterates, inner edges electricity
Hold Cif to reduce, therefore inner edges electric capacity Cif is negligible when assessing parasitic capacitance, only need to be to direct overlap capacitance Cdo with outer
Edge capacitance Cof is estimated, but conventional test architectures of the prior art and method are difficult to isolate this two electric capacity.
In consideration of it, on being necessary that the test structure designing a kind of new fin formula field effect transistor parasitic capacitance is in order to solve
State technical problem.
Utility model content
The shortcoming of prior art in view of the above, the purpose of this utility model is to provide a kind of fin field effect crystal
The test structure of pipe parasitic capacitance, is used for solving conventional test architectures of the prior art and method cannot separate outward flange electric capacity
Cof and the problem of direct overlap capacitance Cdo.
For achieving the above object and other relevant purposes, this utility model provides a kind of fin formula field effect transistor parasitism electricity
The test structure held, described test structure includes:
Semi-conductive substrate；
At least one fin structure being formed in described Semiconductor substrate；
It is positioned at the shallow channel isolation area of described semiconductor substrate surface；
Grid region across described fin structure；
It is formed at above described fin structure and is positioned at source region and the drain region of both sides, described grid region；
Described grid region, source region and drain region are drawn by grid, source, drain electrode respectively；
It is also formed with insulating barrier between described grid, source, drain electrode；
Wherein, described fin structure be mid portion be the fin structure of dead slot, be filled with shallow channel isolation area in described dead slot
Insulant.
Preferably, the height of described dead slot is the height of fin structure.
Preferably, described dead slot is inverted trapezoidal.
Preferably, the distance that described grid and source, drain junctions divide is L, and described L is in the range of 10～50nm.
Preferably, the width in a length of grid region on the long base of described inverted trapezoidal with 2*L's and.
Preferably, the height of described fin structure is 30～50nm.
Preferably, the width of described fin structure is 6～12nm
Preferably, the quantity of described fin structure is 4.
Preferably, described grid region includes:
Formed and the dielectric layer on the insulant of described shallow channel isolation area；
It is positioned at the work-function layer of described dielectric layer surface；
And it is positioned at the metal level on described work-function layer surface.
Preferably, described insulant is SiO2.
As it has been described above, the test structure of a kind of fin formula field effect transistor parasitic capacitance of the present utility model, have following
Beneficial effect: by test structure described in the utility model, described grid and source, the connecting portion of leakage the two poles of the earth fin structure will be connected
Divide and etch away, form spill fin structure, and make the depressed area of described spill fin structure by institute by forming shallow channel isolation area
Stating oxide insulating layer to fill, eliminate described direct overlap capacitance Cdo with this, test obtains outward flange electric capacity Cof；And by inciting somebody to action
Above-mentioned test structure contrasts with the test result of conventional test architectures, it is achieved by described direct overlap capacitance Cdo and outside
Edge electric capacity Cof separates, and is used for solving conventional test architectures of the prior art and cannot separate direct overlap capacitance Cdo and outward flange
The problem of electric capacity Cof.
Accompanying drawing explanation
Fig. 1 is shown as the structural representation of prior art test structure.
Fig. 2 is shown as described in prior art testing the structure profile along CC ' direction.
Fig. 3 is shown as the structural representation of this utility model test structure.
Fig. 4 is shown as the test structure described in the utility model profile along DD ' direction.
Fig. 5 to Figure 12 is shown as the making step of test structure described in the utility model.
Element numbers explanation
1 substrate
2 oxide layers
3 cushions
4 fin structures
5 second oxide layers
6 shallow channel isolation areas
7 source regions
8 grid regions
81 dielectric layers
82 work-function layer
83 metal levels
9 drain regions
10 source electrodes
11 gate electrodes
12 drain electrodes
13 insulating barriers
Detailed description of the invention
Below by way of specific instantiation, embodiment of the present utility model being described, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages of the present utility model and effect easily.This utility model can also be by additionally
Different detailed description of the invention is carried out or applies, the every details in this specification can also based on different viewpoints with should
With, under without departing from spirit of the present utility model, carry out various modification or change.
Refer to Fig. 1 to Figure 12.It should be clear that structure depicted in this specification institute accompanying drawings, ratio, size etc., the most only use
To coordinate the content disclosed in description, understand for those skilled in the art and read, being not limited to this practicality new
The enforceable qualifications of type, therefore do not have technical essential meaning, the modification of any structure, the change of proportionate relationship or size
Adjustment, under not affecting effect that this utility model can be generated by and the purpose that can reach, all should still fall new in this practicality
In the range of technology contents disclosed in type obtains and can contain.Meanwhile, in this specification cited as " on ", D score, " left ",
The term of " right ", " middle " and " one " etc., is merely convenient to understanding of narration, and it is enforceable to be not used to limit this utility model
Scope, being altered or modified of its relativeness, changing under technology contents without essence, enforceable when being also considered as this utility model
Category.
Referring to Fig. 3 to Figure 12, described test structure includes:
Semi-conductive substrate 1；
At least one fin structure 4 being formed in described Semiconductor substrate 1；
It is positioned at the shallow channel isolation area 6 on described Semiconductor substrate 1 surface；
Grid region 8 across described fin structure 4；
It is formed at above described fin structure 4 and is positioned at source region 7 and the drain region 9 of both sides, described grid region 8；
Described grid region 8, source region 7 and drain region 9 are drawn by grid, source, drain electrode respectively；
Insulating barrier 13 it is also formed with between described grid, source, drain electrode；
Wherein, described fin structure 4 is the fin structure of dead slot for mid portion, is filled with shallow channel isolation area in described dead slot
Insulant.
It should be noted that described grid region 8 includes being formed and the dielectric layer 81 on the insulant of described shallow channel isolation area,
It is positioned at the work-function layer 82 on described dielectric layer 81 surface, and is positioned at the metal level 83 on described work-function layer 82 surface.
Concrete, the distance that described grid and source, drain junctions divide is L, and described L is in the range of 10～50nm.
Concrete, the height of described dead slot is the height of fin structure, it is preferable that described dead slot is inverted trapezoidal, described ladder
The width in a length of grid region on the long base of shape with 2*L's and.
Concrete, the quantity of described fin structure is 4, and the width of described fin structure is 6～12nm, the height of described fin structure
Degree is 30～50nm.
Concrete, described insulant is SiO2.
It should be noted that the application is by etching connecting the described grid coupling part with source, leakage the two poles of the earth fin structure
Fall, form the fin structure that mid portion is dead slot, and make described dead slot be filled by described SiO2 by forming shallow channel isolation area,
Isolate described grid region and source region, grid region and drain region, eliminate described direct overlap capacitance Cdo with this.
Refer to Fig. 1 to Figure 12 below making step and the method for testing of test structure described in the utility model are had
Body explanation.
Step 1 a, it is provided that substrate 1, forms an oxide layer 2 at described substrate surface；
Step 2, forms cushion 3 on described oxide layer 2 surface；
Step 3, performs etching the structure of described step 2, forms fin structure 4；
Step 4, the body structure surface in described step 3 forms the second oxide layer 5；
Step 5, is filled with the structure of described step 4, forms shallow channel isolation area 6；
Step 6, performs etching described shallow channel isolation area 6 and the second oxide layer 5, exposes described oxide layer 2 He
Cushion 3, is etching further to described structure afterwards, forms the fin structure 4 of predetermined altitude；
Step 7, removes oxide layer 2 and the cushion 3 on described fin structure 4 surface, forms source, leakage, grid over the structure
District, and on described source, leakage, grid region, form source, leakage, gate electrode；
Step 8, the body structure surface in described step 7 forms insulating barrier 13.
Concrete, the material of substrate described in step 1 be the one in Si, SiGe, SiC, SOI or III-V compound or
Multiple；Using chemical vapor deposition method to form described oxide layer in step 1, described oxide layer is SiO2 layer.
Concrete, step 2 utilize chemical vapor deposition method form described cushion, cushion is SiN layer.
Concrete, step 3 use dry etch process form described fin structure, etching gas is Cl2 and HBr, is carving
During erosion, it will usually add the O2 of low discharge, partly in order to generate silicon oxide at sidewall thus increase the guarantor to sidewall
Protect, be on the other hand to improve the ratio of the selection to base oxide；The material of described fin structure is SiGe, Ge or III-V
One or more in compound.
During it should be noted that described fin structure is performed etching by step 3, on described cushion, first coat photoetching
Glue, and carry out graphical treatment, then use etching technics to form described fin structure.Fig. 9 is the EE ' direction of structure described in Fig. 8
Profile, as it is shown in figure 9, described fin structure mid portion is etched away, formed in the middle of be the fin structure of inverted trapezoidal dead slot.
Needing further exist for explanation, the mid portion that described fin structure etches away is inverted trapezoidal, the height of described inverted trapezoidal
Degree is the height of fin structure；The width in the longer a length of 2*L+ grid region, base of described inverted trapezoidal.
It should be noted that the height of described fin structure is 30～50nm, the width of described fin structure is 6～12nm.
Concrete, described in step 4, the second oxide layer is SiO2 layer, and forming the second oxide layer is to protect fin structure to exist
Step 5 use when flowing chemical vapor deposition method oxidized.
Concrete, step 5 use flowing chemical vapor deposition method deposition SiO2 form described shallow channel isolation area, it
With chemical mechanical milling tech, described shallow channel isolation area is planarized afterwards.
Concrete, when described shallow channel isolation area is etched by step 6 further, first it is coated with on the dead slot of described fin structure
Cover photoresist, more described shallow channel isolation area is performed etching, form the fin structure of predetermined altitude.
It should be noted that the purpose coating photoresist on the dead slot of described fin structure be protection dead slot in insulation material
Material is not etched, so that the height of insulant is as the height of described fin structure in dead slot.
Needing further exist for explanation, Figure 12 is that structure described in Figure 11 is along the profile in FF ' direction.As shown in figure 12, by
The fin structure formed in the application be centre be the fin structure of inverted trapezoidal dead slot, so when forming shallow channel isolation area, institute
The inverted trapezoidal dead slot stating fin structure is filled by SiO2, then during etching further to fin structure, in dead slot avoided by coating photoresist
SiO2 is etched, and the SiO2 in dead slot plays isolation grid region and source region, grid region and the effect in drain region, eliminates the most overlapping electricity with this
Hold Cdo.
Concrete, described grid region 8 includes being formed and the dielectric layer 81 on the insulant of described shallow channel isolation area, is positioned at institute
Give an account of the work-function layer 82 on electric layer 81 surface, and be positioned at the metal level 83 on described work-function layer 82 surface.
Refer to Fig. 2 and Fig. 4, the AB two ends testing structure described in Fig. 2 are carried out parasitic capacitance measurement, the parasitic electricity recorded
Hold for direct overlap capacitance Cdo and outward flange electric capacity Cof；Afterwards the AB two ends testing structure described in described Fig. 4 are being posted
Raw capacitance measurement, the parasitic capacitance recorded is outward flange electric capacity Cof, finally the measurement result testing structure described in Fig. 2 is deducted
Test the measurement result of structure described in Fig. 4, i.e. obtain direct overlap capacitance Cdo, be achieved in direct overlap capacitance Cdo and outside
The separation of edge electric capacity Cof.
In sum, the test structure of a kind of fin formula field effect transistor parasitic capacitance of the present utility model, have following
Beneficial effect: by test structure described in the utility model, described grid and source, the connecting portion of leakage the two poles of the earth fin structure will be connected
Divide and etch away, form spill fin structure, and make the depressed area of described spill fin structure by institute by forming shallow channel isolation area
Stating oxide insulating layer to fill, eliminate described direct overlap capacitance Cdo with this, test obtains outward flange electric capacity Cof；And by inciting somebody to action
Above-mentioned test structure contrasts with the test result of conventional test architectures, it is achieved by described direct overlap capacitance Cdo and outside
Edge electric capacity Cof separates, and is used for solving conventional test architectures of the prior art and cannot separate direct overlap capacitance Cdo and outward flange
The problem of electric capacity Cof.
Above-described embodiment only illustrative principle of the present utility model and effect thereof are new not for limiting this practicality
Type.Above-described embodiment all can be carried out by any person skilled in the art under spirit and the scope of the present utility model
Modify or change.Therefore, art has usually intellectual such as without departing from the essence disclosed in this utility model
All equivalences completed under god and technological thought are modified or change, and must be contained by claim of the present utility model.
Claims (10)
1. the test structure of a fin formula field effect transistor parasitic capacitance, it is characterised in that described test structure includes:
Semi-conductive substrate；
At least one fin structure being formed in described Semiconductor substrate；
It is positioned at the shallow channel isolation area of described semiconductor substrate surface；
Grid region across described fin structure；
It is formed at above described fin structure and is positioned at source region and the drain region of both sides, described grid region；
Described grid region, source region and drain region are drawn by grid, source, drain electrode respectively；
It is also formed with insulating barrier between described grid, source, drain electrode；
Wherein, described fin structure be mid portion be the fin structure of dead slot, be filled with the exhausted of shallow channel isolation area in described dead slot
Edge material.
The test structure of fin formula field effect transistor parasitic capacitance the most according to claim 1, it is characterised in that described sky
The height of groove is the height of fin structure.
The test structure of fin formula field effect transistor parasitic capacitance the most according to claim 1, it is characterised in that described sky
Groove is inverted trapezoidal.
The test structure of fin formula field effect transistor parasitic capacitance the most according to claim 3, it is characterised in that described grid
The distance that pole and source, drain junctions divide is L, and described L is in the range of 10～50nm.
The test structure of fin formula field effect transistor parasitic capacitance the most according to claim 4, it is characterised in that described fall
The width in a length of grid region on trapezoidal long base with 2*L's and.
The test structure of fin formula field effect transistor parasitic capacitance the most according to claim 1, it is characterised in that described fin
The height of structure is 30～50nm.
The test structure of fin formula field effect transistor parasitic capacitance the most according to claim 1, it is characterised in that described fin
The width of structure is 6～12nm.
The test structure of fin formula field effect transistor parasitic capacitance the most according to claim 1, it is characterised in that described fin
The quantity of structure is 4.
The test structure of fin formula field effect transistor parasitic capacitance the most according to claim 1, it is characterised in that described grid
District includes:
Formed and the dielectric layer on the insulant of described shallow channel isolation area；
It is positioned at the work-function layer of described dielectric layer surface；
And it is positioned at the metal level on described work-function layer surface.
The test structure of fin formula field effect transistor parasitic capacitance the most according to claim 1, it is characterised in that described
Insulant is SiO2.
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| CN201620502335.8U CN205749689U (en) | 2016-05-27 | 2016-05-27 | A kind of test structure of fin formula field effect transistor parasitic capacitance |
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| CN201620502335.8U CN205749689U (en) | 2016-05-27 | 2016-05-27 | A kind of test structure of fin formula field effect transistor parasitic capacitance |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108899320A (en) * | 2018-07-20 | 2018-11-27 | 上海华力微电子有限公司 | A kind of MOSFET gate oxide capacitance calibration structure |
| WO2022077979A1 (en) * | 2020-10-16 | 2022-04-21 | 长鑫存储技术有限公司 | Parasitic capacitance measurement method, and memory and readable storage medium |
| US11378611B1 (en) | 2020-10-16 | 2022-07-05 | Changxin Memory Technologies, Inc. | Measurement method for contact resistance of transistor test device and computer-readable medium |
| US11867745B2 (en) | 2020-10-16 | 2024-01-09 | Changxin Memory Technologies, Inc. | Parasitic capacitance detection method, memory and readable storage medium |
-
2016
- 2016-05-27 CN CN201620502335.8U patent/CN205749689U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108899320A (en) * | 2018-07-20 | 2018-11-27 | 上海华力微电子有限公司 | A kind of MOSFET gate oxide capacitance calibration structure |
| WO2022077979A1 (en) * | 2020-10-16 | 2022-04-21 | 长鑫存储技术有限公司 | Parasitic capacitance measurement method, and memory and readable storage medium |
| US11378611B1 (en) | 2020-10-16 | 2022-07-05 | Changxin Memory Technologies, Inc. | Measurement method for contact resistance of transistor test device and computer-readable medium |
| US11867745B2 (en) | 2020-10-16 | 2024-01-09 | Changxin Memory Technologies, Inc. | Parasitic capacitance detection method, memory and readable storage medium |
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