CN1032285C - Method for manufacturing semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device comprising the steps of: forming an insulating interlayer with an opening on a semiconductor substrate, forming a first metal layer and heat-treating it to fill the opening with metal, and forming a second metal layer on the first metal layer And heat treat it to make it planar. In another embodiment of the present invention, the metal used to form the metal layer is pure aluminum or aluminum alloy without silicon element. The advantages of the semiconductor wafer obtained according to the invention are that even if the contact hole has a large aspect ratio, it can be completely filled with metal, after patterning, there is no silicon deposition on its surface, and there are no aluminum peaks.

Description

Method for manufacturing semiconductor device

The present invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of forming a planarizing metal layer in a semiconductor device. The present invention is an improvement upon the subject matter of the present inventor's co-pending US patent application, Ser. No. 07/585,218, filed September 19, 1990, the disclosure of which is incorporated herein by reference.

With the development of semiconductor device manufacturing technology towards ultra-large-scale integration (ULSI), the metallization process increasingly determines the yield, performance (such as: operating speed) and reliability of the device. Therefore, people regard the metallization process as a semiconductor device. The most important aspect of manufacturing technology. Metal step coverage is not a very good option for lower density prior art semiconductor devices because of their larger geometry, smaller aspect ratio (height to width ratio) of contact holes, and shallower steps. Important issues. However, as the integration density of semiconductor devices increases, the contact holes have become very small, and at the same time the doped layer formed on the surface of the semiconductor substrate has become very thin. As far as the existing high-density semiconductor devices are concerned, due to the comprehensive reasons that the aspect ratio of the contact hole becomes larger and the step depth becomes larger and larger, in order to achieve the standards of high-speed performance, high yield, and high reliability of semiconductor devices Design goals, it is necessary to improve the traditional aluminum (Al) metallization process. More specifically, the conventional aluminum metallization process used in the fabrication of existing high-density semiconductor devices has brought about problems such as: high contact hole aspect ratio and poor step coverage of sputtered aluminum Reliability reduction and aluminum interconnect failure; increased contact resistance caused by silicon (Si) deposition; and reduced shallow junction characteristics caused by aluminum peaking (Al spking).

Various new processes have been proposed to overcome these problems in conventional aluminum metallization processes. For example, the following processes have been proposed to prevent semiconductor reliability degradation due to aluminum interconnect failures due to large contact hole aspect ratios and poor step coverage of sputtered aluminum during aluminum metallization And caused.

Japanese Patent Application Publication No. 62-132348 of Yukiyosu Sugano et al. discloses a method for improving the uniformity of a film formed on a steep step of a semiconductor device, which method includes forming a film on a steep step (which is located on a semiconductor substrate) A metal wiring layer, which is then thermally fused in such a way as to planarize the metal wiring layer. Japanese patent application of Shinpei Iijma et al., Publication No. 63-99546, discloses a method for improving wiring reliability and capable of forming multilayer interconnections, wherein metal wiring layers are formed by heating and melting them in a Contact holes and steps are formed on the substrate. In particular, Shinpei Iijma et al. have proposed a method of manufacturing a semiconductor device, the method comprising the steps of: forming a plurality of devices on a semiconductor substrate, depositing an insulating layer on the plurality of devices, forming an insulating layer in the insulating layer A contact hole leading to the preset position of the device, a titanium nitride film is formed on the surface of the insulating layer and the contact hole, a metallized wiring layer is deposited on the entire surface of the titanium nitride film, and then heated to make it Melting and flowing to planarize the surface of the metal layer, and etching the metal surface and the iron nitride film according to a pre-designed wiring pattern to form at least a first wiring layer.

The Japanese patent application of Masahiro Shimizu et al., Publication No. 62-10341, proposes a method that can prevent wiring disconnection and improve the reliability of semiconductor devices. Above) forming an aluminum conductive film with good coverage.

In particular, Masahiro Shimizu et al. disclose a method of fabricating a semiconductor device comprising: coating a silicon substrate with a solution containing liquid aluminum (or an aluminum compound), and then curing it to form an aluminum conductive film.

According to all the above-mentioned methods, the contact holes can be filled by melting aluminum or aluminum alloy and reflowing it. In summary, in the reflow step, the aluminum or aluminum alloy metal layer is heated above its melting point, and as a result, the molten metal will flow into the contact hole and fill it. This reflow step has the following disadvantages and deficiencies. First, the semiconductor wafer must be positioned horizontally so that the contact holes can be properly filled with flowing, molten metal material. Second, the liquid metal layer that flows into the contact holes has a low surface tension, so when solidified, it may shrink or bend, exposing the underlying semiconductor material. Further, the temperature of the heat treatment cannot be precisely controlled, so that it is difficult to produce the desired result any more. Furthermore, although these methods can fill the contact hole with molten metal of the metal layer, other parts of the metal layer (outside the contact hole) may become rough, compromising the subsequent protective coating process. Therefore, to smooth or planarize these rough portions of the metal layer, a second metal layer coating process may be necessary.

It is known that a barrier layer can be formed in a contact hole formed on a semiconductor wafer to improve the reliability of a semiconductor by preventing the degradation of the shallow junction characteristics caused by the aluminum peak. For example, U.S. Patent No. 4,897,709 to Natsuki Yokoyama et al. describes a semiconductor device having a titanium nitride film (barrier layer) formed on a contact hole to prevent contact between the metal wiring layer and the semiconductor substrate. reaction between. The titanium nitride film can be formed by a low-pressure CVD method which can be realized by a cold-type CVD apparatus. The resulting membranes have very good properties, providing good step coverage of relatively fine pores with large aspect ratios. After the titanium nitride film was formed, a metal wiring layer was formed using aluminum alloy by the sputtering method.

U.S. Patent No. 4,970,176 to Clarence J. Tracy et al. discloses a multilayer metallization process that can replace molten aluminum or aluminum alloys for filling contact holes and can improve metal step coverage. According to the above-mentioned patent, a first part of a predetermined thickness of the metal layer is deposited on a semiconductor wafer at a low temperature; reflow. The reflow of the metal layer occurs through grain size growth, recrystallization, and bulk diffusion.

One et al. have disclosed that when the temperature of the semiconductor substrate is higher than 500°C, the liquidity of aluminum-silicon will suddenly increase (see Journal of the VMIC Conference on June 11-12, 1990, pages 76-82, Hisako Paper by One et al.). According to the research results of One et al., the stress of Al-1%Si film will change suddenly when it is close to 500℃, and at this temperature, the stress decay of Al-1%Si film will appear rapidly. Furthermore, in order to satisfactorily fill the contact holes, the temperature of the semiconductor substrate must be maintained between 500°C and 550°C. This mechanism is different from the mechanism in Tracy et al. (4,970,176) that promotes reflow of the metal layer.

One of the inventors of the present application has a previous pending item in the United States Patent and Trademark Office (U.S.P.T.O) entitled "A Method for Forming a Metal Layer in a Semiconductor Device" ("AMethed for Forming a Metal Layer in a Semiconductor Device") ”) invention. The invention relates to a method of forming a metal wiring layer passing through a contact hole in a semiconductor device, the method comprising the steps of: depositing metal at a low temperature (below 200°C), and then depositing metal at a temperature equal to the melting point of the deposited metal material The deposited metal material is heated within a range between 80% and its melting point.

Fig. 1A, 1B, 1C have provided a kind of method of forming metal layer according to above-mentioned invention, with reference to Fig. 1A, it has provided the process of forming the first metal layer, and contact hole 2 is formed on semiconductor substrate 10. Then, the substrate is placed in a sputtering reaction chamber (not shown in the figure), in this reaction chamber, the first metal layer 4 is formed by depositing metal (Al or Al alloy) at a temperature of 200° C. Or below 200°C, and under a predetermined degree of vacuum. Layer 4 has a polycrystalline grain structure.

Fig. 1 B has described the method for filling contact hole, with reference to Fig. 1 B, the substrate structure obtained by the previous process is moved to another sputtering reaction chamber (not shown in the figure), then, without opening vacuum, temperature is 550 °C, heat for at least 2 minutes to allow the metal to fill the contact holes. At the same time, the pressure of the reaction chamber is preferably as low as possible so that the aluminum atoms have a higher surface free energy. In this way, metal can more easily fill the contact holes. Parameter 4a represents the metal filling the contact hole 2 .

The heat treatment temperature range in the process shown in Figure 1B must be between 80% and between the melting point of the metal and varies depending on the particular aluminum alloy or aluminum used.

Since the heat treatment temperature of the metal layer is lower than the melting point of aluminum, 660° C., the metal layer does not melt. For example, at 550°C, when heat treatment at a higher temperature, these deposited aluminum atoms sputtered below 150°C do not melt but migrate. This migration is increased when the surface area is inhomogeneous or multi-grained because of the increased energy of those surface atoms that are not in full contact with surrounding atoms. Thus, the initially sputtered, multi-grained layer increases the migration of atoms at the thermal treatment level.

Figure 1C shows the process of forming the second metal layer 5, in particular, the second metal layer 5 is formed by depositing the rest of the required full metal layer thickness, and its deposition temperature depends on the reliability of the desired semiconductor device. sex to choose. This completes the formation of the entire (composite) metal layer.

According to the above method, by using the same sputtering equipment as the conventional thermal deposition method, and gradually cooling the deposited metal, it is easy to completely fill the contact hole with the metal. Thus, even a contact hole with a large aspect ratio can be completely filled.

However, when a void is formed in the contact hole or when the step coverage of the metal layer is insufficient, the contact hole cannot be filled although the semiconductor wafer deposited with the metal layer can be maintained at a predetermined temperature and vacuum level. Further, although a second metal layer can be formed subsequently on the semiconductor wafer on which the initial metal layer has been deposited, good step coverage of the contact hole cannot be guaranteed, so the reliability of the manufactured semiconductor device will be reduced.

In the earliest stage of silicon technology, the contact structure used was to deposit pure aluminum directly on silicon. However, aluminum-silicon contacts exhibit some poor contact characteristics, such as junction spiking during pouring. This sintering step is performed after the contact metal film has been deposited and patterned. In the case of an aluminum-silicon contact, this sintering causes the aluminum to react with the native oxide layer formed on the silicon surface. When aluminum reacts with a thin _SiO2 layer, _Al2O3 is produced, and if in a good ohmic contact _, this native oxide layer is eventually consumed completely. Aluminum then diffuses to the silicon surface through the resulting Al ₂ O ₃ layer, forming an intimate metal-silicon contact. Aluminum must diffuse through _{the Al2O3} layer onto the remaining _SiO2 . As the thickness of the Al ₂ O ₃ layer increases, it takes longer for Al to penetrate it. So _, if the native oxide layer is too thick, the _Al2O3 layer will eventually become too thick for aluminum to diffuse through it. In this case, not all the _SiO2 can be consumed and a bad ohmic contact will result. The rate of Al penetration into Al ₂ O ₃ is a function of temperature. For the allowable sintering temperature and sintering times, the thickness of Al ₂ O ₃ should be in the range of 5-10 angstroms. Since the maximum Al ₂ O ₃ thickness is of the same order of magnitude as the consumed natural oxide layer thickness, the upper limit of the allowable thickness of the natural oxide layer should be determined. The longer the silicon surface is exposed to an oxygen-containing environment, the thicker the native oxide layer becomes. Therefore, in most contact layer processes, the surface cleaning procedure is done before placing the wafer into the deposition chamber for metal deposition.

Between 450°C and 500°C in contact with the alloy temperature, aluminum absorbs 0.5% to 1% of silicon. If a layer of pure aluminum is heated to 450°C and a source of silicon is provided, then in solution, the aluminum will absorb silicon until the silicon concentration reaches 0.5 wt%. The semiconductor substrate acts as a source of this silicon, and when the temperature rises, the silicon from the substrate diffuses into the aluminum. If there is a large amount of aluminum, a large amount of silicon from below the Al-Si interface will diffuse into the aluminum film. At the same time, aluminum from the aluminum film moves rapidly to fill the voids formed by the free silicon. If the aluminum penetration depth is greater than the PN-junction depth below the contact surface, then the junction will exhibit a large leakage current and even become a short circuit. This phenomenon is called PN junction peaking.

In order to alleviate the peak problem of the PN junction at the contact surface, silicon is added to the aluminum film during aluminum deposition. Aluminum-silicon alloys (silicon point 1.0 weight percent) have been widely used in the manufacture of integrated circuit contact surfaces and internal connections. Using aluminum-silicon alloys instead of pure aluminum can alleviate the junction peak problem, but unfortunately, this will cause another problem. one question. More specifically, during the cooling period of the annealing process, the solubility of silicon in aluminum decreases with decreasing temperature. So aluminum becomes supersaturated with respect to silicon, which will cause agglomeration and precipitation of silicon from the aluminum-silicon solution. This kind of Al-SiO ₂ interface and Al-Si interface that precipitates in the contact surface will appear. If these precipitates form on the contact interface to generate n ⁺ Si, this can lead to an undesired increase in contact resistance. In addition, where the n ⁺ Si precipitation is greater than about 1.5μ, a large flux divergence (flwx-divergence) will be generated in the current. This will lead to early conductor failure due to electromigration-induced open-circuit conditions.

Figure 2 depicts the formation of silicon deposits on the surface of a semiconductor substrate after metallization. Obviously, these silicon precipitates should be eliminated. So far, silicon deposits can only be removed by sanding, overetching or wet etching, or by using etchant containing groups that remove the deposits from the substrate.

However, when the metal layer is deposited at high temperature, the silicon precipitate is not easily removed. When overetching is used to remove silicon deposits, its patterns are transferred to the base layer, and these patterns remain after the overetch is complete. Thus, the surface quality and appearance of the semiconductor substrate are still poor.

Based on the above reasons, there is a need for a method for forming a planar metal wiring layer in a semiconductor device, which can overcome all the above-mentioned shortcomings and deficiencies in the prior art processes. The present invention is aimed at and can satisfy this requirement.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an improved method of forming a metal wiring layer in a semiconductor device having a contact hole formed in a semiconductor substrate. The method includes the steps of depositing a metal and then completely filling the contact hole to obtain a reliable metal wiring layer.

Another object of the present invention is to provide an improved method of forming a metal layer for a metal wiring pattern without any silicon precipitation in subsequent processes.

According to the present invention, there is provided a method of manufacturing a semiconductor device, the method comprising the steps of: forming an insulating interlayer on a semiconductor substrate; providing an opening formed on the semiconductor substrate on the insulating interlayer; forming a first a metal layer; heat treating the first metal layer to fill the opening with the metal; forming a second metal layer on the first metal layer and then heat treating the second metal layer to planarize the layer.

The first metal layer is formed by depositing a metal such as aluminum or an aluminum alloy at a low temperature under vacuum conditions. Suitable aluminum alloys include, for example, Al-0.5% Cu, Al-1% Si, Al-1% Si-0.5% Cu, and the like. Depositing the first metal layer is preferably performed below 150°C. The lower the temperature, the easier it is for metal atoms to migrate to the opening during subsequent heat treatment. The thickness of the first metal layer is preferably one third to two thirds of the predetermined overall (composite) metal layer thickness (ie the sum of the first and second metal layer thicknesses).

After forming the first metal layer in vacuum, the metal layer is heat-treated without turning on the vacuum. This heat treatment is performed in an inert gas environment of 10 mTorr or below, or in a vacuum of 5×10 ^-7 Torr or below 5×10 ^-7 , using the gas conduction method or RTA (rapid thermal Annealing) is achieved by heating the semiconductor substrate, and its temperature range varies between 0.8Tm-Tm, preferably 500°C-550°C, where Tm is the melting point of the metal. The melting point of pure aluminum here is 660°C. For aluminum alloys, the eutectic point can be regarded as the melting point. The eutectic points of Al-1%Si alloy, Al-0.5%Cu alloy and Al-0.5%Cu-1%Si alloy are 577℃, 548℃ and 520℃ respectively. The heat treatment is carried out under the environment of inert gas (such as N ₂ , Ar) or a reducing gas (H ₂ ). When heat-treating the metal layer, metal atoms migrate toward the openings in order to reduce surface free energy. The result is that the opening is filled with metal. As the metal atoms migrate toward the opening, the metal surface area decreases. Then, the protruding portion of the metal layer disappears from the upper portion of the opening, and the entrance of the opening becomes larger. Therefore, when the second metal layer is deposited later, good step coverage of the metal layer can be obtained.

If the vacuum is turned on during _the above heat treatment step, it will cause oxidation to form an Al ₂ O ₃ film, which will prevent the migration of aluminum atoms to the opening at the above temperature, so that the opening cannot be completely _filled with metal, Obviously, this is not desired. When the hydrogen gas conduction method is used, the above heat treatment step preferably lasts 1-5 minutes, while when using RTA equipment, the heat treatment of the metal layer preferably requires several 20-30 second cycles, or lasts about 2 minutes.

Thereafter, the second metal layer is formed by depositing metal in the same manner as above for forming the first metal layer, but the temperature of the latter metal deposition is 350°C or lower. After the second metal layer is formed, the second metal layer is also heat-treated in the same manner as the heat treatment of the first metal layer.

All the above steps are carried out in an inert gas of 10 mTorr or below, or a vacuum of 5×10 ^-7 Torr or below 5×10 ^-7 Torr, and do not turn on the vacuum, which is the One of the most important features of an invention.

According to one embodiment of the present invention, after forming an opening in the semiconductor substrate, a diffusion barrier layer is formed on the entire surface of the semiconductor substrate (including the opening). The barrier layer consists of a transition metal or transition metal compound, such as titanium or titanium nitride.

When the wiring layer made of aluminum or aluminum alloy is connected to the surface of a doped thin layer region through a contact hole, and the heat treatment is completed, aluminum diffuses into the doped region and penetrates the PN-junction, which causes PN- junction peaks and may damage the PN-junction.

In order to prevent the reaction between aluminum and the semiconductor substrate, there has been proposed a method comprising providing a layer made of titanium nitride between a wiring layer made of aluminum or an aluminum alloy and the surface of the semiconductor substrate. barrier layer. For example, a technique for forming iron nitride by an active sputtering method is disclosed in J. Vac. Sci. Technol., A ₄ (4) (1986, pp. 1850-1854). US Patent No. 4,897,709 also discloses that a titanium nitride film excellent in thickness uniformity is used as a barrier layer on the inner surface of an ultrafine pore having a large aspect ratio.

In addition, Yoda Dakashi et al. have also proposed a method for manufacturing a semiconductor device, which includes the steps of: forming a double barrier layer to prevent the wiring layer from reacting with the semiconductor substrate or with the insulating layer on the inner surface of the contact hole, The contact hole is then filled with deposited metal (such as aluminum alloy) while heating the semiconductor substrate to a set temperature (see Japanese Patent Application No. 01-061557 filed on March 14, 1989 corresponding to South Korea Published Patent Application No. 90-15227).

Returning now to the present invention, a diffusion barrier layer can be readily formed on the inner surface of the contact openings of the present invention by using any of the techniques described above. The barrier layer preferably includes a first barrier layer (such as a titanium metal layer) and a second barrier layer (such as an iron nitride layer). The thickness of the first barrier layer is preferably 100-300 angstroms, and the thickness of the second barrier layer is preferably 200-1500 angstroms.

According to another aspect of the present invention, an anti-reflection layer is formed on the second metal layer to prevent harmful reflection in subsequent photolithography steps, thereby improving the reliability of the metal wiring layer.

Further, according to the present invention, there is provided a method of manufacturing a semiconductor device, the method comprising the steps of: providing a semiconductor wafer with openings above, forming a metal layer on the wafer, and then heat-treating the metal layer to The opening is filled, wherein the metal used for forming the metal layer is aluminum or aluminum alloy without silicon component. The opening of the present invention is preferably a contact hole with a step on its upper portion.

Preferred metals for carrying out the invention include, for example, pure aluminum, aluminum-copper and aluminum-titanium. In addition, the eutectic point of Al—Ti alloy is 665°C. According to a preferred embodiment of the present invention, the metal layer is formed by a method comprising the steps of: forming the first metal layer by depositing the first metal layer, performing heat treatment on the first metal layer, and then forming the first metal layer on the first metal layer A second metal layer is deposited on it. One of the first or second metal layers is pure aluminum or an aluminum alloy that does not contain silicon, and the other layer is an aluminum alloy that contains silicon. The metal layer can also be formed by successively depositing a metal not containing elemental silicon and a metal containing elemental silicon, wherein each deposition is performed at least once. Metals that do not contain silicon absorb silicon atoms from metals that contain silicon when the temperature is lowered. Thus, the formation of silicon deposits on the surface of the semiconductor substrate can be eliminated. In addition, it is easier for silicon-free metals to absorb silicon atoms from silicon-containing metals than for semiconductor substrates, thus effectively eliminating the aluminum peak.

According to another aspect of the present invention, after forming the opening, a barrier layer is formed on the entire surface of the semiconductor wafer in order to prevent a reaction between the metal layer and the semiconductor substrate or the insulating layer. The barrier layer includes a metal compound with a high melting point. The opening may be a contact hole having a step at its upper portion, and its aspect ratio is 1.0 or more.

The metal layer is preferably formed in a vacuum sputtering chamber with a temperature below 150°C. The temperature for heat-treating the metal layer may be 0.8Tm-Tm. All the above-mentioned steps of forming the metal wiring layer are preferably performed in a vacuum, and the vacuum is not turned on between the steps.

Through the following detailed description of the present invention with reference to the accompanying drawings, it will help to better understand the aforementioned purpose of the present invention, in the figures:

Figures 1A, 1B, and 1C depict a prior art method of forming a metal layer (as described in U.S. Patent Application No. 07/585,218);

Figure 2 depicts the silicon deposits formed on the surface of the semiconductor substrate after metallization in the prior art method of Figure 1;

3A-3D represent an embodiment of the method for forming a metal wiring layer according to the present invention;

4A-4D show another method for forming a metal wiring layer according to the present invention.

Example;

Figure 5 is a SEM image showing an opening completely filled with metal formed on a semiconductor substrate obtained according to a method of the present invention;

FIG. 6 depicts a clean semiconductor substrate surface finally obtained according to a method of the present invention.

Description of the preferred embodiment:

Example 1

3A-3D depict one embodiment of a method of forming a metal wiring structure in accordance with the present invention.

Figure 3A depicts a step in forming the first metal layer. More specifically, on a semiconductor substrate (21) with an insulating interlayer (22), an opening (23) with a diameter of 0.8 µm and a stepped portion thereon is formed, and then the substrate (21) is cleaned.

Next, a barrier layer (24) comprising a refractory metal compound such as TiN is deposited on the entire surface of the insulating interlayer (22) and the exposed portion of the semiconductor substrate (21). The thickness of the barrier layer (24) is preferably between 200-1500 Angstroms. Substrate (21) is then placed in a sputtering reaction chamber (not shown among the figure), forms the first metal layer by depositing such as aluminum or the aluminum alloy that does not contain silicon composition at this, and its thickness is whole (composite ) two-thirds of the metal layer (when the period thickness of the entire metal layer is 6000 angstroms, it is 4000 angstroms), its temperature is about 150 ℃, and under a predetermined vacuum level, the first metal layer thus formed has Small aluminum grains and high surface free energy.

Fig. 3 B has described the step of filling opening 23, further say, under the situation of not opening vacuum chamber, semiconductor wafer is moved to another sputtering reaction chamber (not shown among the figure), at this, to the first metal layer (25) Carry out heat treatment, and its temperature is preferably 550 ℃ and lasts 3 minutes, thereby causes aluminum grain to migrate to opening (23), and the migration of aluminum grain causes surface free energy to reduce, thereby makes its surface area reduce and as The opening can be completely filled with aluminum as shown in Figure 3B.

Figure 3C describes the step of forming a second metal layer (26) on the first metal layer (25), more specifically, at a temperature below 350°C, by depositing the rest of the required total thickness of the entire metal layer to form second metal layer (26), thereby completing the formation of the entire metal layer. Aluminum alloys containing silicon such as Al—Si or Al—Cu—Si are used to form the second metal layer (26).

Fig. 3 D has described by using conventional etch process (as known widely used in semiconductor processing technology) to remove the predetermined position of second metal layer (26), first metal layer (25) and barrier layer (24) part of the metal wiring pattern formed.

Example 2

4A-4D illustrate another embodiment of a method of forming a metal wiring pattern according to the present invention.

Fig. 4A has described the step of forming the first metal layer, in more detail, on the semiconductor substrate (31) that has the insulating layer (33) that _SiO2 is made of, form the opening of diameter 0.8 μ m, and have step in its top (35) and then clean the substrate (31). In order to prevent the reaction between the wiring layer and the semiconductor substrate (31) or with the insulating layer (33), on the entire surface of the insulating layer (33) and the exposed part of the semiconductor substrate (31) including the opening (35) , form the first diffusion barrier layer (37) made of Ti; its thickness is preferably between 100-500 angstroms; form the second diffusion barrier layer (39) on the first diffusion barrier layer (37), it is made of TiN Composition (its thickness is preferably between 200-1500 Angstroms).

In the next step, the entire semiconductor wafer is heat-treated in an N ₂ gas environment at a temperature of about 450° C. for half an hour. Then, a first metal layer (41) is deposited on the second diffusion barrier layer (39), preferably with a thickness of 2000-4000 Angstroms, using an alloy such as Al-0.5% Cu. Al—1% Si, or Al—0.5% Cu—1% Si, the heating temperature is 150°C or below, and the method used is either sputtering or vacuum vapor deposition.

Fig. 4B has described a first step of thermally treating the metal layer (41), furthermore, using the gas conduction method without opening the vacuum, at a temperature of 0.8Tm-Tm, at 10 ^-2 Torr or 10 ^-2 In an inert gas below Torr, or in a vacuum of 5 x 10 ^-7 Torr or below 5 x 10 ^-7 Torr, the metal layer (41) is heat-treated for 1-5 minutes.

Fig. 4C has described the step of forming the second metal layer (43), under the condition of not opening the vacuum, the temperature is below 350 ℃, forms the second metal layer on the whole surface of the first metal layer (41), and its thickness is the most Preferably between 2000-4000 Angstroms.

Figure 4D depicts a first second step of heat treating the second metal layer (43) to planarize the surface of the metal layer. This step is performed in the same manner as the first heat treatment step without opening the vacuum. An antireflection layer comprising a transition metal compound such as TiN is thus formed on the surface of the second metal layer (43), preferably in a thickness between 200-500 angstroms. Then, according to a conventional etching process, a metal wiring pattern (not shown in the figure) can be obtained.

According to the principle of the present invention, metal atoms of the metal layer formed on the semiconductor wafer migrate toward the opening when the metal layer is heat-treated. When the metal layer is deposited at a lower temperature, it is easier for the metal atoms to migrate towards the opening during the subsequent heat treatment. In addition, after heat-treating the first deposited metal layer, a second metal layer is deposited at a low temperature and then heat-treated. In this way, a planarized metal layer can be obtained and the subsequent etching steps can be carried out easily and efficiently. Furthermore, according to the invention, by properly treating the second deposited metal layer, the opening can be completely filled with metal. The photomicrograph in Figure 5 depicts the results.

Further, according to the present invention, the metal containing silicon and the metal not containing silicon can be deposited continuously or simultaneously to form a composite metal layer, and when the temperature of the semiconductor substrate is lowered, the metal layer not containing silicon absorbs the metal containing silicon. The silicon atom of the metal layer of the element. Then, after forming the wiring pattern, no silicon precipitate is formed on the surface of the semiconductor device, and the Al peak can be completely eliminated. As shown in FIG. 6, a clean semiconductor substrate surface can be realized, and thus, a reliable metal wiring pattern can be obtained.

Although the invention has been described with reference to particular embodiments, various modifications can be made by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (38)

1. method of making semiconductor device comprises step:

On semiconductor chip 31, form an insulating interlayer 33;

An opening 35 is provided on described insulating interlayer 33;

On described insulating interlayer, form the first metal layer 41;

Described the first metal layer 41 is heat-treated to use the metal filled described opening 35 of described the first metal layer 41;

On described the first metal layer, form one second metal level 43, thereby a complex metal layer is provided; With

The method that is used in the surface planarization of second metal level 43 that makes generation under the temperature in 0.8Tm～Tm scope is heat-treated second metal level 43, and wherein, Tm is the fusing point of the metal of described second metal level.

2. according to the process of claim 1 wherein: described opening 35 extends to the surface of described semiconductor chip 31, thereby exposes the part on described semiconductor chip 31 surfaces; With

The step that forms described the first metal layer is included in the step that forms described the first metal layer 41 above the surface portion of exposure of described insulating interlayer 33 and described semiconductor chip 31.

3. according to the method for claim 2, also comprise the following steps: on the surface of described insulating interlayer 33 and limit on the semiconductor chip 31 of described opening 35 to form diffusion impervious layer 37,39.

4. according to the method for claim 3, wherein, described diffusion impervious layer 37,39 is made of a kind of metal of selecting from comprise transition metal and transistion metal compound.

5. according to the method for claim 3, wherein, described diffusion impervious layer 37,39 is made of the material of selecting from comprise titanium and titanium nitride.

6. according to the method for claim 3, wherein, the formation step of described diffusion impervious layer 37,39 comprises step:

On the semiconductor chip 31 of described insulating interlayer 33 and the described opening 35 of qualification, form first diffusion impervious layer 37; With

On described first diffusion impervious layer 37, form second diffusion impervious layer 39.

7. according to the method for claim 6, wherein, described first barrier layer 37 is made of Ti, and described second barrier layer is made of titanium nitride.

8. according to the method for claim 6, wherein, the thickness on described first barrier layer is 100-500 dusts, and the thickness on second barrier layer is 200-1500 dusts.

9. according to the method for claim 2, wherein, described the first metal layer forms step and comprises: in a vacuum, under the low temperature, metal is deposited on the exposed surface portion thereof of described insulating interlayer 33 and described semiconductor chip 31.

10. according to the method for claim 9, wherein said low temperature is below 150 ℃.

11. according to the process of claim 1 wherein, described to the first metal layer step of heat treatment range of temperature for O.8Tm-carry out under the Tm, wherein Tm is the fusing point of this metal.

12. according to the method for claim 9, wherein, described is to carry out under the condition of not opening vacuum to the first metal layer step of heat treatment.

13. according to the process of claim 1 wherein, the thickness of described the first metal layer 41 is 1/3rd to 2/3rds of described composite bed predetermined thickness.

14. according to the process of claim 1 wherein, described second metal form step be included in temperature be below 350 ℃ the time on described the first metal layer the step of a kind of metal of deposit.

15. according to the process of claim 1 wherein that the thickness of described second metal level 43 is 1/3rd to 2/3rds of described composite bed predetermined thickness.

16. according to the process of claim 1 wherein, all under vacuum, carry out in steps, and do not open vacuum between each step.

17. according to the process of claim 1 wherein, in a kind of inert gas environment, carry out in steps.

18. according to the process of claim 1 wherein, in a kind of reducing gas environment, carry out in steps.

19. according to the method for claim 17, wherein, described step be pressure be equal to or less than 10 the milli torrs inert gas environment in carry out.

20., further be included in the step that forms an anti-reflecting layer 46 on described second metal level according to the method for claim 2.

21. according to the method for claim 20, wherein, described anti-reflecting layer 45 is made of a kind of transistion metal compound.

22. according to the method for claim 21, wherein, described transistion metal compound is a titanium nitride.

23. according to the method for claim 2, wherein, described first and second metal level 41,43 is made of a kind of metal of selecting from the one group of material that comprises aluminium and aluminium alloy.

24. according to the process of claim 1 wherein, described opening 35 is contact holes that a ladder is arranged at an upper portion thereof.

25. according to the process of claim 1 wherein, described the first metal layer 41 is by from aluminium with do not conform to a kind of metal of selecting the aluminium alloy of element silicon and constitute, described second metal level 43 is then by from aluminium with contain a kind of metal of selecting the aluminium alloy of element silicon and constitute.

26. according to the process of claim 1 wherein described the first metal layer 41 by from aluminium with contain a kind of metal of selecting the aluminium alloy of element silicon and constitute, described second metal level 43 is then by from aluminium with do not conform to a kind of metal of selecting the aluminium alloy of element silicon and constitute.

27. a method of making semiconductor device comprises step:

On Semiconductor substrate 21, form an insulating interlayer 22;

On described insulating interlayer 22, form an opening 23 to expose the part surface of described Semiconductor substrate 21;

On that part of surface of the inner surface of described insulating interlayer, described opening 23 and the described Semiconductor substrate that exposes, form metal level 25; And

Described metal level 25 is heat-treated, so that with the described opening 23 of the metal complete filling of described metal level;

Wherein, the metal of described metal level 25 is made of a kind of metal of selecting from the aluminium alloy family of fine aluminium and siliceous composition not.

28., further be included in the step that forms a barrier layer 24 on the whole surface of the described semiconductor wafer that contains the surface that limits described opening 23 according to a kind of method of claim 27.29. a kind of methods according to claim 27, wherein, described aluminium alloy is Al-Cu alloy and Al-Ti alloy.

30. according to a kind of method of claim 27, wherein, described opening 23 comprises and forms a contact hole that a step portion is arranged thereon.

31. according to a kind of method of claim 27, wherein, described metal level forms step and realizes by using sputter procedure a kind of metal of deposit on described semiconductor wafer in a vacuum.

32. according to the process of claim 1 wherein, it is to carry out being equal to or less than under 150 ℃ the temperature that described metal level forms step.

33. according to the method for claim 27, wherein, the aspect ratio of described opening 23 is greater than 1.0.

34. according to the method for claim 27, wherein, described metal level heat treatment step is under vacuum and does not open under the condition of vacuum and carry out in sputtering chamber.

35. according to the method for claim 27, wherein, described metal level heat treatment step is to carry out under its scope is temperature between 80% and the described melting point metal of described melting point metal.

36. according to the method for claim 28, wherein, described barrier layer 24 is made of the high-melting point metal compound.

37. according to the method for claim 36, wherein, described metallic compound is a titanium nitride.

38. according to a kind of method of claim 27, further be included in the step that forms another metal level 26 on the described metal level 25, described another metal level 26 contains element silicon.

39. according to a kind of method of claim 27, wherein, described metal level forms step and comprises use sputtering technology deposit the first metal layer 25 step of deposit second metal level 26 on described the first metal layer 25 again.

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