CN101694835A - Manufacture method of metal layer - Google Patents
Manufacture method of metal layer Download PDFInfo
- Publication number
- CN101694835A CN101694835A CN200910197109A CN200910197109A CN101694835A CN 101694835 A CN101694835 A CN 101694835A CN 200910197109 A CN200910197109 A CN 200910197109A CN 200910197109 A CN200910197109 A CN 200910197109A CN 101694835 A CN101694835 A CN 101694835A
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- CN
- China
- Prior art keywords
- metal layer
- metal level
- manufacture method
- metal
- film layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 83
- 239000002184 metal Substances 0.000 title claims abstract description 83
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000013078 crystal Substances 0.000 claims abstract description 7
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims abstract description 3
- 239000004411 aluminium Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 230000005540 biological transmission Effects 0.000 abstract description 4
- 238000000137 annealing Methods 0.000 abstract description 3
- 239000002245 particle Substances 0.000 abstract 2
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000008719 thickening Effects 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a manufacture method of a metal layer. The method includes the steps: forming a metal film layer; annealing the metal film layer; continually growing to form a metal layer; and annealing the metal layer. The thickness of the metal layer is more than 3micron, the crystal particle formed by the metal layer is more than 25micron and the material of the metal layer is aluminum or aluminum alloy. Compared with the prior art, in the manufacture method, a thinner metal layer is formed firstly and then annealed, grows continually on the basis, thickens and finally is annealed again to form a metal layer with coarser crystal particles, thus reducing the resistance of the metal layer. Moreover, as the formed metal layer is thicker, the resistance of the metal layer is reduced further, thus greatly reducing the interconnection resistance of devices formed by the manufacture method of the metal layer, improving the transmission speed of signals and enhancing the performance of chips.
Description
Technical field
The present invention relates to a kind of manufacture method of metal level, concrete, relate to a kind of manufacture method that is applied in the metal level of semiconductor device.
Background technology
The manufacturing of integrated circuit is divided into two major parts usually: produce active device and passive device earlier on the surface of wafer, this stage is called front (FEOL:front-end-of-line).After finishing the front, need on this wafer, connect each device and different layers with metal, this stage be called the back line (BEOL:back-end-of-line), this stage just on the dielectric film deposited metal and subsequently the mint-mark figure so that form the process of interconnected metal wire.
Along with the increase of chip integration, the corresponding thereupon increase of metal interconnection complexity, and the interconnection resistance that metal interconnection produces also increases thereupon, has reduced the transmission speed of signal, has seriously restricted the performance of chip.
Summary of the invention
The technical problem to be solved in the present invention is: provide a kind of manufacture method of metal level, to reduce metal interconnected resistance.
In order to realize the object of the invention, the invention provides a kind of manufacture method of metal level, comprise step:
Form metal film layer;
This metal film layer is annealed;
Continued growth on the basis of described metal film layer forms metal level;
Described metal level is annealed.
Adopt chemical gas-phase deposition method to form described metal film layer.
Described metal layer thickness is greater than 3 microns.
The crystal grain that described metal level forms is greater than 25 microns.
The material of described metal level is aluminium or aluminium alloy.
The thickness of described metal film layer is 0～1 micron.
Compared with prior art, metal level of the present invention is by forming a relatively thinner metal level earlier, annealing then, continued growth on this basis then, thickening, anneal once more at last, form the relatively metal level of coarse grain, thereby reduce the resistance of described metal level.And, because the metal level that forms is thicker, further reduced the resistance of described metal level, thereby the interconnection resistance of the device that the manufacture method of the described metal level of feasible employing forms reduces greatly, has improved the transmission speed of signal, has improved the performance of chip.
Description of drawings
Fig. 1 is the manufacturing flow chart of the manufacture method of metal level of the present invention.
Embodiment
For clearer understanding technology contents of the present invention, especially exemplified by specific embodiment and cooperate appended graphic being described as follows.
See also Fig. 1, Fig. 1 is the manufacturing flow chart of the manufacture method of metal level of the present invention.
Present embodiment with make metal level in surface of silicon, described metal level is that example describes with aluminium, certainly, the present invention is not limited to make described metal level on the surface of silicon, on the surface of the metal level that will form low-resistance value of also can in officely what is the need for.Described metal level also not only is confined to aluminium, also can be the alloy of aluminium or the metal and the alloy thereof of other low-resistance values.
Step S1: at first on surface of silicon, adopt the method for chemical vapor deposition, form a metal film layer, the thickness of described metal film layer is 0～1 micron.
Step S2: this metal film layer is annealed, make the crystal grain of the metal film layer after annealed become big.
Step S3: continued growth on the basis of described metal film layer, thickening forms metal level, and described metal layer thickness is greater than 3 microns.
Step S4: described metal level is annealed, make the crystal grain of all metal levels become big, the crystal grain of formation is greater than 25 microns.
The metal level that present embodiment forms by forming a relatively thinner metal level earlier, is annealed then, continued growth on this basis then, and thickening is annealed at last once more, forms the relatively metal level of coarse grain, thereby reduces the resistance of described metal level.And, because the metal level that forms is thicker, further reduced the resistance of described metal level, thereby the interconnection resistance of the device that the manufacture method of the described metal level of feasible employing forms reduces greatly, has improved the transmission speed of signal, has improved the performance of chip.
More than show and described basic principle of the present invention, principal character and advantage of the present invention.The technical staff of the industry should understand; the present invention is not restricted to the described embodiments; that describes in the foregoing description and the specification just illustrates principle of the present invention; the present invention also has various changes and modifications without departing from the spirit and scope of the present invention, and these changes and improvements all fall in the claimed scope of the invention.The claimed scope of the present invention is defined by appending claims and equivalent thereof.
Claims (6)
1. the manufacture method of a metal level is characterized in that, comprises step:
Form metal film layer;
This metal film layer is annealed;
Continued growth on the basis of described metal film layer forms metal level;
Described metal level is annealed.
2. the manufacture method of metal level as claimed in claim 1 is characterized in that: adopt chemical gas-phase deposition method to form described metal film layer.
3. the manufacture method of metal level as claimed in claim 1, it is characterized in that: described metal layer thickness is greater than 3 microns.
4. the manufacture method of metal level as claimed in claim 1 is characterized in that: the crystal grain that described metal level forms is greater than 25 microns.
5. the manufacture method of metal level as claimed in claim 1, it is characterized in that: the material of described metal level is aluminium or aluminium alloy.
6. the manufacture method of metal level as claimed in claim 1, it is characterized in that: the thickness of described metal film layer is 0～1 micron.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910197109A CN101694835A (en) | 2009-10-13 | 2009-10-13 | Manufacture method of metal layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910197109A CN101694835A (en) | 2009-10-13 | 2009-10-13 | Manufacture method of metal layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101694835A true CN101694835A (en) | 2010-04-14 |
Family
ID=42093791
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910197109A Pending CN101694835A (en) | 2009-10-13 | 2009-10-13 | Manufacture method of metal layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101694835A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105659388A (en) * | 2013-10-25 | 2016-06-08 | 夏普株式会社 | Photoelectric conversion element, photoelectric conversion module, and solar photovoltaic power generation system |
| CN105659389A (en) * | 2013-10-25 | 2016-06-08 | 夏普株式会社 | A cyclonic separation assembly having a low residence time plenum arranged in a fluidized bed reactor vessel |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1068681A (en) * | 1991-06-27 | 1993-02-03 | 三星电子株式会社 | Method for manufacturing semiconductor device |
| US20040092100A1 (en) * | 2002-11-08 | 2004-05-13 | Taiwan Semiconductor Manufacturing Company | Method to eliminate copper hillocks and to reduce copper stress |
| CN1790663A (en) * | 2004-11-12 | 2006-06-21 | 台湾积体电路制造股份有限公司 | Semiconductor element and method for manufacturing copper wire |
-
2009
- 2009-10-13 CN CN200910197109A patent/CN101694835A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1068681A (en) * | 1991-06-27 | 1993-02-03 | 三星电子株式会社 | Method for manufacturing semiconductor device |
| US20040092100A1 (en) * | 2002-11-08 | 2004-05-13 | Taiwan Semiconductor Manufacturing Company | Method to eliminate copper hillocks and to reduce copper stress |
| CN1790663A (en) * | 2004-11-12 | 2006-06-21 | 台湾积体电路制造股份有限公司 | Semiconductor element and method for manufacturing copper wire |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105659388A (en) * | 2013-10-25 | 2016-06-08 | 夏普株式会社 | Photoelectric conversion element, photoelectric conversion module, and solar photovoltaic power generation system |
| CN105659389A (en) * | 2013-10-25 | 2016-06-08 | 夏普株式会社 | A cyclonic separation assembly having a low residence time plenum arranged in a fluidized bed reactor vessel |
| CN105659388B (en) * | 2013-10-25 | 2018-06-12 | 夏普株式会社 | Photo-electric conversion element, photoelectric conversion module and photovoltaic power generation system |
| CN105659389B (en) * | 2013-10-25 | 2018-10-19 | 夏普株式会社 | Photo-electric conversion element, photoelectric conversion module and photovoltaic power generation system |
| US11031516B2 (en) | 2013-10-25 | 2021-06-08 | Sharp Kabushiki Kaisha | Photoelectric conversion element, photoelectric conversion module, and solar photovoltaic power generation system |
| US11121270B2 (en) | 2013-10-25 | 2021-09-14 | Sharp Kabushiki Kaisha | Photoelectric conversion element, photoelectric conversion module, and solar photovoltaic power generation system |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20100414 |