CN103186361A - CMOS (Complementary Metal-Oxide-Semiconductor) random number generator - Google Patents
CMOS (Complementary Metal-Oxide-Semiconductor) random number generator Download PDFInfo
- Publication number
- CN103186361A CN103186361A CN2011104446569A CN201110444656A CN103186361A CN 103186361 A CN103186361 A CN 103186361A CN 2011104446569 A CN2011104446569 A CN 2011104446569A CN 201110444656 A CN201110444656 A CN 201110444656A CN 103186361 A CN103186361 A CN 103186361A
- Authority
- CN
- China
- Prior art keywords
- cmos
- pipe
- common
- drain electrode
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title abstract description 3
- 230000000295 complement effect Effects 0.000 title abstract 2
- 230000007704 transition Effects 0.000 claims description 12
- 230000003321 amplification Effects 0.000 claims description 2
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Images
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
The invention discloses a CMOS (Complementary Metal-Oxide-Semiconductor) random number generator, which comprises a biasing circuit, a dual-drain CMOS transistor noise current source and a control unit, wherein the biasing circuit is used for providing a direct-current operating point for the dual-drain CMOS transistor noise current source; the dual-drain CMOS transistor noise current source is used for generating noise current signals by adopting a dual-drain CMOS transistor; and the control unit is used for directly amplifying the noise current signals generated by the dual-drain CMOS transistor noise current source and then generating random numbers. The CMOS random number generator has the advantages of simpler circuit structure and lower power consumption.
Description
Technical field
The present invention relates to the randomizer field, relate in particular to a kind of CMOS randomizer.
Background technology
Randomizer is very important part in the anti-collision algorithm of RFID tag, and the noise current source structure that adopts in traditional randomizer is comparatively complicated, and the power consumption that randomizer is caused is also bigger.
Summary of the invention
The invention provides a kind of CMOS randomizer.This CMOS randomizer comprises biasing circuit, two drain electrode CMOS pipe noise current source and control module, and wherein, biasing circuit is used to two drain electrode CMOS pipe noise current sources that dc point is provided; Two drain electrode CMOS pipe noise current sources adopt two drain electrode CMOS pipes to produce the noise current signal; After directly amplifying, the noise current signal that control module produces two drain electrode CMOS pipe noise current sources is converted to random number.
In an embodiment of the present invention, two drain electrode CMOS pipe noise current sources comprise that the two common CMOS that a pair of drain electrode CMOS manages and is connected in two drain electrodes of two drain electrode CMOS pipe manage.
In an embodiment of the present invention, two drain electrode CMOS pipes are two drain electrode PMOS pipes; Two common CMOS pipes comprise the first common NMOS pipe and the second common NMOS pipe; The source electrode of two drain electrode PMOS pipes connects supply voltage, and grid connects described biasing circuit, and two drain electrodes link to each other with the drain electrode of the described first common NMOS pipe, the drain electrode of the second common NMOS pipe respectively; The grid leak utmost point short circuit of the first common NMOS pipe, source ground, grid are an output terminal of described two drain electrode CMOS pipe noise current sources; The grid leak utmost point short circuit of the second common NMOS pipe, source ground, grid are another output terminal of described two drain electrode CMOS pipe noise current sources.
In an embodiment of the present invention, two drain electrode CMOS pipes are two drain electrode NMOS pipes; Two common CMOS pipes comprise the first common PMOS pipe and the second common PMOS pipe; The source ground of two drain electrode NMOS pipes, grid connects described biasing circuit, and two drain electrodes link to each other with the drain electrode of the first common PMOS pipe, the drain electrode of the second common PMOS pipe respectively; The grid leak utmost point short circuit of the first common PMOS pipe, source electrode connects supply voltage, and grid is an output terminal of described two drain electrode CMOS pipe noise current sources; The grid leak utmost point short circuit of the second common PMOS pipe, source electrode connects supply voltage, and grid is another output terminal of described two drain electrode CMOS pipe noise current sources.
In an embodiment of the present invention, control module comprises current processing module and digital signal processing module; After directly amplifying, the noise current signal that the current processing module produces described two drain electrode CMOS pipe noise current sources is converted to digital signal; Digital signal processing module produces random number according to described digital signal.
In an embodiment of the present invention, the current processing module comprises the 3rd common NMOS pipe and the 3rd common PMOS pipe that drains and join and be connected to first node, comprising that also drain electrode is joined and the 4th common NMOS pipe and the 4th common PMOS that are connected to Section Point manages, comprising that also the voltage transitions with described first node or Section Point is the comparison module of digital signal.
In an embodiment of the present invention, the grid of the 3rd common NMOS pipe connects an output terminal of described two drain electrode CMOS pipe noise current sources, and the grid of the 4th common NMOS pipe connects another output terminal of described two drain electrode CMOS pipe noise current sources; The source ground of the source electrode of the 3rd common NMOS pipe and the 4th common NMOS pipe; The source electrode of the source electrode of the 3rd common PMOS pipe and the described the 4th common PMOS pipe connects supply voltage, and grid joins; With the grid leak utmost point short circuit of the 3rd common PMOS pipe, comparison module is digital signal with the voltage transitions of Section Point; Perhaps with the grid leak utmost point short circuit of the 4th common PMOS pipe, comparison module is digital signal with the voltage transitions of first node.
In an embodiment of the present invention, the grid of the 3rd common PMOS connects an output terminal of described two drain electrode CMOS pipe noise current sources, and the grid of the 4th common PMOS pipe connects another output terminal of described two drain electrode CMOS pipe noise current sources respectively; The source electrode of the source electrode of the 3rd common PMOS pipe and the 4th common PMOS pipe connects supply voltage; The source ground of the source electrode of the 3rd common NMOS pipe and the described the 4th common NMOS pipe, grid joins; With the grid leak utmost point short circuit of the 3rd common NMOS pipe, comparison module is digital signal with the voltage transitions of Section Point; Perhaps with the grid leak utmost point short circuit of the 4th common NMOS pipe, comparison module is digital signal with the voltage transitions of first node.
In an embodiment of the present invention, comparison module is comparer or phase inverter.
In an embodiment of the present invention, digital signal processing module is d type flip flop.
This CMOS randomizer adopts two drain electrode CMOS pipe noise current sources to substitute the noise current source that adopts in traditional randomizer, not only can simplify the circuit structure of noise current source, also greatly reduces the power consumption of randomizer.
Description of drawings
The synoptic diagram of the CMOS randomizer that Fig. 1 provides for one embodiment of the invention;
The synoptic diagram of the CMOS randomizer that Fig. 2 provides for another embodiment of the present invention.
Embodiment
By reference to the accompanying drawings the present invention is described in further detail below by embodiment.
As shown in Figure 1, the CMOS randomizer that provides of one embodiment of the invention comprises biasing circuit 11, two drain electrode CMOS pipe noise current source 12 and control module.Wherein, biasing circuit 11 is used to two drain electrode CMOS pipe noise current sources 12 that dc point is provided.Two drain electrode CMOS pipe noise current sources 12 can comprise a pair of drain electrode PMOS pipe (PM0, P type dual-drain CMOS pipe), the first common NMOS pipe (NM1) and the second common NMOS pipe (NM2).Control module can comprise the digital signal processing module that is converted to the current processing module 131 of digital signal after directly amplifying for the noise current signal that two drain electrode CMOS pipe noise current sources 12 are produced and is used for producing according to the digital signal of the output of current processing module 131 random number.The present embodiment digital signal processing module can be a d type flip flop (DFF1).Current processing module 131 can comprise the 3rd common NMOS pipe (NM3) and the 3rd common PMOS pipe (PM3) that drains and join and be connected to first node (A), comprising that also drain electrode joins and be connected to the 4th common NMOS pipe (NM4) and the 4th common PMOS pipe (PM4) of Section Point (B), the voltage transitions that reaches first node (A) or Section Point (B) is the comparison module of digital signal.Comparison module can be a phase inverter (INV1) in the present embodiment.
The source electrode of PM0 connects supply voltage (VDD), and grid connects biasing circuit 11, two drain electrodes and links to each other with the drain electrode of NM1, the drain electrode of NM2 respectively.The grid leak utmost point short circuit of NM1, source ground.The grid leak utmost point short circuit of NM2, source ground.The grid of NM1 connects the grid of NM3.The grid of NM2 connects the grid of NM4.The source electrode of NM3 and the source ground of NM4.The source electrode of PM3 and the source electrode of PM4 meet VDD.The grid of PM3 and the grid of PM4 join.The grid leak utmost point short circuit of PM3, the input end of INV1 is connected to Section Point (B), is digital signal with the voltage transitions of Section Point (B), the INV1 output terminal is connected with the input end S of DFF1, DFF1 by Q or
End output random series.INV1 can be the reverser that a band enables, and the Enable Pin of INV1 is connected clock signal clk respectively with the CK of DFF1 end.
The principle of work of this CMOS randomizer is:
After two drain electrode CMOS pipe noise current sources 12 power on, produce noise current signal Id1, Id2 respectively in two drain electrodes of PM0, though NM1 and NM2 can be size identical two common NMOS pipes, but because the noise effect of metal-oxide-semiconductor, the noise current signal Id1 ' that flows through NM1 is variant with the noise current signal Id2 ' meeting of flowing through NM2, supposes Id1 '+Id2 '=2*Iref.
If Id1 '＜Id2 ', and Id2 '-Id1 '=2 Δ I, Id1 '=Iref-Δ I then, Id2 '=Iref+ Δ I.The size of NM3 and NM4 can be identical, NM3 obtains Id3 after amplifying the noise current signal Id1 ' that flows through NM1 by mirror image, Id3=k*Id1 '=k* (Iref-Δ I), after NM4 flows through the noise current signal Id2 ' of NM2 by the mirror image amplification, can obtain Id4, Id4=k*Id2 '=k* (Iref+ Δ I), the size of PM3 and PM4 can be identical, the electric current of PM4 mirror image PM3, because Id3=k* (Iref-Δ I)＜＜k* (Iref+ Δ I), so flow through actual noise current signal Id4 '=Id3=k* (Iref-Δ I) of NM4, so the voltage VB that B is ordered＜(1/2) * VDD;
Otherwise if Id1 '＞Id2 ' then by above-mentioned deduction, can get VB＞(1/2) * VDD;
INV1 opens under the control of clock signal, detects VB, as if VB＞(1/2) * VDD, then exports the input end S of control signal 0 to DFF1; Otherwise if VB＜(1/2) * VDD then exports the input end S that control signal 1 is given DFF1;
DFF1 is according to the control signal of INV1 output, by Q or QN end output random series.
In the present embodiment, can also be with the grid leak utmost point short circuit of PM4, INV1 is converted to digital signal with the A point voltage.
As shown in Figure 2, the CMOS randomizer structure that the CMOS randomizer that another embodiment of the present invention provides and embodiment one provide is similar, but the former two drain electrode CMOS pipe noise current sources 12 can comprise a pair of drain electrode NMOS pipe (NM0, N-type dual-drain CMOS pipe), the first common PMOS pipe (PM1) and the second common PMOS pipe (PM2).The source ground of NM0, grid connect biasing circuit 11, two drain electrodes and link to each other with the drain electrode of PM1, the drain electrode of PM2 respectively; The grid leak utmost point short circuit of PM1, source electrode meets VDD, the grid leak utmost point short circuit of PM2, source electrode meets VDD, and the grid of PM1 connects the grid of PM3 simultaneously, and the grid of PM2 connects the grid of PM4 simultaneously, and the source electrode of PM3 and PM4 meets VDD; The source ground of NM3 and NM4, grid joins; The grid leak utmost point short circuit of NM3.Same with embodiment one, the input end of INV1 is connected to the B point, and the B point voltage is converted to digital signal, and the INV1 output terminal is connected with the input end S of DFF1, DFF1 by Q or
End output random series.INV1 can be the reverser that a band enables, and the Enable Pin of INV1 is connected clock signal clk respectively with the CK of DFF1 end.The principle of work of this CMOS randomizer is as embodiment one.
In the present embodiment, can also be with the grid leak utmost point short circuit of NM4, INV1 is converted to digital signal with the A point voltage.
Among the present invention, comparison module is including, but not limited to phase inverter, and such as being a comparer, comparer is with A point or B point voltage and reference value comparison, according to comparative result output digital signal; Digital signal processing module of the present invention is including, but not limited to d type flip flop.
The present invention adopts two drain electrode CMOS pipe noise current sources to substitute the noise current source that adopts in traditional randomizer, can simplify the circuit structure of noise current source.The present invention is converted to digital signal after directly the noise current signal being amplified, and after need not earlier to transfer the noise current signal to voltage by voltage conversion circuit, amplifies again, has further simplified circuit structure.The present invention adopts the current processing module to combine with comparison module, has realized easily the conversion of noise current signal to digital signal.
Above content be in conjunction with concrete embodiment to further describing that the present invention does, can not assert that concrete enforcement of the present invention is confined to these explanations.For the general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, can also make some simple deduction or replace, all should be considered as belonging to protection scope of the present invention.
Claims (10)
1. CMOS randomizer comprises:
Two drain electrode CMOS pipe noise current sources, it adopts two drain electrode CMOS pipes to produce the noise current signal;
Biasing circuit, it is used to described two drain electrode CMOS pipe noise current source that dc point is provided; With
Control module, it is used for the noise current signal that described pair of drain electrode CMOS pipe noise current sources produce directly is converted to random number after the amplification.
2. CMOS randomizer as claimed in claim 1 is characterized in that, described two drain electrode CMOS pipe noise current sources comprise that the two common CMOS that a pair of drain electrode CMOS manages and is connected in two drain electrodes of described two drain electrode CMOS pipe manage.
3. CMOS randomizer as claimed in claim 2 is characterized in that, described two drain electrode CMOS pipes are two drain electrode PMOS pipes; Described two common CMOS pipes comprise the first common NMOS pipe and the second common NMOS pipe;
The source electrode of described two drain electrode PMOS pipes connects supply voltage, and grid connects described biasing circuit, and two drain electrodes link to each other with the drain electrode of the described first common NMOS pipe, the drain electrode of the second common NMOS pipe respectively;
The grid leak utmost point short circuit of the first common NMOS pipe, source ground, grid are an output terminal of described two drain electrode CMOS pipe noise current sources; The grid leak utmost point short circuit of the second common NMOS pipe, source ground, grid are another output terminal of described two drain electrode CMOS pipe noise current sources.
4. CMOS randomizer as claimed in claim 2 is characterized in that, described two drain electrode CMOS pipes are two drain electrode NMOS pipes; Described two common CMOS pipes comprise the first common PMOS pipe and the second common PMOS pipe;
The source ground of described two drain electrode NMOS pipes, grid connects described biasing circuit, and two drain electrodes link to each other with the drain electrode of the first common PMOS pipe, the drain electrode of the second common PMOS pipe respectively;
The grid leak utmost point short circuit of the first common PMOS pipe, source electrode connects supply voltage, and grid is an output terminal of described two drain electrode CMOS pipe noise current sources; The grid leak utmost point short circuit of the second common PMOS pipe, source electrode connects supply voltage, and grid is another output terminal of described two drain electrode CMOS pipe noise current sources.
5. as each described CMOS randomizer of claim 1 to 4, it is characterized in that described control module comprises current processing module and digital signal processing module; After directly amplifying, the noise current signal that described current processing module produces described two drain electrode CMOS pipe noise current sources is converted to digital signal; Digital signal processing module produces random number according to described digital signal.
6. CMOS randomizer as claimed in claim 5 is characterized in that, described digital signal processing module is d type flip flop.
7. CMOS randomizer as claimed in claim 5, it is characterized in that, described current processing module comprises the 3rd common NMOS pipe and the 3rd common PMOS pipe that drains and join and be connected to first node, the 4th common NMOS pipe and the 4th common PMOS pipe that drain and join and be connected to Section Point, the voltage transitions that reaches described first node or Section Point is the comparison module of digital signal.
8. CMOS randomizer as claimed in claim 7, it is characterized in that, the grid of the described the 3rd common NMOS pipe connects an output terminal of described two drain electrode CMOS pipe noise current sources, and the grid of the described the 4th common NMOS pipe connects another output terminal of described two drain electrode CMOS pipe noise current sources;
The source ground of the source electrode of the described the 3rd common NMOS pipe and the 4th common NMOS pipe;
The source electrode of the source electrode of the described the 3rd common PMOS pipe and the described the 4th common PMOS pipe connects supply voltage, and grid joins;
With the grid leak utmost point short circuit of the described the 3rd common PMOS pipe, comparison module is digital signal with the voltage transitions of described Section Point; Perhaps with the grid leak utmost point short circuit of the described the 4th common PMOS pipe, comparison module is digital signal with the voltage transitions of described first node.
9. CMOS randomizer as claimed in claim 7, it is characterized in that, the grid of described the 3rd common PMOS connects an output terminal of described two drain electrode CMOS pipe noise current sources, and the grid of the described the 4th common PMOS pipe connects another output terminal of described two drain electrode CMOS pipe noise current sources respectively;
The source electrode of the source electrode of the described the 3rd common PMOS pipe and the 4th common PMOS pipe connects supply voltage;
The source ground of the source electrode of the described the 3rd common NMOS pipe and the described the 4th common NMOS pipe, grid joins;
With the grid leak utmost point short circuit of the described the 3rd common NMOS pipe, comparison module is digital signal with the voltage transitions of described Section Point; Perhaps with the grid leak utmost point short circuit of the described the 4th common NMOS pipe, comparison module is digital signal with the voltage transitions of described first node.
10. CMOS randomizer as claimed in claim 7 is characterized in that, described comparison module is comparer or phase inverter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110444656.9A CN103186361B (en) | 2011-12-27 | 2011-12-27 | CMOS randomizers |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110444656.9A CN103186361B (en) | 2011-12-27 | 2011-12-27 | CMOS randomizers |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103186361A true CN103186361A (en) | 2013-07-03 |
| CN103186361B CN103186361B (en) | 2017-07-04 |
Family
ID=48677540
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110444656.9A Active CN103186361B (en) | 2011-12-27 | 2011-12-27 | CMOS randomizers |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103186361B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104679476A (en) * | 2015-03-11 | 2015-06-03 | 大唐微电子技术有限公司 | Noise type random number generation device |
| CN109284084A (en) * | 2018-08-06 | 2019-01-29 | 温州大学 | A True Random Number Generator Without Capacitive Coupling Effect |
| CN109375898A (en) * | 2018-11-26 | 2019-02-22 | 弦海（上海）量子科技有限公司 | Quantum True Random Number Generator chip and method based on CMOS detection |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2185494Y (en) * | 1993-06-09 | 1994-12-14 | 张曼卿 | Controller for decorative lamps |
| US20070033242A1 (en) * | 1995-02-14 | 2007-02-08 | Wilber Scott A | Random number generator and generation method |
| CN101188402A (en) * | 2007-12-20 | 2008-05-28 | 北京航空航天大学 | A low voltage mixer |
| CN101202532A (en) * | 2006-12-13 | 2008-06-18 | 中国科学院半导体研究所 | Complementary type metal oxidizing layer semiconductor noise generator |
| CN101833434A (en) * | 2009-03-13 | 2010-09-15 | 国民技术股份有限公司 | CMOS (Complementary Metal Oxide Semiconductor) random number generator |
| CN102095917A (en) * | 2010-11-30 | 2011-06-15 | 西安电子科技大学 | Test method for current noise of high-resistance device and medium material |
-
2011
- 2011-12-27 CN CN201110444656.9A patent/CN103186361B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2185494Y (en) * | 1993-06-09 | 1994-12-14 | 张曼卿 | Controller for decorative lamps |
| US20070033242A1 (en) * | 1995-02-14 | 2007-02-08 | Wilber Scott A | Random number generator and generation method |
| CN101202532A (en) * | 2006-12-13 | 2008-06-18 | 中国科学院半导体研究所 | Complementary type metal oxidizing layer semiconductor noise generator |
| CN101188402A (en) * | 2007-12-20 | 2008-05-28 | 北京航空航天大学 | A low voltage mixer |
| CN101833434A (en) * | 2009-03-13 | 2010-09-15 | 国民技术股份有限公司 | CMOS (Complementary Metal Oxide Semiconductor) random number generator |
| CN102095917A (en) * | 2010-11-30 | 2011-06-15 | 西安电子科技大学 | Test method for current noise of high-resistance device and medium material |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104679476A (en) * | 2015-03-11 | 2015-06-03 | 大唐微电子技术有限公司 | Noise type random number generation device |
| CN104679476B (en) * | 2015-03-11 | 2018-01-16 | 大唐微电子技术有限公司 | Noisy-type generating random number device |
| CN109284084A (en) * | 2018-08-06 | 2019-01-29 | 温州大学 | A True Random Number Generator Without Capacitive Coupling Effect |
| CN109284084B (en) * | 2018-08-06 | 2023-03-21 | 温州大学 | True random number generator without capacitive coupling effect |
| CN109375898A (en) * | 2018-11-26 | 2019-02-22 | 弦海（上海）量子科技有限公司 | Quantum True Random Number Generator chip and method based on CMOS detection |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103186361B (en) | 2017-07-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105471425B (en) | A kind of achievable XOR gate or the circuit with OR gate multiplexing | |
| CN106230416B (en) | It is a kind of with active clamp without bootstrapping gate driving circuit | |
| US7368955B2 (en) | Current-balanced logic circuit | |
| CN105187030B (en) | Oscillator | |
| CN102025352A (en) | Hysteresis voltage comparator | |
| CN206193580U (en) | LDO circuit | |
| CN102930891A (en) | Reading circuit | |
| CN103795401A (en) | Output unit circuit with controllable output level | |
| CN103186361A (en) | CMOS (Complementary Metal-Oxide-Semiconductor) random number generator | |
| WO2017167177A1 (en) | High-speed, high-swing driver circuit suitable for use in silicon optical modulator | |
| CN105103444B (en) | Signal output apparatus | |
| CN103138741B (en) | A kind of ultra-low power consumption level shift circuit | |
| CN102904432B (en) | Drive control circuit of synchronous switch power switching system | |
| TWI502306B (en) | Current-to-voltage converter and electronic apparatus thereof | |
| CN106712765B (en) | A PECL Transmitter Interface Circuit Based on CMOS Technology | |
| CN105375916A (en) | Improved XOR gate logic unit circuit | |
| CN102571069A (en) | Single-power-supply positive and negative logic conversion circuit | |
| CN101764596A (en) | Inbuilt miicromicro farad stage capacitance intermittent microcurrent second-level time delay circuit | |
| CN103457554A (en) | Rail-to-rail operation amplifier | |
| TWI225333B (en) | Class D amplifier | |
| CN102545849A (en) | Self-adaptive input hysteresis comparator | |
| CN205265661U (en) | Can realize that anticoincidence gate is perhaps with multiplexing circuit of disjunction gate | |
| CN102109869A (en) | Driving circuit | |
| CN101944903A (en) | The CMOS input buffer circuit | |
| CN107517045B (en) | Ring oscillator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |