CN103094087B - The method of etching groove polysilicon gate - Google Patents
The method of etching groove polysilicon gate Download PDFInfo
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- CN103094087B CN103094087B CN201110340515.2A CN201110340515A CN103094087B CN 103094087 B CN103094087 B CN 103094087B CN 201110340515 A CN201110340515 A CN 201110340515A CN 103094087 B CN103094087 B CN 103094087B
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- polysilicon
- groove
- etch rate
- gate
- etch
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 51
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 51
- 238000005530 etching Methods 0.000 title claims abstract description 26
- 238000000034 method Methods 0.000 title claims abstract description 23
- 238000000151 deposition Methods 0.000 claims abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 5
- 239000010703 silicon Substances 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000001312 dry etching Methods 0.000 claims abstract description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- Drying Of Semiconductors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a kind of method of etching groove polysilicon gate, comprise the following steps: the first step, at the epitaxial loayer etching groove of silicon substrate upper front, growth gate oxide, then depositing polysilicon; Second step, adopts isotropic dry etch polysilicon, and in etching process, etch rate is vertically downward identical with the etch rate of horizontal direction or close; 3rd step, adopts anisotropic dry etch polysilicon, is returned by polysilicon and carves to groove top, make the polysilicon outside groove be etched totally; In etching process, etch rate is vertically downward much larger than the etch rate of horizontal direction.The present invention adopts two step dry etchings after the deposit of trench polysilicon Si-gate, polysilicon gate in groove can be made greatly to improve to the degree of lower recess, thus improve the pattern of polysilicon gate in groove.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor device, be specifically related to a kind of method of etching groove polysilicon gate.
Background technology
Existing trench-gate power devices, at the epitaxial loayer etching groove of silicon substrate upper front, growth gate oxide, then depositing polysilicon, finally remove the polysilicon outside groove by anisotropic dry etch, the polysilicon stayed in groove serves as the grid of device.After depositing polysilicon, the polysilicon of groove overcentre can to lower recess.
The trench-gate power devices that this anisotropic lithographic method is formed, can make the polysilicon in groove a lot of to lower recess, as shown in Figure 1 after etching.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of method of etching groove polysilicon gate, and in the groove that it can improve trench-gate power devices, polysilicon gate is to the degree of lower recess.
For solving the problems of the technologies described above, the technical solution of the method for etching groove polysilicon gate of the present invention is comprise the following steps:
The first step, at the epitaxial loayer etching groove of silicon substrate upper front, growth gate oxide, then depositing polysilicon;
Second step, adopts isotropic dry etch polysilicon, and in etching process, etch rate is vertically downward identical with the etch rate of horizontal direction or close;
Described etch rate is vertically downward less than two times of the etch rate of horizontal direction.
3rd step, adopts anisotropic dry etch polysilicon, is returned by polysilicon and carves to groove top, make the polysilicon outside groove be etched totally; In etching process, etch rate is vertically downward greater than the etch rate of horizontal direction.
Described etch rate is vertically downward greater than two times of the etch rate of horizontal direction.
The technique effect that the present invention can reach is:
The present invention adopts two step dry etchings after the deposit of trench polysilicon Si-gate, polysilicon gate in groove can be made greatly to improve to the degree of lower recess, thus improve the pattern of polysilicon gate in groove.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the pattern sectional view of the trench-gate power devices formed by prior art;
Fig. 2 to Fig. 4 is the structural representation corresponding to each step of the method for etching groove polysilicon gate of the present invention.
Embodiment
The method of etching groove polysilicon gate of the present invention, comprises the following steps:
The first step, as shown in Figure 2, conventionally trench-gate power devices technique, at the epitaxial loayer etching groove of silicon substrate upper front, growth gate oxide, then depositing polysilicon, make it fill up and exceed the degree of depth of groove, forming polysilicon gate;
Second step, as shown in Figure 3, adopts isotropic dry etch polysilicon, and in etching process, etch rate is vertically downward identical with the etch rate of horizontal direction or close;
Etch rate is vertically downward less than two times of the etch rate of horizontal direction.
After polysilicon deposition, the pattern out-of-flatness of its groove upper surface, makes the polysilicon of top in the middle part of groove to lower recess; The present invention first adopts isotropic dry etch, and after etching, the polysilicon surface of groove overcentre obviously reduces to the degree of lower recess;
3rd step, as shown in Figure 4, adopts anisotropic dry etch polysilicon, and in etching process, etch rate is vertically downward greater than the etch rate of horizontal direction; Returned by polysilicon and carve to groove top, the polysilicon outside groove is etched totally.
Etch rate is vertically downward greater than two times of the etch rate of horizontal direction.
Claims (3)
1. a method for etching groove polysilicon gate, is characterized in that, after groove depositing polysilicon grid, polysilicon is successively carried out to two step dry etchings of isotropic dry etch, anisotropic dry etch, to improve the pattern of polysilicon gate in groove; Comprise the following steps:
The first step, at the epitaxial loayer etching groove of silicon substrate upper front, growth gate oxide, then depositing polysilicon;
Second step, adopts isotropic dry etch polysilicon, and in etching process, etch rate is vertically downward identical with the etch rate of horizontal direction or close;
3rd step, adopts anisotropic dry etch polysilicon, is returned by polysilicon and carves to groove top, make the polysilicon outside groove be etched totally; In etching process, etch rate is vertically downward greater than the etch rate of horizontal direction.
2. the method for etching groove polysilicon gate according to claim 1, is characterized in that, in described second step, etch rate is vertically downward less than two times of the etch rate of horizontal direction.
3. the method for etching groove polysilicon gate according to claim 1 and 2, is characterized in that, in described 3rd step, etch rate is vertically downward greater than two times of the etch rate of horizontal direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110340515.2A CN103094087B (en) | 2011-11-01 | 2011-11-01 | The method of etching groove polysilicon gate |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110340515.2A CN103094087B (en) | 2011-11-01 | 2011-11-01 | The method of etching groove polysilicon gate |
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| Publication Number | Publication Date |
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| CN103094087A CN103094087A (en) | 2013-05-08 |
| CN103094087B true CN103094087B (en) | 2015-08-19 |
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| CN201110340515.2A Active CN103094087B (en) | 2011-11-01 | 2011-11-01 | The method of etching groove polysilicon gate |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104658937B (en) * | 2013-11-20 | 2017-06-09 | 北大方正集团有限公司 | A kind of method for determining trench VDMOS device gate oxide breakdown voltage |
| CN106252218A (en) * | 2016-09-30 | 2016-12-21 | 上海华虹宏力半导体制造有限公司 | Trench MOSFET grid etch process |
| CN107611027A (en) * | 2017-08-16 | 2018-01-19 | 江苏鲁汶仪器有限公司 | A kind of method for improving deep silicon etching sidewall roughness |
| CN109686663A (en) * | 2018-12-27 | 2019-04-26 | 上海华力微电子有限公司 | A kind of semiconductor structure and its manufacturing method |
| CN111524802B (en) * | 2020-04-30 | 2022-10-04 | 华虹半导体(无锡)有限公司 | Polysilicon gate etching method for MOS device with SGT structure |
| CN112838009B (en) * | 2021-01-11 | 2022-08-26 | 广州粤芯半导体技术有限公司 | Manufacturing method of shielded gate trench power device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1416175A (en) * | 2001-10-17 | 2003-05-07 | 硅存储技术公司 | Memory array self-alignment method and memory array for forming floating gate memory cells |
| KR100505604B1 (en) * | 1998-05-28 | 2005-09-26 | 삼성전자주식회사 | Trench isolating method |
| CN1757117A (en) * | 2003-03-05 | 2006-04-05 | 先进模拟科技公司 | Trench Power Metal-Oxide-Semiconductor Field-Effect Transistor with Planarized Gate Bus |
| CN1893111A (en) * | 2005-05-12 | 2007-01-10 | 谢福渊 | Elimination of gate oxide weak spot in deep trench |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1126513A1 (en) * | 2000-02-16 | 2001-08-22 | Semiconductor 300 GmbH & Co. KG | Process for planarization and recess etching of polysilicon in an overfilled trench |
| US7204934B1 (en) * | 2001-10-31 | 2007-04-17 | Lam Research Corporation | Method for planarization etch with in-situ monitoring by interferometry prior to recess etch |
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- 2011-11-01 CN CN201110340515.2A patent/CN103094087B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100505604B1 (en) * | 1998-05-28 | 2005-09-26 | 삼성전자주식회사 | Trench isolating method |
| CN1416175A (en) * | 2001-10-17 | 2003-05-07 | 硅存储技术公司 | Memory array self-alignment method and memory array for forming floating gate memory cells |
| CN1757117A (en) * | 2003-03-05 | 2006-04-05 | 先进模拟科技公司 | Trench Power Metal-Oxide-Semiconductor Field-Effect Transistor with Planarized Gate Bus |
| CN1893111A (en) * | 2005-05-12 | 2007-01-10 | 谢福渊 | Elimination of gate oxide weak spot in deep trench |
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| CN103094087A (en) | 2013-05-08 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140109 |
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Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
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Effective date of registration: 20140109 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
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