CN103094087A - Method of etching groove polycrystalline silicon gate - Google Patents
Method of etching groove polycrystalline silicon gate Download PDFInfo
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- CN103094087A CN103094087A CN2011103405152A CN201110340515A CN103094087A CN 103094087 A CN103094087 A CN 103094087A CN 2011103405152 A CN2011103405152 A CN 2011103405152A CN 201110340515 A CN201110340515 A CN 201110340515A CN 103094087 A CN103094087 A CN 103094087A
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- groove
- polycrystalline silicon
- polysilicon
- etching
- etch rate
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 50
- 238000005530 etching Methods 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title claims abstract description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 5
- 239000010703 silicon Substances 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 229920005591 polysilicon Polymers 0.000 claims description 38
- 238000000151 deposition Methods 0.000 claims description 5
- 238000001035 drying Methods 0.000 abstract 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a method of etching a groove polycrystalline silicon gate. The method of etching the groove polycrystalline silicon gate comprises the following steps: firstly, a groove is etched in an extension layer above the front side of a silicon substrate, a gate oxide layer is developed and the polycrystalline silicon is deposited. Secondly, the polycrystalline silicon is etched by using an isotropy drying method. The etching rate in the perpendicular and downward direction is the same with or close to the etching rate in the horizontal direction in the etching process. Thirdly, the polycrystalline silicon is etched by using the isotropy drying method. The polycrystalline silicon is etched back to the top portion of the groove, thus the polycrystalline silicon outside the groove is etched cleanly. The etching rate in the perpendicular and downward direction is much larger than the etching rate in the horizontal direction in the etching process. The groove polycrystalline silicon gate is etched by using a two-step drying method after the groove polycrystalline silicon gate is deposited. Degree of sinking downward of the polycrystalline silicon gate in the groove can be greatly improved, thus features of the polycrystalline silicon gate in the groove are improved.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor device, be specifically related to a kind of method of etching groove polysilicon gate.
Background technology
Existing trench-gate power devices, the epitaxial loayer etching groove above the silicon substrate front, growth gate oxide, then depositing polysilicon remove the polysilicon of groove outside at last with anisotropic dry etch, stay the grid that polysilicon in groove serves as device.After depositing polysilicon, the polysilicon above the ditch groove center can be to lower recess.
This with the formed trench-gate power devices of anisotropic lithographic method, can make the polysilicon in groove a lot of to lower recess after etching, as shown in Figure 1.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of method of etching groove polysilicon gate, and it can improve the interior polysilicon gate of groove of trench-gate power devices to the degree of lower recess.
For solving the problems of the technologies described above, the technical solution of the method for etching groove polysilicon gate of the present invention is, comprises the following steps:
The first step, the epitaxial loayer etching groove above the silicon substrate front, growth gate oxide, then depositing polysilicon;
Second step adopts the isotropic dry etch polysilicon, and in etching process, vertically downward etch rate is identical or approaching with the etch rate of horizontal direction;
Described etch rate vertically downward is less than two times of the etch rate of horizontal direction.
The 3rd step, adopt the anisotropic dry etch polysilicon, polysilicon is returned carve to the groove top, the outer polysilicon of groove is etched totally; In etching process, vertically downward etch rate is greater than the etch rate of horizontal direction.
Described etch rate vertically downward is greater than two times of the etch rate of horizontal direction.
The technique effect that the present invention can reach is:
The present invention adopts two step dry etchings after the deposit of groove polysilicon gate, the interior polysilicon gate of groove is improved greatly to the degree of lower recess, thereby improves the pattern of polysilicon gate in groove.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 is the pattern sectional view with the formed trench-gate power devices of prior art;
Fig. 2 to Fig. 4 is the corresponding structural representation of each step with the method for etching groove polysilicon gate of the present invention.
Embodiment
The method of etching groove polysilicon gate of the present invention comprises the following steps:
The first step, as shown in Figure 2, according to prior art trench-gate power devices technique, the epitaxial loayer etching groove above the silicon substrate front, the growth gate oxide, depositing polysilicon then fills up it and surpasses the degree of depth of groove, the formation polysilicon gate;
Second step as shown in Figure 3, adopts the isotropic dry etch polysilicon, and in etching process, vertically downward etch rate is identical or approaching with the etch rate of horizontal direction;
Etch rate vertically downward is less than two times of the etch rate of horizontal direction.
After the polysilicon deposit, the pattern out-of-flatness of its groove upper surface makes the polysilicon of top, groove middle part to lower recess; The present invention first adopts isotropic dry etch, and after etching, the polysilicon surface of ditch groove center top obviously reduces to the degree of lower recess;
The 3rd step, as shown in Figure 4, adopt the anisotropic dry etch polysilicon, in etching process, vertically downward etch rate is greater than the etch rate of horizontal direction; Polysilicon is returned carve to the groove top, the outer polysilicon of groove is etched totally.
Etch rate vertically downward is greater than two times of the etch rate of horizontal direction.
Claims (3)
1. the method for an etching groove polysilicon gate, is characterized in that, comprises the following steps:
The first step, the epitaxial loayer etching groove above the silicon substrate front, growth gate oxide, then depositing polysilicon;
Second step adopts the isotropic dry etch polysilicon, and in etching process, vertically downward etch rate is identical or approaching with the etch rate of horizontal direction;
The 3rd step, adopt the anisotropic dry etch polysilicon, polysilicon is returned carve to the groove top, the outer polysilicon of groove is etched totally; In etching process, vertically downward etch rate is greater than the etch rate of horizontal direction.
2. the method for etching groove polysilicon gate according to claim 1, is characterized in that, in described second step, vertically downward etch rate is less than two times of the etch rate of horizontal direction.
3. the method for etching groove polysilicon gate according to claim 1 and 2, is characterized in that, in described the 3rd step, vertically downward etch rate is greater than two times of the etch rate of horizontal direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110340515.2A CN103094087B (en) | 2011-11-01 | 2011-11-01 | The method of etching groove polysilicon gate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110340515.2A CN103094087B (en) | 2011-11-01 | 2011-11-01 | The method of etching groove polysilicon gate |
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| Publication Number | Publication Date |
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| CN103094087A true CN103094087A (en) | 2013-05-08 |
| CN103094087B CN103094087B (en) | 2015-08-19 |
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| CN201110340515.2A Active CN103094087B (en) | 2011-11-01 | 2011-11-01 | The method of etching groove polysilicon gate |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104658937A (en) * | 2013-11-20 | 2015-05-27 | 北大方正集团有限公司 | Method for measuring breakdown voltage of gate oxide layer of groove type VDMOS device |
| CN106252218A (en) * | 2016-09-30 | 2016-12-21 | 上海华虹宏力半导体制造有限公司 | Trench MOSFET grid etch process |
| CN107611027A (en) * | 2017-08-16 | 2018-01-19 | 江苏鲁汶仪器有限公司 | A kind of method for improving deep silicon etching sidewall roughness |
| CN109686663A (en) * | 2018-12-27 | 2019-04-26 | 上海华力微电子有限公司 | A kind of semiconductor structure and its manufacturing method |
| CN111524802A (en) * | 2020-04-30 | 2020-08-11 | 华虹半导体(无锡)有限公司 | Polysilicon gate etching method for MOS device with SGT structure |
| CN112838009A (en) * | 2021-01-11 | 2021-05-25 | 广州粤芯半导体技术有限公司 | Manufacturing method of shielded gate trench power device |
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| US20030022510A1 (en) * | 2000-02-16 | 2003-01-30 | Thomas Morgenstern | Process for planarization and recess etching of integrated circuits |
| CN1416175A (en) * | 2001-10-17 | 2003-05-07 | 硅存储技术公司 | Memory array self-alignment method and memory array for forming floating gate memory cells |
| CN1582490A (en) * | 2001-10-31 | 2005-02-16 | 拉姆研究公司 | Method for planarization etch with in-situ monitoring by interferometry prior to recess etch |
| KR100505604B1 (en) * | 1998-05-28 | 2005-09-26 | 삼성전자주식회사 | Trench isolating method |
| CN1757117A (en) * | 2003-03-05 | 2006-04-05 | 先进模拟科技公司 | Trench Power Metal-Oxide-Semiconductor Field-Effect Transistor with Planarized Gate Bus |
| CN1893111A (en) * | 2005-05-12 | 2007-01-10 | 谢福渊 | Elimination of gate oxide weak spot in deep trench |
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2011
- 2011-11-01 CN CN201110340515.2A patent/CN103094087B/en active Active
Patent Citations (6)
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|---|---|---|---|---|
| KR100505604B1 (en) * | 1998-05-28 | 2005-09-26 | 삼성전자주식회사 | Trench isolating method |
| US20030022510A1 (en) * | 2000-02-16 | 2003-01-30 | Thomas Morgenstern | Process for planarization and recess etching of integrated circuits |
| CN1416175A (en) * | 2001-10-17 | 2003-05-07 | 硅存储技术公司 | Memory array self-alignment method and memory array for forming floating gate memory cells |
| CN1582490A (en) * | 2001-10-31 | 2005-02-16 | 拉姆研究公司 | Method for planarization etch with in-situ monitoring by interferometry prior to recess etch |
| CN1757117A (en) * | 2003-03-05 | 2006-04-05 | 先进模拟科技公司 | Trench Power Metal-Oxide-Semiconductor Field-Effect Transistor with Planarized Gate Bus |
| CN1893111A (en) * | 2005-05-12 | 2007-01-10 | 谢福渊 | Elimination of gate oxide weak spot in deep trench |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104658937A (en) * | 2013-11-20 | 2015-05-27 | 北大方正集团有限公司 | Method for measuring breakdown voltage of gate oxide layer of groove type VDMOS device |
| CN104658937B (en) * | 2013-11-20 | 2017-06-09 | 北大方正集团有限公司 | A kind of method for determining trench VDMOS device gate oxide breakdown voltage |
| CN106252218A (en) * | 2016-09-30 | 2016-12-21 | 上海华虹宏力半导体制造有限公司 | Trench MOSFET grid etch process |
| CN107611027A (en) * | 2017-08-16 | 2018-01-19 | 江苏鲁汶仪器有限公司 | A kind of method for improving deep silicon etching sidewall roughness |
| CN109686663A (en) * | 2018-12-27 | 2019-04-26 | 上海华力微电子有限公司 | A kind of semiconductor structure and its manufacturing method |
| CN111524802A (en) * | 2020-04-30 | 2020-08-11 | 华虹半导体(无锡)有限公司 | Polysilicon gate etching method for MOS device with SGT structure |
| CN111524802B (en) * | 2020-04-30 | 2022-10-04 | 华虹半导体(无锡)有限公司 | Polysilicon gate etching method for MOS device with SGT structure |
| CN112838009A (en) * | 2021-01-11 | 2021-05-25 | 广州粤芯半导体技术有限公司 | Manufacturing method of shielded gate trench power device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103094087B (en) | 2015-08-19 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140109 |
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Effective date of registration: 20140109 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
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