CN102944974B - Mask plate and array substrate manufacturing method - Google Patents

Abstract

An embodiment of the present invention provides a method for manufacturing a mask plate and an array substrate, which relates to the field of manufacturing thin-film transistor liquid crystal displays, which can increase the amount of photoresist that needs to be developed in the fan-out wire area and reduce the concentration of the developer to avoid fan-out wires. The TFT near the lead-out region loses its switching characteristics after etching, which improves the yield of the product. The mask plate of the present invention includes a substrate, a first pattern area and a second pattern area arranged on the substrate, the second pattern area corresponds to the fan-out wire area of the array substrate, and the second pattern area includes a partial transmission area and a total transmission area area, when etching the source and drain layers of the fan-out wire region, the partial transmission area makes the photoresist coated on the source and drain layer develop and form a part of the photoresist remaining area, and the total transmission area makes the coating on the source After the photoresist on the drain layer is developed, a photoresist completely removed region is formed, the photoresist partially reserved region corresponds to the fan-out wire, and the photoresist completely removed region corresponds to the space between the fan-out wires.

Description

Method for manufacturing mask plate and array substrate

technical field

The invention relates to the field of manufacturing thin film transistor liquid crystal displays, in particular to a method for manufacturing a mask plate and an array substrate.

Background technique

With the continuous advancement of technology, users' demand for liquid crystal display equipment is increasing, and TFT-LCD (Thin Film Transistor-Liquid Crystal Display, Thin Film Field Effect Transistor Liquid Crystal Display) has also become the mainstream display used in mobile phones, tablet computers and other products .

In the layout of the entire TFT-LCD array substrate, the data lines in the pixel area are relatively sparse, and the fan-out wires in the fan-out area are very dense. In the existing process of making fan-out wires, when etching the source and drain layers, the photoresist corresponding to the interval between the fan-out wires is fully exposed, and the photoresist corresponding to the fan-out wires is fully exposed. No exposure is performed, so that during development, the photoresist developed in the fan-out wire area is far less than the photoresist developed in the pixel area, because the concentration of the developer will increase with the reaction between the developer and the photoresist. gradually decreases, so the concentration of the developer in the fan-out wire area will be higher than that in the pixel area, which will cause the photoresist corresponding to the TFT channel area near the fan-out wire area to be easily overdeveloped, and the photoresist Thin or developed, resulting in the loss of switching characteristics of the etched TFT, low product yield.

Contents of the invention

Embodiments of the present invention provide a method for manufacturing a mask plate and an array substrate, which can increase the amount of photoresist that needs to be developed in the fan-out wire area and reduce the concentration of the developer, so as to avoid TFTs near the fan-out wire area The switching characteristics are lost after etching, which improves the yield of products.

In order to achieve the above object, embodiments of the present invention adopt the following technical solutions:

The present invention provides a mask plate, including a substrate, a first pattern area and a second pattern area arranged on the substrate, the first pattern area corresponds to the pixel area of the array substrate, and the second pattern area corresponds to the fan-out of the array substrate wire area,

The second pattern area includes a partial transmission area and a total transmission area. When etching the source and drain layers of the fan-out wire area, the partial transmission area makes the photolithography coated on the source and drain layers A photoresist partly retained region is formed after the glue is developed, and the total transmission region makes the photoresist coated on the source and drain layers be developed to form a photoresist completely removed region, wherein the photoresist The partially reserved areas correspond to the fan-out wires, and the photoresist completely removed areas correspond to spaces between the fan-out wires.

The partially transmissive area is provided with a mask material layer.

The mask material layer is chromium, molybdenum, titanium metal oxide or nitride layer.

The substrate is a glass substrate, a quartz substrate or a sapphire substrate.

The present invention also provides a method for manufacturing an array substrate, including:

forming a source and drain layer on the substrate;

Coating photoresist on the source-drain layer;

Use a mask with any of the above features to expose the photoresist, and after development, the area corresponding to the partial transmission area of the second pattern area forms a photoresist partial retention area, which is related to the total transmission area of the second pattern area. The corresponding area forms a photoresist completely removed area;

An etching process is used to etch the source and drain layers corresponding to the photoresist completely removed region.

A method for manufacturing a mask plate and an array substrate provided by the present invention, the mask plate includes a substrate, a first pattern area and a second pattern area arranged on the substrate, the first pattern area corresponds to the pixel area of the array substrate, and the second pattern area The second pattern area corresponds to the fan-out wiring area of the array substrate, wherein the second pattern area includes a partial transmission area and a total transmission area. When the source and drain layers of the fan-out wiring area are etched, the partial transmission area makes it possible to coat The photoresist on the drain layer is developed to form a photoresist partially reserved area, and the total transmission area makes the photoresist coated on the source and drain layers developed to form a photoresist completely removed area, wherein the photoresist part The reserved areas correspond to the fan-out wires, and the photoresist completely removed areas correspond to the spaces between the fan-out wires. Through this solution, since the second pattern area of the mask includes a semi-transmissive area and a full-transmissive area, when etching the source-drain layer of the fan-out wire area, the partially-transmissive area makes the coating on the source-drain layer After the photoresist is developed, the photoresist is partially retained, and the total transmission area makes the photoresist coated on the source and drain layers developed to form a photoresist completely removed area. Compared with the prior art, the photoresist is completely retained. For the region and the region where the photoresist is completely removed, the amount of photoresist that needs to be developed in the fan-out wire region is increased, and the concentration of the developer is reduced, thereby avoiding the overdevelopment of the TFT channel region near the fan-out wire region. The switching characteristic is lost after etching, which improves the yield rate of the product.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

Fig. 1 is the structural representation of the mask plate provided by the present invention;

FIG. 2 is a top view of the fan-out wiring area of the array substrate;

FIG. 3 is a side view of the fan-out wiring area of the array substrate;

Fig. 4 is a schematic flow chart of the manufacturing method of the array substrate provided by the present invention;

FIG. 5 is a schematic diagram of a fan-out wire structure in the process of etching the source and drain layers provided by the present invention;

FIG. 6 is a second schematic diagram of the fan-out wire structure in the process of etching the source and drain layers provided by the present invention;

FIG. 7 is a schematic flow chart of the manufacturing method of the mask plate provided by the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

It should be noted that "upper" and "lower" in the embodiments of the present invention are only used to describe the embodiments of the present invention with reference to the drawings, and are not used as limiting terms.

The mask plate 1 provided by the embodiment of the present invention, as shown in FIG. 1 , includes:

The substrate 10, the first pattern area and the second pattern area 11 arranged on the substrate 10, the first pattern area corresponds to the pixel area of the array substrate, the second pattern area 11 corresponds to the fan-out wire area of the array substrate, and the first pattern area corresponds to the fan-out wire area of the array substrate. The second pattern area 11 includes a partial transmission area 110 and a total transmission area 111. When the source and drain layers of the fan-out wiring area are etched, the partial transmission area 110 makes the light coated on the source and drain layers After the development of the resist, a photoresist partly retained region is formed, and the total transmission region 111 makes the photoresist coated on the source and drain layers form a photoresist completely removed region after development, wherein the photoresist The partly remaining regions of the resist correspond to the fan-out wires, and the completely removed regions of the photoresist correspond to the spaces between the fan-out wires.

Further, the partial transmission area is provided with a mask material layer.

Further, the mask material layer can be a translucent chromium, molybdenum, titanium metal oxide or nitride layer, specifically, it can be a multi-chromium oxide layer, or it can be a transparent heat-resistant polymer material, a polymer, etc. .

Further, the substrate is a glass substrate, a quartz substrate or a sapphire substrate.

As shown in Figure 2 and Figure 3, Figure 2 is a top view of the fan-out wire area of the array substrate, and Figure 2 is a side view of the fan-out wire area of the array substrate, in Figure 2 and Figure 3, the shaded part is the fan-out wire, and the rest Section is the space between the fanout wires.

A mask plate provided by the present invention includes a substrate, a first pattern area and a second pattern area arranged on the substrate, the first pattern area corresponds to the pixel area of the array substrate, and the second pattern area corresponds to the sector of the array substrate. Outlet line area, wherein, the second pattern area includes a partial transmission area and a total transmission area, when etching the source and drain layer of the fan-out line area, the partial transmission area makes the photoresist coated on the source and drain layer develop Afterwards, a partly reserved region of photoresist is formed, and the total transmission region makes the photoresist coated on the source-drain layer developed to form a completely removed region of photoresist, wherein, the partly reserved region of photoresist corresponds to the fan-out wire, and the photoresist The resist completely removed area corresponds to the space between the fan-out wires. Through this solution, since the second pattern area of the mask includes a semi-transmissive area and a full-transmissive area, when etching the source-drain layer of the fan-out wire area, the partially-transmissive area makes the coating on the source-drain layer After the photoresist is developed, the photoresist is partially retained, and the total transmission area makes the photoresist coated on the source and drain layers developed to form a photoresist completely removed area. Compared with the prior art, the photoresist is completely retained. For the region and the region where the photoresist is completely removed, the amount of photoresist that needs to be developed in the fan-out wire region is increased, and the concentration of the developer is reduced, thereby avoiding the overdevelopment of the TFT channel region near the fan-out wire region. The switching characteristic is lost after etching, which improves the yield rate of the product.

In the process of preparing the fan-out wire of the array substrate, when etching the source and drain layers of the fan-out wire area, the mask plate provided by the embodiment of the present invention is used. The mask plate includes a substrate, and the first pattern area set on the substrate And the second pattern area, the first pattern area corresponds to the pixel area of the array substrate, the second pattern area corresponds to the fan-out wire area of the array substrate, and the second pattern area includes a partial transmission area and a total transmission area.

Exemplarily, as shown in FIG. 4 , an embodiment of the present invention provides a method for manufacturing an array substrate, using the mask plate provided in the above embodiment, the method includes:

S101, forming a source and drain layer on a substrate.

The mask plate provided by the embodiment of the present invention is used to etch the source and drain layers of the fan-out wiring region. Therefore, in step S101 it is exemplarily proposed that the source and drain layers are formed on the substrate. In the actual production process, the source and drain layers The electrode layer can be formed on the substrate (thin film transistor with top gate structure), or on the gate insulating layer (thin film transistor with bottom gate structure), which is not limited in the present invention.

S102 , coating photoresist on the source and drain layers.

As shown in FIG. 5 , after the source and drain layers 21 are formed on the substrate 20 , a photoresist 23 is coated on the source and drain layers 21 .

S103. Use a mask to expose the photoresist. After development, the area corresponding to the partial transmission area of the second pattern area forms a partially reserved area of photoresist, and the area corresponding to the full transmission area of the second pattern area forms a photoresist. Glue completely removes the area.

As shown in Figure 6, use the mask plate 1 to expose the photoresist 23 (that is, photolithography), use the developer to develop the photoresist 23, and form the photoresist part retention area 230 and the photoresist after development. Region 231 is completely removed.

It should be noted that, compared with the formation of the photoresist completely retained region and the photoresist completely removed region in the prior art, step S103 increases the amount of photoresist that needs to be developed when developing the photoresist with the developing solution. The amount, thereby reducing the concentration of the developer.

Among them, photolithography technology is the basis for constructing semiconductor MOS (Metal-Oxide-Semiconductor, Metal-Oxide-Semiconductor) tubes and circuits on a flat substrate, which includes many steps and processes. For example, first coat a layer of corrosion-resistant photoresist on the silicon wafer, and then allow strong light to shine on the substrate through a hollow mask plate engraved with a circuit pattern. The photoresist in the irradiated part (such as the source region and the drain region) will deteriorate, but the place where the pattern is constructed (such as the gate region) will not be irradiated, so the photoresist will still adhere to it. The next step is to clean the silicon wafer with a corrosive liquid, and the deteriorated photoresist is removed to expose the underlying substrate, while the gate area will not be affected under the protection of the photoresist.

S104 , using an etching process to etch the photoresist to completely remove the source and drain layers corresponding to the region.

Furthermore, after using an etching process to etch the source and drain layers corresponding to the photoresist to completely remove the region, and remove the remaining photoresist, the fabrication of the source and drain layers of the fan-out wires is completed.

A method for manufacturing an array substrate provided by the present invention includes a substrate, forming a source and drain layer on the substrate, and coating a photoresist on the source and drain layer in a part of the transmission area, using the mask provided in the above embodiment to The film plate exposes the photoresist in the partial transmission area, and after development, the area corresponding to the partial transmission area of the second pattern area forms a photoresist partial retention area, and the area corresponding to the full transmission area of the second pattern area forms a photoresist completely removing the region: using an etching process to etch the source and drain layers of the partly transmitting region corresponding to the completely removed region of the photoresist in the partly transmitting region. Through this solution, since the second pattern area of the mask includes a semi-transmissive area and a full-transmissive area, when etching the source-drain layer of the fan-out wire area, the partially-transmissive area makes the coating on the source-drain layer After the photoresist is developed, the photoresist is partially retained, and the total transmission area makes the photoresist coated on the source and drain layers developed to form a photoresist completely removed area. Compared with the prior art, the photoresist is completely retained. For the region and the region where the photoresist is completely removed, the amount of photoresist that needs to be developed in the fan-out wire region is increased, and the concentration of the developer is reduced, thereby avoiding the overdevelopment of the TFT channel region near the fan-out wire region. The switching characteristic is lost after etching, which improves the yield rate of the product.

An embodiment of the present invention provides a method for manufacturing a mask, including forming a mask material layer on a substrate as a partial transmission area of a second pattern area, wherein the second pattern area corresponds to the fan-out of the array substrate In the wire area, the second pattern area includes the partial transmission area and the total transmission area, the partial transmission area corresponds to the fan-out wire, and the total transmission area corresponds to the interval between the fan-out wires.

Exemplarily, as shown in FIG. 7 , the method for forming a mask material layer on the substrate as a partial transmission region of the second pattern region includes:

S201. Using a deposition process, deposit a mask material layer on the second pattern area of the substrate.

Wherein, the mask material layer is a chromium, molybdenum, titanium metal oxide or nitride layer, specifically, it may be a multi-chromium oxide layer, or it may be a transparent heat-resistant polymer material, a polymer, or the like.

S202. Coating a photoresist on the mask material layer by using a coating process.

S203. Using a photolithography process, remove the photoresist in the total transmission area of the second pattern area after development.

S204. Using an etching process, etch the mask material layer corresponding to the total transmission area of the second pattern area.

S205 , removing the remaining photoresist through a stripping process.

So far, the mask plate 1 as shown in FIG. 1 has been produced, including a substrate 10, a first pattern area and a second pattern area 11 arranged on the substrate 10, the first pattern area corresponds to the pixel area of the array substrate, and the second pattern area 11 is arranged on the substrate 10. The second pattern area 11 corresponds to the fan-out wiring area of the array substrate. The second pattern area 11 includes a partial transmission area 110 and a total transmission area 111. When etching the source and drain layers of the fan-out wiring area, the partial transmission area 110 makes the coating The photoresist covering the source-drain layer is developed to form a partially-retained region of the photoresist, and the total transmission region 111 makes the photoresist coated on the source-drain layer developed to form a completely removed region of photoresist, wherein, The photoresist partially reserved area corresponds to the fan-out wires, and the photoresist completely removed area corresponds to the space between the fan-out wires.

A method for manufacturing a mask plate provided by the present invention includes forming a mask material layer on a substrate as a partial transmission area of a second pattern area, wherein the second pattern area corresponds to the fan-out wire area of the array substrate, The second pattern area includes a partial transmission area and a total transmission area. The partial transmission area corresponds to the fan-out wire, and the total transmission area corresponds to the interval between the fan-out wires. When etching the source and drain layers of the fan-out wire area, the partial The transmissive area makes the photoresist coated on the source and drain layers develop to form a photoresist partially reserved area, and the total transmission area makes the photoresist coated on the source and drain layers developed to form a photoresist completely removed area , wherein the photoresist partially reserved region corresponds to the fan-out wires, and the photoresist completely removed region corresponds to the space between the fan-out wires. Through this solution, since the second pattern area of the mask includes a semi-transmissive area and a full-transmissive area, when etching the source-drain layer of the fan-out wire area, the partially-transmissive area makes the coating on the source-drain layer After the photoresist is developed, the photoresist is partially retained, and the total transmission area makes the photoresist coated on the source and drain layers developed to form a photoresist completely removed area. Compared with the prior art, the photoresist is completely retained. For the region and the region where the photoresist is completely removed, the amount of photoresist that needs to be developed in the fan-out wire region is increased, and the concentration of the developer is reduced, thereby avoiding the overdevelopment of the TFT channel region near the fan-out wire region. The switching characteristic is lost after etching, which improves the yield rate of the product.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (3)

1. A mask plate for manufacturing an array substrate, comprising a substrate, a first pattern area and a second pattern area arranged on the substrate, the first pattern area corresponds to the pixel area of the array substrate, and the second pattern area Corresponding to the fan-out wire area of the array substrate, it is characterized in that, The second pattern area includes a partial transmission area and a total transmission area. When etching the source and drain layers of the fan-out wire area, the partial transmission area makes the photolithography coated on the source and drain layers A photoresist partly retained region is formed after the glue is developed, and the total transmission region makes the photoresist coated on the source and drain layers be developed to form a photoresist completely removed region, wherein the photoresist The partially reserved area corresponds to the fan-out wires, and the photoresist completely removed area corresponds to the space between the fan-out wires; The partial transmission area is provided with a mask material layer; The mask material layer is polymer material. 2. The mask plate according to claim 1, wherein the substrate is a glass substrate, a quartz substrate or a sapphire substrate. 3. A method for manufacturing an array substrate, comprising: forming a source and drain layer on the substrate; Coating photoresist on the source-drain layer; Use the mask plate described in claim 1 or 2 to expose the photoresist, and after development, the area corresponding to the partial transmission area of the second pattern area forms a part of the photoresist reserved area, which is consistent with the entire area of the second pattern area. The area corresponding to the transmission area forms a photoresist completely removed area; An etching process is used to etch the source and drain layers corresponding to the photoresist completely removed region.